litex.git
2020-08-14 Florent Kermarrecsoc/integration/csr_bridge: use registered version... master
2020-08-13 Florent Kermarrecinterconnect/wishbone/Wishbone2CSR: add registered...
2020-08-13 Florent Kermarrecbuild/lattice/diamond: use diamondc instead of pnmainc...
2020-08-13 Dolu1990cores/cpu/vexriscv_smp fix argument parsing
2020-08-11 Florent Kermarrecbios/main/sdram: fix speed reporting (Mbps/pin not...
2020-08-10 enjoy-digitalMerge pull request #627 from gsomlo/gls-dma-addr-64
2020-08-10 Gabriel Somlocores/dma, liblitesdcard/sdcard: use 64 bits for dma...
2020-08-07 Florent Kermarrecsoftware/bios: display SDRAM databits and freq.
2020-08-07 Florent Kermarreccpu/vexriscv_smp: more coherent_dma to __init__ instead...
2020-08-07 Florent Kermarreccores/cpu: add external cpu_type.
2020-08-06 Florent Kermarrectargets: use platform.request_all on LedChaser.
2020-08-06 Florent Kermarrecbuild/generic_platform: add request_all method.
2020-08-06 Florent Kermarreccores/cpu/zynq7000: simplify using new loose parameter...
2020-08-06 enjoy-digitalMerge pull request #624 from trabucayre/emio_zynq
2020-08-06 Florent Kermarrecbuild/generic_plaform: add loose parameter to return...
2020-08-06 enjoy-digitalMerge pull request #625 from scanakci/blackparrot_litex
2020-08-06 Florent Kermarrecintegration/soc/add_etherbone: pass phy to ethcore...
2020-08-06 sadullahupdate BlackParrot transducer
2020-08-06 sadullahBlackparrot human name update
2020-08-06 Gwenhael Goavec... soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio...
2020-08-06 enjoy-digitalMerge pull request #623 from Dolu1990/vexriscv_smp
2020-08-06 Dolu1990cpu/vexriscv_smp Add --with-coherent-dma
2020-08-05 Florent Kermarrecintegration/soc/add_sdram: update rules to connect...
2020-08-05 Florent Kermarreccpu/vexriscv_smp: fix args_read.
2020-08-05 Florent Kermarreccpu/vexriscv_smp: cleanup, fix coherent_dma connection.
2020-08-05 enjoy-digitalMerge pull request #622 from antmicro/fix_connectors
2020-08-05 Florent Kermarrecsoc/interconnect/axi: minor cleanups.
2020-08-05 Florent Kermarrecinterconnect/stream: set default AsyncFIFO depth to...
2020-08-05 Pawel Saganarty: Change USB-uart and I2S Pmod configuration
2020-08-05 Florent Kermarrecinterconnect/csr: add CSR registers ordering support.
2020-08-05 Florent Kermarrecsoc/interconnect/csr: improve ident.
2020-08-04 Florent Kermarrecintegration/soc: add expection on decoder when full...
2020-08-04 Florent Kermarrecwishbone: revert default adr_width to 30.
2020-08-04 Florent Kermarrectools/litex_json2dts: add missing copyrights.
2020-08-04 Florent Kermarrecsetup: add litex_json2dts to console_scripts.
2020-08-04 enjoy-digitalMerge pull request #620 from antmicro/add_litex_json2dts
2020-08-04 Florent Kermarrecbuild/sim/config: add default_clk/default_clk_freq...
2020-08-04 Florent Kermarrecbuild/sim: use json_object_get_int64 instead of json_ob...
2020-08-04 enjoy-digitalMerge pull request #619 from antmicro/jboc/sim-clocker
2020-08-04 Mateusz Holenkojson2dts: Add Linux DT generation script
2020-08-04 Jędrzej Boczarbuild/sim: improve timebase calculation (strict checks...
2020-08-04 Florent Kermarreccores/uart: add txempty/rxfull CSRs.
2020-08-04 Florent Kermarrectools/litex_server: enable read_merger with CommUDP.
2020-08-04 Florent Kermarrectest: specify wishbone adr_width on AXI(Lite)<-->Wishbo...
2020-08-04 enjoy-digitalMerge pull request #617 from gsomlo/gls_rocket_dma
2020-08-03 Gabriel Somlodebug: make CI print offending values
2020-08-03 Gabriel Somloliblitesdcard/sdcard: (temporarily) slow down SDCARD_CL...
2020-08-03 Gabriel Somlocores/cpu/rocket: expose slave port for DMA
2020-08-03 Gabriel Somlointegration/soc: make DMA slave region cover (at least...
2020-08-03 Gabriel Somlointerconnect/wishbone: increase WB address width to 31
2020-08-03 Gabriel Somlosoc/interconnect/axi: add Wishbone2AXI converter
2020-08-03 Florent Kermarreccores/gpio: add support for Record on GPIOOut, GPIOIn...
2020-08-03 Jędrzej Boczarbuild/sim: allow for arbitrary clocks generation using...
2020-08-03 Jędrzej Boczarbuild/sim: use a real timebase in the simulation
2020-08-03 enjoy-digitalMerge pull request #615 from pepijndevos/openfpgaloader
2020-08-01 Pepijn de Vosremove debugging
2020-08-01 Pepijn de Vosadd openFPGAloader programmer
2020-07-31 Florent Kermarreccpu/vexriscv/core: use variant name as human_name.
2020-07-31 Florent Kermarreccpu/vexriscv/system.h: provide empty flush_cpu_i/dcache...
2020-07-30 Florent Kermarreccpu/zynq7000: set csr map to 0x00000000.
2020-07-30 enjoy-digitalMerge pull request #611 from antmicro/jboc/axi-lite
2020-07-30 Florent Kermarrectools/litex_server/read_merger: review/simplify a bit.
2020-07-30 enjoy-digitalMerge pull request #605 from cklarhorst/feature-uart...
2020-07-30 Jędrzej Boczarsoc/interconnect/axi: add AXILite -> AXI converter
2020-07-30 Florent Kermarreccpu/blackparrot: minor cleanups, add sim variant (since...
2020-07-29 enjoy-digitalMerge pull request #610 from Dolu1990/vexriscv_smp
2020-07-29 Dolu1990soc/cores/cpu/vexriscv_smp enable dynamic litedram...
2020-07-29 Dolu1990Merge branch 'master' into vexriscv_smp
2020-07-29 Florent Kermarrecintegration/soc/add_sdram: allow the CPU to add the...
2020-07-29 Florent Kermarreccores/cpu/rocket: add use_memory_bus parameter to easil...
2020-07-28 Dolu1990Merge branch 'master' into vexriscv_smp
2020-07-28 Dolu1990soc/cores/cpu/vexriscv_smp config update
2020-07-28 Florent KermarrecCHANGES: update.
2020-07-28 Florent Kermarreccpu/vexriscv_smp: move litedram import, remove os.path...
2020-07-28 Florent Kermarreclitex_setup: fix vexriscv-smp repository.
2020-07-28 enjoy-digitalMerge pull request #607 from Dolu1990/vexriscv_smp
2020-07-28 Dolu1990soc/cores/cpu/vexriscv_smp integration
2020-07-28 Florent Kermarrecliblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.
2020-07-27 Florent Kermarrecintegration/soc/etherbone: expose ethcore (useful to...
2020-07-27 Florent Kermarrecintegration/soc: fix dma_bus typo.
2020-07-26 Christian KlarhorstMerge sequential reads for the UART litex_server backend
2020-07-24 Florent Kermarrectargets: keep in sync with litex-boards.
2020-07-24 enjoy-digitalMerge pull request #604 from antmicro/jboc/axi-lite
2020-07-24 Jędrzej Boczarsoc/interconnect/axi: add basic AXI Lite up-converter
2020-07-24 Sean CrossMerge pull request #603 from enjoy-digital/socdoc-exten...
2020-07-24 Sean Crossdoc: socdoc: document new `sphinx_extra_config` parameter
2020-07-24 enjoy-digitalMerge pull request #602 from enjoy-digital/socdoc-exten...
2020-07-24 Sean Crosslitex: add `sphinx_extra_config` to `generate_docs()`
2020-07-24 Sean Crossdoc: socdoc: document `sphinx_extensions` parameter
2020-07-24 Jędrzej Boczarsoc/interconnect/axi: separate AXI Lite converter channels
2020-07-23 Florent KermarrecCHANGES: update.
2020-07-23 Florent Kermarreccore/cpu: integrate Zynq as a classical CPU (Zynq7000...
2020-07-22 Florent Kermarrecliblitesdcard/sdcard: use max divider of 256 (128 was...
2020-07-22 Florent KermarrecCHANGES: update.
2020-07-22 enjoy-digitalMerge pull request #600 from antmicro/jboc/axi-lite
2020-07-22 Florent Kermarrecsoc: add initial DMA bus support (optionally provided...
2020-07-22 Jędrzej Boczartest/axi: move all AXI Lite tests to separate file
2020-07-22 Jędrzej Boczarsoc/integration: use AXILiteSRAM when using bus_standar...
2020-07-22 Jędrzej Boczartest/axi: add crossbar stress tests
2020-07-22 Jędrzej Boczarsoc/integration: add bus standard parser arguments
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