5 NEXTPNR ?
= nextpnr-ecp5
13 uart_files
= $(wildcard ..
/uart16550
/rtl
/verilog
/*.v
)
16 VERILATOR_ROOT
=$(shell verilator
-getenv VERILATOR_ROOT
2>/dev
/null
)
17 ifeq (, $(VERILATOR_ROOT
))
19 $(error
"Verilator is required to make this target !")
29 #RAM_INIT_FILE=hello_world/hello_world.bin
30 RAM_INIT_FILE
=coldboot
/coldboot.bin
35 #RAM_INIT_FILE=micropython/firmware.bin
38 #MEMORY_SIZE=536870912
39 #RAM_INIT_FILE=dtbImage.microwatt.bin
41 SIM_BRAM_CHAINBOOT
=6291456 # 0x600000
43 FPGA_TARGET ?
= verilator
45 ifeq ($(FPGA_TARGET
), verilator
)
48 CLK_FREQUENCY
=100000000
49 clkgen
=fpga
/clk_gen_bypass.vhd
53 python3 src
/ls2.py sim
$(RAM_INIT_FILE
)
55 # Need to investigate why yosys is hitting verilator warnings,
56 # and eventually turn on -Wall
57 microwatt-verilator
: ls2.v \
58 verilator
/microwatt-verilator.
cpp \
59 verilator
/uart-verilator.c
60 verilator
-O3
-CFLAGS
"-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
64 --cc external_core_top.v \
65 --exe verilator
/microwatt-verilator.
cpp verilator
/uart-verilator.c \
66 -o
$@
-I..
/uart16550
/rtl
/verilog \
67 -Wno-fatal
-Wno-CASEOVERLAP
-Wno-UNOPTFLAT \
74 # --unroll-count 256 \
75 # --output-split 5000 \
76 # --output-split-cfuncs 500 \
77 # --output-split-ctrace 500 \
78 make
-C obj_dir
-f Vtop.mk
79 @cp
-f obj_dir
/microwatt-verilator microwatt-verilator
82 rm -fr obj_dir microwatt-verilator ls2.v