comment out reset signal for iverilog simulation
authorTobias Platen <tplaten@posteo.de>
Sun, 7 Aug 2022 17:56:34 +0000 (19:56 +0200)
committerTobias Platen <tplaten@posteo.de>
Sun, 7 Aug 2022 17:56:34 +0000 (19:56 +0200)
commitba7d6761286ec2ea6e47b89de5dc0599bf7a6f34
treeaf2ab18d997a42703a7b072f8ae7e046d17cbceb
parent7a2b18ad502aa7880aa64c429e397f92dbd4cb09
comment out reset signal for iverilog simulation
src/simsoctb.v