| 9 days ago |
Cesar Strauss | ls2: add support for the Nexys Video board master |
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| 10 days ago |
Cesar Strauss | ls2: avoid using DRIVE attribute on Xilinx devices... |
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| 10 days ago |
Cesar Strauss | ls2: fix keyword for declaring pin voltage type on... |
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| 2022-11-22 |
Tobias Platen | coldboot: add lfsr.h by Anton Blanchard |
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| 2022-11-20 |
Tobias Platen | add mode registers macro for orangecrab, extracted... |
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| 2022-09-13 |
Tobias Platen | undo deletion of line defining toolchain for orangecrab |
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| 2022-09-12 |
Tobias Platen | add core_clk_freq variable |
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| 2022-08-07 |
Tobias Platen | comment out reset signal for iverilog simulation |
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| 2022-08-03 |
Tobias Platen | more work on orangecrab dram |
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| 2022-07-20 |
Tobias Platen | merge part 2 of Cesar's patch |
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| 2022-07-15 |
Tobias Platen | optionally add ECLKBRIDGECS to ECP5CRG |
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| 2022-07-06 |
Tobias Platen | fixed KeyError for rcs_arctic_tern_bmc_card |
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| 2022-06-30 |
Tobias Platen | set dram_clk_freq to None |
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| 2022-05-17 |
Tobias Platen | orangecrab: don't use async. set to 50 mhz. |
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| 2022-05-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2022-05-15 |
Tobias Platen | set dram_clk_freq = 100.0e6 for orangecrab |
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| 2022-05-04 |
Luke Kenneth... | pass in freq setting to nextpnr-xilinx |
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| 2022-05-04 |
Luke Kenneth... | add micron n25q 128mb QSPI device to table of |
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| 2022-05-04 |
Luke Kenneth... | add tercel speed-up but missing id for arty a7 at the... |
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| 2022-05-03 |
Tobias Platen | begin dram support for ls2 |
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| 2022-05-02 |
Tobias Platen | add spi for orangecrab |
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| 2022-04-30 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2022-04-30 |
Tobias Platen | change frequency for orangecrab, correct uart output |
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| 2022-04-30 |
Luke Kenneth... | nope, 24 mhz works, 27 does not |
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| 2022-04-30 |
Luke Kenneth... | update arty a7 clock frequency to 27 mhz, works with... |
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| 2022-04-30 |
Luke Kenneth... | update length of program being copied and update |
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| 2022-04-26 |
Tobias Platen | add Wno-TIMESCALEMOD |
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| 2022-04-24 |
Luke Kenneth... | doh |
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| 2022-04-24 |
Luke Kenneth... | list of hyperrams not just one |
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| 2022-04-22 |
Luke Kenneth... | read 2nd word of signature |
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| 2022-04-22 |
Luke Kenneth... | move hyperram to 0x0000_00000 and 0x2000_0000 |
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| 2022-04-22 |
Luke Kenneth... | add second hyperram module, for arty-a7, |
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| 2022-04-16 |
Luke Kenneth... | put versa_ecp5 back to synchronous at 50 mhz to test... |
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| 2022-04-16 |
Luke Kenneth... | remove stall from WBASyncBridges on master side |
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| 2022-04-16 |
Luke Kenneth... | get runsimsoc2.sh running again, test asynchronous... |
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| 2022-04-16 |
Luke Kenneth... | attempting to get VERSA_ECP5 and Icarus Sim to work... |
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| 2022-04-16 |
Luke Kenneth... | add in extra delay-for-core in ECP5CRG |
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| 2022-04-16 |
Tobias Platen | orangecrab: set clock frequency, remove ignored iostandard |
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| 2022-04-15 |
Luke Kenneth... | comment about UARTResource for orangecrab |
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| 2022-04-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2022-04-15 |
Tobias Platen | add orangecrab uart and toolchain |
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| 2022-04-15 |
Luke Kenneth... | checking simulation of Async DDR3 |
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| 2022-04-15 |
Luke Kenneth... | work-in-progress |
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| 2022-04-15 |
Luke Kenneth... | reorg of the ECP5 Clock-Reset to be able to add |
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| 2022-04-15 |
Tobias Platen | whitespace |
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| 2022-04-15 |
Tobias Platen | add orangecrab to list of supported boards |
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| 2022-04-14 |
Luke Kenneth... | reduce versa_ecp5 clock freq to 50 mhz, reduce bit... |
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| 2022-04-14 |
Luke Kenneth... | add default args in DDR3SoC |
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| 2022-04-14 |
Luke Kenneth... | put fw_addr back to 0xff00_0000, xics.bin test passed |
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| 2022-04-14 |
Luke Kenneth... | move firmware to address 0x0 to test microwatt xics.bin |
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| 2022-04-14 |
Luke Kenneth... | wrap QSPI exploration in SYSCON check for QSPI |
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| 2022-04-14 |
Luke Kenneth... | add DELAYG to icarus sim |
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| 2022-04-14 |
Luke Kenneth... | bleh. add XICS_ICS and XICS_ICP but the patch is |
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| 2022-04-14 |
Luke Kenneth... | flash read-and-dump |
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| 2022-04-14 |
Luke Kenneth... | code-comments for when ASyncBridge is deployed |
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| 2022-04-14 |
Luke Kenneth... | add new dram_clk_freq argument which does nothing for now |
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| 2022-04-14 |
Luke Kenneth... | add an extra domain dramsync2x in preparation for |
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| 2022-04-14 |
Luke Kenneth... | add a dramsync2x domain as well |
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| 2022-04-14 |
Luke Kenneth... | move 2x-clock-and-dividing into separate function in... |
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| 2022-04-13 |
Luke Kenneth... | annoying, coldboot.bin getting too big to fit into... |
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| 2022-04-13 |
Luke Kenneth... | get microwatt-verilator sim running at different boot... |
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| 2022-04-12 |
Luke Kenneth... | GAH jump to start of SPI Flash not the offset *in* SPI |
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| 2022-04-12 |
Luke Kenneth... | move flash-first-phase-initialisation to separate function |
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| 2022-04-12 |
Luke Kenneth... | make hello_world relocatable with BOOT_INIT_BASE define |
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| 2022-04-12 |
Luke Kenneth... | add comments on locations where async bridge needs... |
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| 2022-04-11 |
Luke Kenneth... | even more speedup possible on QSPI |
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| 2022-04-11 |
Luke Kenneth... | hack offset into boot address as well |
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| 2022-04-11 |
Luke Kenneth... | hmm go back to mtspr for now, also add explicit loading... |
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| 2022-04-11 |
Luke Kenneth... | too big, shift down to 2MB offset |
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| 2022-04-11 |
Luke Kenneth... | fix coldboot to boot from return address |
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| 2022-04-11 |
Luke Kenneth... | hmm getting flags sorted out on coldboot link |
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| 2022-04-11 |
Luke Kenneth... | annoying, read from wrong offset in SPI FLASH |
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| 2022-04-11 |
Luke Kenneth... | make DRAM init conditional on whether it is detected... |
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| 2022-04-11 |
Luke Kenneth... | put versa_ecp5 below 50 mhz as a bodge-way to stop... |
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| 2022-04-11 |
Luke Kenneth... | set start to _start in hello_world lds script |
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| 2022-04-11 |
Luke Kenneth... | sigh dump memory *at* address, not address itself |
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| 2022-04-11 |
Luke Kenneth... | dump start of copied memory |
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| 2022-04-11 |
Luke Kenneth... | speed up QSPI by putting it into way-faster mode |
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| 2022-04-10 |
Luke Kenneth... | need to merge in tercel flash code |
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| 2022-04-10 |
Luke Kenneth... | Revert "Wire up missing CRG / DDR3 clock control /... |
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| 2022-04-10 |
Luke Kenneth... | Revert "Put sysclk2x back under system reset control" |
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| 2022-04-10 |
Luke Kenneth... | attempting to sort out what looks like a stack overflow |
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| 2022-04-10 |
Raptor Engineering... | Put sysclk2x back under system reset control |
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| 2022-04-09 |
Luke Kenneth... | add QSPI dump back in (smaller one) to check it is... |
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| 2022-04-09 |
Raptor Engineering... | Wire up missing CRG / DDR3 clock control / reset signals |
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| 2022-04-09 |
Luke Kenneth... | sigh use MEMORY_BASE which is at 0x0000_0000 and coinci... |
commit | commitdiff | tree |
| 2022-04-09 |
Luke Kenneth... | shuffle addresses around a bit |
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| 2022-04-08 |
Luke Kenneth... | add DRAM offset into SYSCON and jump to DRAM if flash... |
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| 2022-04-08 |
Luke Kenneth... | add ELF reading to coldboot.c, move spi address to... |
commit | commitdiff | tree |
| 2022-04-08 |
Luke Kenneth... | add read of SYSCON and entry for SPIFlash |
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| 2022-04-08 |
Luke Kenneth... | up the delay-time on ddr3 reset, put loop around dram... |
commit | commitdiff | tree |
| 2022-04-08 |
Luke Kenneth... | comment/80-char limit |
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| 2022-04-07 |
Raptor Engineering... | Update coldboot DDR3 init firmware to work with latest... |
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| 2022-04-07 |
Raptor Engineering... | Add an asm dump with source to the coldboot makefile |
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| 2022-04-07 |
Raptor Engineering... | Enable DDR3 using a 50MHz clock on Versa 85 |
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| 2022-04-07 |
Raptor Engineering... | Move simulation HyperRAM pins off of DDR3 pins |
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| 2022-04-07 |
Raptor Engineering... | Fix DRAM simulation commands |
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| 2022-04-06 |
Luke Kenneth... | add QSPI support to arty_a7 |
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| 2022-04-04 |
Luke Kenneth... | allow setting individual directions on QSPI dq0-dq3 |
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| 2022-04-04 |
Luke Kenneth... | write out firmware to correct location, |
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