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last changeSun, 14 Apr 2024 19:39:44 +0000 (16:39 -0300)
shortlog
2 days ago Cesar Straussls2: add support for the Nexys Video board master
3 days ago Cesar Straussls2: avoid using DRIVE attribute on Xilinx devices...
3 days ago Cesar Straussls2: fix keyword for declaring pin voltage type on...
2022-11-22 Tobias Platencoldboot: add lfsr.h by Anton Blanchard
2022-11-20 Tobias Platenadd mode registers macro for orangecrab, extracted...
2022-09-13 Tobias Platenundo deletion of line defining toolchain for orangecrab
2022-09-12 Tobias Platenadd core_clk_freq variable
2022-08-07 Tobias Platencomment out reset signal for iverilog simulation
2022-08-03 Tobias Platenmore work on orangecrab dram
2022-07-20 Tobias Platenmerge part 2 of Cesar's patch
2022-07-15 Tobias Platenoptionally add ECLKBRIDGECS to ECP5CRG
2022-07-06 Tobias Platenfixed KeyError for rcs_arctic_tern_bmc_card
2022-06-30 Tobias Platenset dram_clk_freq to None
2022-05-17 Tobias Platenorangecrab: don't use async. set to 50 mhz.
2022-05-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2022-05-15 Tobias Platenset dram_clk_freq = 100.0e6 for orangecrab
...
heads
2 days ago master
13 months ago orangecrab-ddr3
2 years ago async-wip
2 years ago async
2 years ago ddr3