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last changeTue, 22 Nov 2022 19:43:46 +0000 (20:43 +0100)
shortlog
2022-11-22 Tobias Platencoldboot: add lfsr.h by Anton Blanchard master
2022-11-20 Tobias Platenadd mode registers macro for orangecrab, extracted...
2022-09-13 Tobias Platenundo deletion of line defining toolchain for orangecrab
2022-09-12 Tobias Platenadd core_clk_freq variable
2022-08-07 Tobias Platencomment out reset signal for iverilog simulation
2022-08-03 Tobias Platenmore work on orangecrab dram
2022-07-20 Tobias Platenmerge part 2 of Cesar's patch
2022-07-15 Tobias Platenoptionally add ECLKBRIDGECS to ECP5CRG
2022-07-06 Tobias Platenfixed KeyError for rcs_arctic_tern_bmc_card
2022-06-30 Tobias Platenset dram_clk_freq to None
2022-05-17 Tobias Platenorangecrab: don't use async. set to 50 mhz.
2022-05-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2022-05-15 Tobias Platenset dram_clk_freq = 100.0e6 for orangecrab
2022-05-04 Luke Kenneth... pass in freq setting to nextpnr-xilinx
2022-05-04 Luke Kenneth... add micron n25q 128mb QSPI device to table of
2022-05-04 Luke Kenneth... add tercel speed-up but missing id for arty a7 at the...
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heads
3 months ago orangecrab-ddr3
6 months ago master
13 months ago async-wip
13 months ago async
13 months ago ddr3