amd/addrlib: update Mesa's copy of addrlib Update to the internal master as of 2018-11-15. This has a lot of gratuitous whitespace change, but on the plus side it's built using the same tooling that's used for AMDVLK, which should help going forward.
amd/addrlib: update to the latest version for Vega12 Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
amd/addrlib: update to latest version This uses C++11 initializer lists. I just overwrote all Mesa files with internal addrlib and discarded hunks that we should probably keep, but I might have missed something. The code depending on ADDR_AM_BUILD is removed. We can add it back next time if needed. Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
amd/addrlib: fix typo in api name. This fixes the misspelling of ALIGNMENTS in addrlib. Reviewed-by: Eduardo Lima Mitev <elima@igalia.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
amd/addrlib: import gfx9 support
amdgpu/addrlib: Fix number of // Find ^/{80,99}$ and replace them to 100 "/" Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
amdgpu/addrlib: Cleanup. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
amdgpu/addrlib: Use namespaces Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignment Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
amdgpu/addrlib: add equation generation 1. Add new surface flags needEquation for client driver use to force the surface tile setting equation compatible. Override 2D/3D macro tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1. 2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure to return number of equations and the equation table to client driver 3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to return the equation index to client driver Please note the use of address equation has following restrictions: 1) The surface can't be splitable 2) The surface can't have non zero tile swizzle value 3) Surface with > 1 slices must have PRT tile mode, which disable slice rotation
amdgpu/addrlib: style changes and minor cleanups Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
amdgpu/addrlib: rearrange code in preparation of refactoring No code changes. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
amdgpu/addrlib: add disableLinearOpt flag
amdgpu/addrlib: Add GetMaxAlignments
amdgpu/addrlib: Rewrite tile mode optmization code Note: remove reference to degrade4Space and use opt4Space instead.
amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure. Even if surface info input flag "tcComaptible" is enabled, tc compatible may be not supported if tile split happens for depth surfaces. Add a new flag in output structure to notify client to disable tc compatible in this case.
amdgpu/addrlib: Change to compute TC compatible stencil info Change the logic to compute tc compatible stencil info via depth's tileIndex instead of using depth's tileInfo. So the clients can get the stencil's tileInfo computed from macroModeTable. If the stencil tileInfo is same as depth tileInfo, then stencil is tc compatible; otherwise, stencil is not tc compatible. The current suggestion is to create another stencil buffer with the tc compatible tileInfo, use depth-to-color copy to decompress and tile convert the rendered stencil to tc compoatible stencil (And use the new stencil buffer to program TC).
amd/addrlib: move addrlib from amdgpu winsys to common code Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>