intel/disasm: Label support in shader disassembly for UIP/JIP Shader instructions which use UIP/JIP now get formatted with a label in addition with immediate value, labels have "LABEL%d" format. v2: - Consider brw_jump_scale when calculating label's offset From: "Lonnberg, Toni" <toni.lonnberg@intel.com> Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>
intel/disasm: Change visibility of has_uip and has_jip Pre-work for shader disassembly label support. From: "Lonnberg, Toni" <toni.lonnberg@intel.com> Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>
intel/compiler: add and fix up fallthrough comments for gcc warnings Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5714>
intel/fs: Emit HALT for discard on Gen4-5 Using HALT to immediately jump to the end of the shader is required to implement GL_EXT_gpu_shader4 and OpenGL 3.0. However, vanilla OpenGL 1.2 doesn't forbid it and it likely makes something somewhere faster. We should be consistent and implement the same discard behavior on all hardware if we can. The rules for HALT on Gen4-5 are a bit different from Gen6+. On the older hardware, there is no stack for HALT; instead it's up to software to save and restore mask registers. However, there's no real saving needed since we only use HALT to jump to the end of the program where we're about about to do our FB writes. All we need to do is reset AMask to DMask, the value it was initialized to at the start of the thread. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5244>
intel/gen12: Take into account opcode when decoding SWSB The interpretation of the fields is different depending whether the instruction is a SEND/MATH or not. This fixes the disassembly output for non-SEND/MATH instructions that have both in-order and out-of-order dependencies. Their dependencies were wrongly represented as `@A $B` when the correct would be `@A $B.dst`. Fixes: 6154cdf924f ("intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.") Fixes: 83612c01271 ("intel/disasm/gen12: Disassemble software scoreboard information.") Acked-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
intel/disasm: Properly disassemble indirect SENDs Instead of emitting g[a0]UD for the indirect descriptor, emit a0<0>UD. This is more correct because there is no GRF involved. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
intel/compiler: Don't disassemble align1 3-src operands on Gen < 10 Since the platforms don't support align1 3-src instructions, the contents of these operands are not going to be meaningful. Just don't print them to avoid hitting some assertions in brw_inst functions. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
intel/disasm: Fix decoding of src0 of SENDS There is no instruction field for the register file for src0 because it's always GRF. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
intel/compiler: Refactor disassembly of sources in 3src instruction Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
intel/disasm: Disassemble register file of split SEND sources. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/disasm: Don't disassemble saturate control on SEND instructions. The field is gone on Gen12+ and it was illegal on previous generations. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/disasm/gen12: Disassemble Gen12 SEND instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/disasm/gen12: Disassemble Gen12 SYNC instruction. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/disasm/gen12: Disassemble three-source instruction source and destination regions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/disasm/gen12: Fix disassembly of some common instruction controls. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/disasm/gen12: Disassemble software scoreboard information. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C). The brw_inst opcode accessors are going away in one of the following commits. We could potentially replace them with the new helpers that do opcode remapping, but that would lead to a circular dependency between brw_inst.h and brw_eu.h. This way we also avoid ordering issues that can cause the semantics of the ex_desc accessors to change depending on whether the ex_desc field is set after or before the opcode instruction field. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
intel/disasm: Disassemble immediate value properly for dim On haswell, for dim instruction we encode immediate float value operand into double float, v2: Fix comment (Matt Turner) Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
intel/disasm: Disassemble JIP offset for while Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
intel/compiler: Print quad value in hex format Print quad value same as unsigned quad so that we can distinguish in between quater control disassembled values for e.g 1/2/3[Q] and immediate quad value for e.g 1Q. This allows round-tripping through the assembler/disassembler. Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>