intel/assembler: Add labels support Use labels instead of numeric JIP/UIP offsets. Works for gen6+. v2: - Change asm tests to use labels on gen6+ - Remove usage of relative offsets on gen6+ - Consider brw_jump_scale when setting relative offset - Return error if there is a JIP/UIP label without matching target - Fix matching of label tokens Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>
intel/tools: Simplify notification register handling Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Don't hardcode notification register Previously we parsed a src non-terminal but did nothing with it. Since the WAIT instruction is kind of weird, in that you have to give it the same notification subregister for both destination and source, and it always has an exec size of 1, let's parse a destination instead of a source. This way, we can parse a writemask rather than a swizzle in align16 mode, and easily convert the writemask to a swizzle to create the source register. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Manually set ARF register file/nr/subnr brw_reg::subnr is in bytes, like the subnr field in the instruction word, but we disassemble the subregister number in units of the type. For example g0.3<1>F would have a subnr=12. These non-terminals produce a brw_reg and feed into other non-terminals that call brw_reg(), where they are passed the subnr that we set here. brw_reg()'s subnr parameter is expected to be in terms of the register type, and it is multiplied by the type size to calculate the subnr in bytes. In these non-terminals, we don't know the register type yet, so we must store the subregister number as it was given to us in the .subnr field and let the brw_reg() constructor handle the conversion to the canonical byte-based subnr form when it knows the type. Before this patch, subregister numbers applied to these registers would be multiplied with the type size twice. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Pass integers, not enums, to stride() Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Simplify dstregion Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Simplify immediate handling Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Make writemask an integer Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Make swizzle an integer Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Simplify register type handling Produce a brw_reg_type rather than a whole brw_reg and rename a few non-terminals. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Don't allow empty type specifier It's preferable to require an explicit type. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Remove stray newline Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Fix typos Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
intel/tools: Disallow control subregisters > 3 > 4 was probably a typo, since the documentation says that there are 4 subregisters (0-3). Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
intel/tools: Require explicit regions/types for special regs The docs say that these registers should only be read with a certain type, and I'm inclined to believe that the hardware behaves that way, but it makes the assembler a little more confusing and also confuses the user of the assembler that some operands don't take types or regions. Just always requiring regions and types seems like the sensible thing. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
intel/tools: Drop srctype from ipreg It's unused, and it would cause shift/reduce conflicts after the next patch. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
intel/tools: Remove unnecessary reg number checking a0 is the only address register, and cr0 is the only control register, so there's no need to return the register number, espcially since the lexer explicitly consumes "a0" and "cr0". Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
intel/tools: Set correct address register file and number in i965_asm We need to use already created brw_reg and set correct file type, register number and sub register number. Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
intel/tools: Handle STATE_REG in typed source operand Also stop using brw_sr0_reg function as it return new brw_reg, we already created register, all we have to is just set file, register number and subnr. Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
intel/tools: Handle illegal instruction Allow assembler to handle illegal instruction even though mesa doesn't use it but might be required at some point in future. Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>