anv: fix up dynamic clip emission There were 2 issues : * We were not emitting the clip state when the pipeline changed * On Gen7 we did not program the front facing & cull mode dynamic values in the clip state Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: c34d8ac26e0a21 ("anv: handle dynamic viewport count") Closes https://gitlab.freedesktop.org/mesa/mesa/-/issues/3379 Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6265>
anv: centralize vk to gen arrays Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6265>
anv: handle dynamic viewport count Emit 3DSTATE_CLIP during cmd_buffer_flush_state so that we can change the max viewport count dynamically. v2: use one common clip state as size is the same for all gens (Lionel) Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5604>
anv: Plumb deref block size through to 3DSTATE_SF Cc: "20.0" mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
anv: Make AUX table invalidate a PIPE_* bit This commit moves it in with all the other cache invalidation operations as if it were done by PIPE_CONTROL even though it's a pair of register writes. This means we only have to write the GFX_AUX_TABLE_BASE_ADDR register once at device initialization instead of every invalidate. Invalidates are now a single LRI instead of two. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
anv: Use PIPE_CONTROL flushes to implement the gen8 VF cache WA Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
anv/gen12: Write GFX_AUX_TABLE base address register Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
anv/gen9: Optimize slice and subslice load balancing behavior. See "i965/gen9: Optimize slice and subslice load balancing behavior." for the rationale. According to Jason, improves Aztec Ruins performance by 2.7%. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Undo CPU performance micro-optimization done in i965 and iris due to lack of data justifying it on anv. Use cmd_buffer_apply_pipe_flushes wrapper instead of emitting pipe control command directly. (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
anv: Move mi_memcpy and mi_memset to gen_mi_builder Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
anv: Implement VK_EXT_conditional_rendering for gen 7.5+ Conditional rendering affects next functions: - vkCmdDraw, vkCmdDrawIndexed, vkCmdDrawIndirect, vkCmdDrawIndexedIndirect - vkCmdDrawIndirectCountKHR, vkCmdDrawIndexedIndirectCountKHR - vkCmdDispatch, vkCmdDispatchIndirect, vkCmdDispatchBase - vkCmdClearAttachments Value from conditional buffer is cached into designated register, MI_PREDICATE is emitted every time conditional rendering is enabled and command requires it. v2: by Jason Ekstrand - Use vk_find_struct_const instead of manually looping - Move draw count loading to prepare function - Zero the top 32-bits of MI_ALU_REG15 v3: Apply pipeline flush before accessing conditional buffer (The issue was found by Samuel Iglesias) v4: - Remove support of Haswell due to possible hardware bug - Made TMP_REG_PREDICATE and TMP_REG_DRAW_COUNT defines to define registers in one place. v5: thanks to Jason Ekstrand and Lionel Landwerlin - Workaround the fact that MI_PREDICATE_RESULT is not accessible on Haswell by manually calculating MI_PREDICATE_RESULT and re-emitting MI_PREDICATE when necessary. v6: suggested by Lionel Landwerlin - Instead of calculating the result of predicate once - re-emit MI_PREDICATE to make it easier to investigate error states. v7: suggested by Jason - Make anv_pipe_invalidate_bits_for_access_flag add CS_STALL if VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT is set. v8: suggested by Lionel - Precompute conditional predicate's result to support secondary command buffers. - Make prepare_for_draw_count_predicate more readable. Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
anv: Add a mi_memset and use it for zeroing queries Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
anv/memcpy: Use addresses instead of bo+offset Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
anv/cmd_buffer: Add a mark_image_written helper Currently, this helper does nothing but we call it every place where an image is written through the render pipeline. This will allow us to properly mark the aux state so that we can handle resolves correctly. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
anv/gpu_memcpy: Add a lighter-weight GPU memcpy function We'll be performing a GPU memcpy in more places to copy small amounts of data. Add an alternate function that thrashes less state. v2: - Make a new function (Jason Ekstrand). - Move the #define into the function. v3: - Update the function name (Jason). - Update comments. v4: Use an indirect drawing register as TEMP_REG (Jason Ekstrand). Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
anv/gpu_memcpy: Rename the gpu_memcpy function A GPU memcpy function could alternatively be implemented using MI_* commands. Provide more detail into how this one operates in case another memcpy function is created. v2: - Update the commit message. v3: - Use 'memcpy' instead of 'cpy' (Jason Ekstrand) - Shorten 'streamout' to 'so' Suggested-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v2) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
anv: Add support for the PMA fix on Broadwell This helps Dota 2 on Broadwell by 8-9%. I also hacked up the driver and used the Sascha "shadowmapping" demo to get some results. Setting uses_kill to true dropped the framerate on the demo by 25-30%. Enabling the PMA fix brought it back up to around 90% of the original framerate. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
anv: Delete anv's HiZ op emit function This is no longer used. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
anv: Implement a depth stall restriction on gen7 Fixes around 60 Vulkan CTS tests on Haswell Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Cc: "13.0" <mesa-stable@lists.freedesktop.org>
intel: Share URB configuration code between GL and Vulkan. This code is far too complicated to cut and paste. v2: Update the newly added genX_gpu_memcpy.c; const a few things. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
anv: Add a helper for doing buffer copies with nothing but VF and SOL. This method of doing copies has the advantage of touching very little of the GPU state. While it does disable all the shader stages, it doesn't have to blow away binding tables, viewports, scissors, or any other bits of dynamic state other than VBO 32 which is already reserved. All of the state that it does touch is contained within a pipeline anyway so that's the only thing that has to be dirtied. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>