2 * Copyright 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
29 #if defined(__cplusplus)
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
61 * Vendors should document their modifier usage in as much detail as
62 * possible, to ensure maximum compatibility across devices, drivers and
65 * The authoritative list of format modifier codes is found in
66 * `include/uapi/drm/drm_fourcc.h`
69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
70 ((__u32)(c) << 16) | ((__u32)(d) << 24))
72 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
74 /* Reserve 0 for the invalid format specifier */
75 #define DRM_FORMAT_INVALID 0
78 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
81 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
84 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
87 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
88 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
91 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
92 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
95 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
96 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
99 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
100 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
101 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
102 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
104 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
105 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
106 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
107 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
109 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
110 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
111 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
112 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
114 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
115 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
116 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
117 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
119 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
120 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
123 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
124 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
127 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
128 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
129 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
130 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
132 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
133 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
134 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
135 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
137 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
138 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
139 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
140 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
142 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
143 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
144 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
145 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
148 * Floating point 64bpp RGB
149 * IEEE 754-2008 binary16 half-precision float
150 * [15:0] sign:exponent:mantissa 1:5:10
152 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
153 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
155 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
156 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
159 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
160 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
161 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
162 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
164 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
165 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
168 * packed YCbCr420 2x2 tiled formats
169 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
171 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
172 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
173 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
174 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
176 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
177 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
178 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
179 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
183 * index 0 = RGB plane, same format as the corresponding non _A8 format has
184 * index 1 = A plane, [7:0] A
186 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
187 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
188 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
189 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
190 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
191 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
192 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
193 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
197 * index 0 = Y plane, [7:0] Y
198 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
200 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
202 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
203 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
204 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
205 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
206 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
207 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
210 * 2 plane YCbCr MSB aligned
211 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
212 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
214 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
217 * 2 plane YCbCr MSB aligned
218 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
219 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
221 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
224 * 2 plane YCbCr MSB aligned
225 * index 0 = Y plane, [15:0] Y little endian
226 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
228 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
232 * index 0: Y plane, [7:0] Y
233 * index 1: Cb plane, [7:0] Cb
234 * index 2: Cr plane, [7:0] Cr
236 * index 1: Cr plane, [7:0] Cr
237 * index 2: Cb plane, [7:0] Cb
239 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
240 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
241 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
242 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
243 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
244 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
245 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
246 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
247 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
248 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
254 * Format modifiers describe, typically, a re-ordering or modification
255 * of the data in a plane of an FB. This can be used to express tiled/
256 * swizzled formats, or compression, or a combination of the two.
258 * The upper 8 bits of the format modifier are a vendor-id as assigned
259 * below. The lower 56 bits are assigned as vendor sees fit.
263 #define DRM_FORMAT_MOD_NONE 0
264 #define DRM_FORMAT_MOD_VENDOR_NONE 0
265 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
266 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
267 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
268 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
269 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
270 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
271 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
272 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
273 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
275 /* add more to the end as needed */
277 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
279 #define fourcc_mod_code(vendor, val) \
280 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
283 * Format Modifier tokens:
285 * When adding a new token please document the layout with a code comment,
286 * similar to the fourcc codes above. drm_fourcc.h is considered the
287 * authoritative source for all of these.
293 * This modifier can be used as a sentinel to terminate the format modifiers
294 * list, or to initialize a variable with an invalid modifier. It might also be
295 * used to report an error back to userspace for certain APIs.
297 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
302 * Just plain linear layout. Note that this is different from no specifying any
303 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
304 * which tells the driver to also take driver-internal information into account
305 * and so might actually result in a tiled framebuffer.
307 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
309 /* Intel framebuffer modifiers */
312 * Intel X-tiling layout
314 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
315 * in row-major layout. Within the tile bytes are laid out row-major, with
316 * a platform-dependent stride. On top of that the memory can apply
317 * platform-depending swizzling of some higher address bits into bit6.
319 * This format is highly platforms specific and not useful for cross-driver
320 * sharing. It exists since on a given platform it does uniquely identify the
321 * layout in a simple way for i915-specific userspace.
323 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
326 * Intel Y-tiling layout
328 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
329 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
330 * chunks column-major, with a platform-dependent height. On top of that the
331 * memory can apply platform-depending swizzling of some higher address bits
334 * This format is highly platforms specific and not useful for cross-driver
335 * sharing. It exists since on a given platform it does uniquely identify the
336 * layout in a simple way for i915-specific userspace.
338 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
341 * Intel Yf-tiling layout
343 * This is a tiled layout using 4Kb tiles in row-major layout.
344 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
345 * are arranged in four groups (two wide, two high) with column-major layout.
346 * Each group therefore consits out of four 256 byte units, which are also laid
347 * out as 2x2 column-major.
348 * 256 byte units are made out of four 64 byte blocks of pixels, producing
349 * either a square block or a 2:1 unit.
350 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
351 * in pixel depends on the pixel depth.
353 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
356 * Intel color control surface (CCS) for render compression
358 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
359 * The main surface will be plane index 0 and must be Y/Yf-tiled,
360 * the CCS will be plane index 1.
362 * Each CCS tile matches a 1024x512 pixel area of the main surface.
363 * To match certain aspects of the 3D hardware the CCS is
364 * considered to be made up of normal 128Bx32 Y tiles, Thus
365 * the CCS pitch must be specified in multiples of 128 bytes.
367 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
368 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
369 * But that fact is not relevant unless the memory is accessed
372 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
373 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
376 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
378 * Macroblocks are laid in a Z-shape, and each pixel data is following the
379 * standard NV12 style.
380 * As for NV12, an image is the result of two frame buffers: one for Y,
381 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
382 * Alignment requirements are (for each buffer):
383 * - multiple of 128 pixels for the width
384 * - multiple of 32 pixels for the height
386 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
388 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
391 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
393 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
394 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
395 * they correspond to their 16x16 luma block.
397 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
400 * Qualcomm Compressed Format
402 * Refers to a compressed variant of the base format that is compressed.
403 * Implementation may be platform and base-format specific.
405 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
406 * Pixel data pitch/stride is aligned with macrotile width.
407 * Pixel data height is aligned with macrotile height.
408 * Entire pixel data buffer is aligned with 4k(bytes).
410 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
412 /* Vivante framebuffer modifiers */
415 * Vivante 4x4 tiling layout
417 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
420 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
423 * Vivante 64x64 super-tiling layout
425 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
426 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
429 * For more information: see
430 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
432 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
435 * Vivante 4x4 tiling layout for dual-pipe
437 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
438 * different base address. Offsets from the base addresses are therefore halved
439 * compared to the non-split tiled layout.
441 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
444 * Vivante 64x64 super-tiling layout for dual-pipe
446 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
447 * starts at a different base address. Offsets from the base addresses are
448 * therefore halved compared to the non-split super-tiled layout.
450 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
452 /* NVIDIA frame buffer modifiers */
455 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
457 * Pixels are arranged in simple tiles of 16 x 16 bytes.
459 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
462 * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
464 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
465 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
467 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
469 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
477 * 5 == THIRTYTWO_GOBS
479 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
482 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
483 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
485 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
486 fourcc_mod_code(NVIDIA, 0x10)
487 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
488 fourcc_mod_code(NVIDIA, 0x11)
489 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
490 fourcc_mod_code(NVIDIA, 0x12)
491 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
492 fourcc_mod_code(NVIDIA, 0x13)
493 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
494 fourcc_mod_code(NVIDIA, 0x14)
495 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
496 fourcc_mod_code(NVIDIA, 0x15)
499 * Some Broadcom modifiers take parameters, for example the number of
500 * vertical lines in the image. Reserve the lower 32 bits for modifier
501 * type, and the next 24 bits for parameters. Top 8 bits are the
504 #define __fourcc_mod_broadcom_param_shift 8
505 #define __fourcc_mod_broadcom_param_bits 48
506 #define fourcc_mod_broadcom_code(val, params) \
507 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
508 #define fourcc_mod_broadcom_param(m) \
509 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
510 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
511 #define fourcc_mod_broadcom_mod(m) \
512 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
513 __fourcc_mod_broadcom_param_shift))
516 * Broadcom VC4 "T" format
518 * This is the primary layout that the V3D GPU can texture from (it
519 * can't do linear). The T format has:
521 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
522 * pixels at 32 bit depth.
524 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
527 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
528 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
529 * they're (TR, BR, BL, TL), where bottom left is start of memory.
531 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
532 * tiles) or right-to-left (odd rows of 4k tiles).
534 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
537 * Broadcom SAND format
539 * This is the native format that the H.264 codec block uses. For VC4
540 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
542 * The image can be considered to be split into columns, and the
543 * columns are placed consecutively into memory. The width of those
544 * columns can be either 32, 64, 128, or 256 pixels, but in practice
545 * only 128 pixel columns are used.
547 * The pitch between the start of each column is set to optimally
548 * switch between SDRAM banks. This is passed as the number of lines
549 * of column width in the modifier (we can't use the stride value due
550 * to various core checks that look at it , so you should set the
551 * stride to width*cpp).
553 * Note that the column height for this format modifier is the same
554 * for all of the planes, assuming that each column contains both Y
555 * and UV. Some SAND-using hardware stores UV in a separate tiled
556 * image from Y to reduce the column height, which is not supported
557 * with these modifiers.
560 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
561 fourcc_mod_broadcom_code(2, v)
562 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
563 fourcc_mod_broadcom_code(3, v)
564 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
565 fourcc_mod_broadcom_code(4, v)
566 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
567 fourcc_mod_broadcom_code(5, v)
569 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
570 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
571 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
572 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
573 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
574 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
575 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
576 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
578 /* Broadcom UIF format
580 * This is the common format for the current Broadcom multimedia
581 * blocks, including V3D 3.x and newer, newer video codecs, and
584 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
585 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
586 * stored in columns, with padding between the columns to ensure that
587 * moving from one column to the next doesn't hit the same SDRAM page
590 * To calculate the padding, it is assumed that each hardware block
591 * and the software driving it knows the platform's SDRAM page size,
592 * number of banks, and XOR address, and that it's identical between
593 * all blocks using the format. This tiling modifier will use XOR as
594 * necessary to reduce the padding. If a hardware block can't do XOR,
595 * the assumption is that a no-XOR tiling modifier will be created.
597 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
600 * Arm Framebuffer Compression (AFBC) modifiers
602 * AFBC is a proprietary lossless image compression protocol and format.
603 * It provides fine-grained random access and minimizes the amount of data
604 * transferred between IP blocks.
606 * AFBC has several features which may be supported and/or used, which are
607 * represented using bits in the modifier. Not all combinations are valid,
608 * and different devices or use-cases may support different combinations.
610 * Further information on the use of AFBC modifiers can be found in
611 * Documentation/gpu/afbc.rst
613 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
616 * AFBC superblock size
618 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
619 * size (in pixels) must be aligned to a multiple of the superblock size.
620 * Four lowest significant bits(LSBs) are reserved for block size.
622 * Where one superblock size is specified, it applies to all planes of the
623 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
624 * the first applies to the Luma plane and the second applies to the Chroma
625 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
626 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
628 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
629 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
630 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
631 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
632 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
635 * AFBC lossless colorspace transform
637 * Indicates that the buffer makes use of the AFBC lossless colorspace
640 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
645 * Indicates that the payload of each superblock is split. The second
646 * half of the payload is positioned at a predefined offset from the start
647 * of the superblock payload.
649 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
654 * This flag indicates that the payload of each superblock must be stored at a
655 * predefined position relative to the other superblocks in the same AFBC
656 * buffer. This order is the same order used by the header buffer. In this mode
657 * each superblock is given the same amount of space as an uncompressed
658 * superblock of the particular format would require, rounding up to the next
659 * multiple of 128 bytes in size.
661 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
664 * AFBC copy-block restrict
666 * Buffers with this flag must obey the copy-block restriction. The restriction
667 * is such that there are no copy-blocks referring across the border of 8x8
668 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
670 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
675 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
676 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
677 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
678 * larger bpp formats. The order between the tiles is scan line.
679 * When the tiled layout is used, the buffer size (in pixels) must be aligned
682 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
685 * AFBC solid color blocks
687 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
688 * can be reduced if a whole superblock is a single color.
690 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
695 * Indicates that the buffer is allocated in a layout safe for front-buffer
698 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
701 * AFBC buffer content hints
703 * Indicates that the buffer includes per-superblock content hints.
705 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
708 * Allwinner tiled modifier
710 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
711 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
714 * With this tiling, the luminance samples are disposed in tiles representing
715 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
716 * The pixel order in each tile is linear and the tiles are disposed linearly,
717 * both in row-major order.
719 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
721 #if defined(__cplusplus)
725 #endif /* DRM_FOURCC_H */