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[mesa.git] / src / amd / addrlib / addrinterface.h
1 /*
2 * Copyright © 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 /**
28 ****************************************************************************************************
29 * @file addrinterface.h
30 * @brief Contains the addrlib interfaces declaration and parameter defines
31 ****************************************************************************************************
32 */
33 #ifndef __ADDR_INTERFACE_H__
34 #define __ADDR_INTERFACE_H__
35
36 #include "addrtypes.h"
37
38 #if defined(__cplusplus)
39 extern "C"
40 {
41 #endif
42
43 #define ADDRLIB_VERSION_MAJOR 6
44 #define ADDRLIB_VERSION_MINOR 2
45 #define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR)
46
47 /// Virtually all interface functions need ADDR_HANDLE as first parameter
48 typedef VOID* ADDR_HANDLE;
49
50 /// Client handle used in callbacks
51 typedef VOID* ADDR_CLIENT_HANDLE;
52
53 /**
54 * /////////////////////////////////////////////////////////////////////////////////////////////////
55 * // Callback functions
56 * /////////////////////////////////////////////////////////////////////////////////////////////////
57 * typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
58 * const ADDR_ALLOCSYSMEM_INPUT* pInput);
59 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
60 * VOID* pVirtAddr);
61 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
62 * const ADDR_DEBUGPRINT_INPUT* pInput);
63 *
64 * /////////////////////////////////////////////////////////////////////////////////////////////////
65 * // Create/Destroy/Config functions
66 * /////////////////////////////////////////////////////////////////////////////////////////////////
67 * AddrCreate()
68 * AddrDestroy()
69 *
70 * /////////////////////////////////////////////////////////////////////////////////////////////////
71 * // Surface functions
72 * /////////////////////////////////////////////////////////////////////////////////////////////////
73 * AddrComputeSurfaceInfo()
74 * AddrComputeSurfaceAddrFromCoord()
75 * AddrComputeSurfaceCoordFromAddr()
76 *
77 * /////////////////////////////////////////////////////////////////////////////////////////////////
78 * // HTile functions
79 * /////////////////////////////////////////////////////////////////////////////////////////////////
80 * AddrComputeHtileInfo()
81 * AddrComputeHtileAddrFromCoord()
82 * AddrComputeHtileCoordFromAddr()
83 *
84 * /////////////////////////////////////////////////////////////////////////////////////////////////
85 * // C-mask functions
86 * /////////////////////////////////////////////////////////////////////////////////////////////////
87 * AddrComputeCmaskInfo()
88 * AddrComputeCmaskAddrFromCoord()
89 * AddrComputeCmaskCoordFromAddr()
90 *
91 * /////////////////////////////////////////////////////////////////////////////////////////////////
92 * // F-mask functions
93 * /////////////////////////////////////////////////////////////////////////////////////////////////
94 * AddrComputeFmaskInfo()
95 * AddrComputeFmaskAddrFromCoord()
96 * AddrComputeFmaskCoordFromAddr()
97 *
98 * /////////////////////////////////////////////////////////////////////////////////////////////////
99 * // Element/Utility functions
100 * /////////////////////////////////////////////////////////////////////////////////////////////////
101 * ElemFlt32ToDepthPixel()
102 * ElemFlt32ToColorPixel()
103 * AddrExtractBankPipeSwizzle()
104 * AddrCombineBankPipeSwizzle()
105 * AddrComputeSliceSwizzle()
106 * AddrConvertTileInfoToHW()
107 * AddrConvertTileIndex()
108 * AddrConvertTileIndex1()
109 * AddrGetTileIndex()
110 * AddrComputeBaseSwizzle()
111 * AddrUseTileIndex()
112 * AddrUseCombinedSwizzle()
113 *
114 **/
115
116 ////////////////////////////////////////////////////////////////////////////////////////////////////
117 // Callback functions
118 ////////////////////////////////////////////////////////////////////////////////////////////////////
119
120 /**
121 ****************************************************************************************************
122 * @brief channel setting structure
123 ****************************************************************************************************
124 */
125 typedef union _ADDR_CHANNEL_SETTING
126 {
127 struct
128 {
129 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid
130 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel
131 UINT_8 index : 5; ///< Channel index
132 };
133 UINT_8 value; ///< Value
134 } ADDR_CHANNEL_SETTING;
135
136 /**
137 ****************************************************************************************************
138 * @brief address equation key structure
139 ****************************************************************************************************
140 */
141 typedef union _ADDR_EQUATION_KEY
142 {
143 struct
144 {
145 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel
146 UINT_32 tileMode : 5; ///< Tile mode
147 UINT_32 microTileType : 3; ///< Micro tile type
148 UINT_32 pipeConfig : 5; ///< pipe config
149 UINT_32 numBanksLog2 : 3; ///< Number of banks log2
150 UINT_32 bankWidth : 4; ///< Bank width
151 UINT_32 bankHeight : 4; ///< Bank height
152 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio
153 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt
154 UINT_32 reserved : 1; ///< Reserved bit
155 } fields;
156 UINT_32 value;
157 } ADDR_EQUATION_KEY;
158
159 /**
160 ****************************************************************************************************
161 * @brief address equation structure
162 ****************************************************************************************************
163 */
164 #define ADDR_MAX_EQUATION_BIT 20u
165
166 // Invalid equation index
167 #define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF
168
169 typedef struct _ADDR_EQUATION
170 {
171 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting
172 ///< each bit is result of addr ^ xor ^ xor2
173 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting
174 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting
175 UINT_32 numBits; ///< The number of bits in equation
176 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being
177 ///< stacked vertically prior to swizzling
178 } ADDR_EQUATION;
179
180
181 /**
182 ****************************************************************************************************
183 * @brief Alloc system memory flags.
184 * @note These flags are reserved for future use and if flags are added will minimize the impact
185 * of the client.
186 ****************************************************************************************************
187 */
188 typedef union _ADDR_ALLOCSYSMEM_FLAGS
189 {
190 struct
191 {
192 UINT_32 reserved : 32; ///< Reserved for future use.
193 } fields;
194 UINT_32 value;
195
196 } ADDR_ALLOCSYSMEM_FLAGS;
197
198 /**
199 ****************************************************************************************************
200 * @brief Alloc system memory input structure
201 ****************************************************************************************************
202 */
203 typedef struct _ADDR_ALLOCSYSMEM_INPUT
204 {
205 UINT_32 size; ///< Size of this structure in bytes
206
207 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags.
208 UINT_32 sizeInBytes; ///< System memory allocation size in bytes.
209 ADDR_CLIENT_HANDLE hClient; ///< Client handle
210 } ADDR_ALLOCSYSMEM_INPUT;
211
212 /**
213 ****************************************************************************************************
214 * ADDR_ALLOCSYSMEM
215 * @brief
216 * Allocate system memory callback function. Returns valid pointer on success.
217 ****************************************************************************************************
218 */
219 typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
220 const ADDR_ALLOCSYSMEM_INPUT* pInput);
221
222 /**
223 ****************************************************************************************************
224 * @brief Free system memory input structure
225 ****************************************************************************************************
226 */
227 typedef struct _ADDR_FREESYSMEM_INPUT
228 {
229 UINT_32 size; ///< Size of this structure in bytes
230
231 VOID* pVirtAddr; ///< Virtual address
232 ADDR_CLIENT_HANDLE hClient; ///< Client handle
233 } ADDR_FREESYSMEM_INPUT;
234
235 /**
236 ****************************************************************************************************
237 * ADDR_FREESYSMEM
238 * @brief
239 * Free system memory callback function.
240 * Returns ADDR_OK on success.
241 ****************************************************************************************************
242 */
243 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
244 const ADDR_FREESYSMEM_INPUT* pInput);
245
246 /**
247 ****************************************************************************************************
248 * @brief Print debug message input structure
249 ****************************************************************************************************
250 */
251 typedef struct _ADDR_DEBUGPRINT_INPUT
252 {
253 UINT_32 size; ///< Size of this structure in bytes
254
255 CHAR* pDebugString; ///< Debug print string
256 va_list ap; ///< Variable argument list
257 ADDR_CLIENT_HANDLE hClient; ///< Client handle
258 } ADDR_DEBUGPRINT_INPUT;
259
260 /**
261 ****************************************************************************************************
262 * ADDR_DEBUGPRINT
263 * @brief
264 * Print debug message callback function.
265 * Returns ADDR_OK on success.
266 ****************************************************************************************************
267 */
268 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
269 const ADDR_DEBUGPRINT_INPUT* pInput);
270
271 /**
272 ****************************************************************************************************
273 * ADDR_CALLBACKS
274 *
275 * @brief
276 * Address Library needs client to provide system memory alloc/free routines.
277 ****************************************************************************************************
278 */
279 typedef struct _ADDR_CALLBACKS
280 {
281 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory
282 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory
283 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message
284 } ADDR_CALLBACKS;
285
286 ////////////////////////////////////////////////////////////////////////////////////////////////////
287 // Create/Destroy functions
288 ////////////////////////////////////////////////////////////////////////////////////////////////////
289
290 /**
291 ****************************************************************************************************
292 * ADDR_CREATE_FLAGS
293 *
294 * @brief
295 * This structure is used to pass some setup in creation of AddrLib
296 * @note
297 ****************************************************************************************************
298 */
299 typedef union _ADDR_CREATE_FLAGS
300 {
301 struct
302 {
303 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off
304 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and
305 /// output structure
306 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid
307 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle
308 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level
309 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
310 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
311 UINT_32 reserved : 25; ///< Reserved bits for future use
312 };
313
314 UINT_32 value;
315 } ADDR_CREATE_FLAGS;
316
317 /**
318 ****************************************************************************************************
319 * ADDR_REGISTER_VALUE
320 *
321 * @brief
322 * Data from registers to setup AddrLib global data, used in AddrCreate
323 ****************************************************************************************************
324 */
325 typedef struct _ADDR_REGISTER_VALUE
326 {
327 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value.
328 /// For R6xx/R7xx, use GB_TILING_CONFIG.
329 /// But they can be treated as the same.
330 /// if this value is 0, use chip to set default value
331 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled.
332 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE
333
334 /// R800 registers-----------------------------------------------
335 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK
336 /// No enums for this value in h/w header files
337 /// 0: 4
338 /// 1: 8
339 /// 2: 16
340 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK
341 /// 0: 1
342 /// 1: 2
343 /// SI (R1000) registers-----------------------------------------
344 const UINT_32* pTileConfig; ///< Global tile setting tables
345 UINT_32 noOfEntries; ///< Number of entries in pTileConfig
346
347 ///< CI registers-------------------------------------------------
348 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table
349 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig
350
351 ///< GFX9 HW parameters
352 UINT_32 blockVarSizeLog2; ///< SW_VAR_* block size
353 } ADDR_REGISTER_VALUE;
354
355 /**
356 ****************************************************************************************************
357 * ADDR_CREATE_INPUT
358 *
359 * @brief
360 * Parameters use to create an AddrLib Object. Caller must provide all fields.
361 *
362 ****************************************************************************************************
363 */
364 typedef struct _ADDR_CREATE_INPUT
365 {
366 UINT_32 size; ///< Size of this structure in bytes
367
368 UINT_32 chipEngine; ///< Chip Engine
369 UINT_32 chipFamily; ///< Chip Family
370 UINT_32 chipRevision; ///< Chip Revision
371 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print
372 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib
373 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data
374 ADDR_CLIENT_HANDLE hClient; ///< Client handle
375 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels
376 } ADDR_CREATE_INPUT;
377
378 /**
379 ****************************************************************************************************
380 * ADDR_CREATEINFO_OUTPUT
381 *
382 * @brief
383 * Return AddrLib handle to client driver
384 *
385 ****************************************************************************************************
386 */
387 typedef struct _ADDR_CREATE_OUTPUT
388 {
389 UINT_32 size; ///< Size of this structure in bytes
390
391 ADDR_HANDLE hLib; ///< Address lib handle
392
393 UINT_32 numEquations; ///< Number of equations in the table
394 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table
395 } ADDR_CREATE_OUTPUT;
396
397 /**
398 ****************************************************************************************************
399 * AddrCreate
400 *
401 * @brief
402 * Create AddrLib object, must be called before any interface calls
403 *
404 * @return
405 * ADDR_OK if successful
406 ****************************************************************************************************
407 */
408 ADDR_E_RETURNCODE ADDR_API AddrCreate(
409 const ADDR_CREATE_INPUT* pAddrCreateIn,
410 ADDR_CREATE_OUTPUT* pAddrCreateOut);
411
412
413
414 /**
415 ****************************************************************************************************
416 * AddrDestroy
417 *
418 * @brief
419 * Destroy AddrLib object, must be called to free internally allocated resources.
420 *
421 * @return
422 * ADDR_OK if successful
423 ****************************************************************************************************
424 */
425 ADDR_E_RETURNCODE ADDR_API AddrDestroy(
426 ADDR_HANDLE hLib);
427
428
429
430 ////////////////////////////////////////////////////////////////////////////////////////////////////
431 // Surface functions
432 ////////////////////////////////////////////////////////////////////////////////////////////////////
433
434 /**
435 ****************************************************************************************************
436 * @brief
437 * Bank/tiling parameters. On function input, these can be set as desired or
438 * left 0 for AddrLib to calculate/default. On function output, these are the actual
439 * parameters used.
440 * @note
441 * Valid bankWidth/bankHeight value:
442 * 1,2,4,8. They are factors instead of pixels or bytes.
443 *
444 * The bank number remains constant across each row of the
445 * macro tile as each pipe is selected, so the number of
446 * tiles in the x direction with the same bank number will
447 * be bank_width * num_pipes.
448 ****************************************************************************************************
449 */
450 typedef struct _ADDR_TILEINFO
451 {
452 /// Any of these parameters can be set to 0 to use the HW default.
453 UINT_32 banks; ///< Number of banks, numerical value
454 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank
455 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank
456 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1
457 UINT_32 tileSplitBytes; ///< Tile split size, in bytes
458 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1
459 } ADDR_TILEINFO;
460
461 // Create a define to avoid client change. The removal of R800 is because we plan to implement SI
462 // within 800 HWL - An AddrPipeCfg is added in above data structure
463 typedef ADDR_TILEINFO ADDR_R800_TILEINFO;
464
465 /**
466 ****************************************************************************************************
467 * @brief
468 * Information needed by quad buffer stereo support
469 ****************************************************************************************************
470 */
471 typedef struct _ADDR_QBSTEREOINFO
472 {
473 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye
474 UINT_32 rightOffset; ///< Offset (in bytes) to right eye
475 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes
476 } ADDR_QBSTEREOINFO;
477
478 /**
479 ****************************************************************************************************
480 * ADDR_SURFACE_FLAGS
481 *
482 * @brief
483 * Surface flags
484 ****************************************************************************************************
485 */
486 typedef union _ADDR_SURFACE_FLAGS
487 {
488 struct
489 {
490 UINT_32 color : 1; ///< Flag indicates this is a color buffer
491 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer
492 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer
493 UINT_32 texture : 1; ///< Flag indicates this is a texture
494 UINT_32 cube : 1; ///< Flag indicates this is a cubemap
495 UINT_32 volume : 1; ///< Flag indicates this is a volume texture
496 UINT_32 fmask : 1; ///< Flag indicates this is an fmask
497 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays
498 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed
499 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface
500 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil
501 UINT_32 display : 1; ///< Flag indicates this should match display controller req.
502 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space
503 /// i.e. save some memory but may lose performance
504 UINT_32 prt : 1; ///< Flag for partially resident texture
505 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface
506 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)
507 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
508 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
509 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce
510 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear
511 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that
512 /// dcc can't be enabled if pipe config of tile mode
513 /// is different from that of ASIC, this flag
514 /// is address lib internal flag, client should ignore it
515 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment.
516 /// This flag indicates we need to follow the
517 /// alignment with CZ families or other ASICs under
518 /// PX configuration + CZ.
519 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split
520 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear
521 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible.
522 /// This flag indicates we need to override tile
523 /// mode to PRT_* tile mode to disable slice rotation,
524 /// which is needed by swizzle pattern equation.
525 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output.
526 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type
527 UINT_32 minimizeAlignment : 1; ///< Minimize alignment
528 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode
529 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface
530 /// to make sure they share same tile config parameters
531 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade
532 UINT_32 reserved : 1; ///< Reserved bits
533 };
534
535 UINT_32 value;
536 } ADDR_SURFACE_FLAGS;
537
538 /**
539 ****************************************************************************************************
540 * ADDR_COMPUTE_SURFACE_INFO_INPUT
541 *
542 * @brief
543 * Input structure for AddrComputeSurfaceInfo
544 ****************************************************************************************************
545 */
546 typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT
547 {
548 UINT_32 size; ///< Size of this structure in bytes
549
550 AddrTileMode tileMode; ///< Tile mode
551 AddrFormat format; ///< If format is set to valid one, bpp/width/height
552 /// might be overwritten
553 UINT_32 bpp; ///< Bits per pixel
554 UINT_32 numSamples; ///< Number of samples
555 UINT_32 width; ///< Width, in pixels
556 UINT_32 height; ///< Height, in pixels
557 UINT_32 numSlices; ///< Number of surface slices or depth
558 UINT_32 slice; ///< Slice index
559 UINT_32 mipLevel; ///< Current mipmap level
560 UINT_32 numMipLevels; ///< Number of mips in mip chain
561 ADDR_SURFACE_FLAGS flags; ///< Surface type flags
562 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
563 /// number of samples for normal AA; Set it to the
564 /// number of fragments for EQAA
565 /// r800 and later HWL parameters
566 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's
567 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate
568 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1
569 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
570 /// while the global useTileIndex is set to 1
571 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a
572 /// must for mip levels from SI+.
573 /// Don't use pitch in blocks for compressed formats!
574 UINT_32 maxBaseAlign; ///< Max base alignment request from client
575 UINT_32 pitchAlign; ///< Pitch alignment request from client
576 UINT_32 heightAlign; ///< Height alignment request from client
577 } ADDR_COMPUTE_SURFACE_INFO_INPUT;
578
579 /**
580 ****************************************************************************************************
581 * ADDR_COMPUTE_SURFACE_INFO_OUTPUT
582 *
583 * @brief
584 * Output structure for AddrComputeSurfInfo
585 * @note
586 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
587 Pixel: Original pixel
588 ****************************************************************************************************
589 */
590 typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
591 {
592 UINT_32 size; ///< Size of this structure in bytes
593
594 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats)
595 UINT_32 height; ///< Height in elements (in blocks for compressed formats)
596 UINT_32 depth; ///< Number of slice/depth
597 UINT_64 surfSize; ///< Surface size in bytes
598 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input
599 UINT_32 baseAlign; ///< Base address alignment
600 UINT_32 pitchAlign; ///< Pitch alignment, in elements
601 UINT_32 heightAlign; ///< Height alignment, in elements
602 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture
603 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit)
604 UINT_32 pixelPitch; ///< Pitch in original pixels
605 UINT_32 pixelHeight; ///< Height in original pixels
606 UINT_32 pixelBits; ///< Original bits per pixel, passed from input
607 UINT_64 sliceSize; ///< Size of slice specified by input's slice
608 /// The result is controlled by surface flags & createFlags
609 /// By default this value equals to surfSize for volume
610 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register
611 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register
612 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register
613
614 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call
615
616 /// r800 and later HWL parameters
617 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input
618 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1
619 INT_32 tileIndex; ///< Tile index, MAY be "downgraded"
620
621 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
622 /// Output flags
623 struct
624 {
625 /// Special information to work around SI mipmap swizzle bug UBTS #317508
626 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled
627 ///< Only meaningful when create flag checkLast2DLevel is set
628 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible
629 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering
630 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT
631 ///< If address lib return true for mip 0, client should set prt flag
632 ///< for child mips in subsequent compute surface info calls
633 UINT_32 reserved :28; ///< Reserved bits
634 };
635
636 UINT_32 equationIndex; ///< Equation index in the equation table;
637
638 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro)
639 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro)
640 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro)
641
642 /// Stereo info
643 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
644
645 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set
646 } ADDR_COMPUTE_SURFACE_INFO_OUTPUT;
647
648 /**
649 ****************************************************************************************************
650 * AddrComputeSurfaceInfo
651 *
652 * @brief
653 * Compute surface width/height/depth/alignments and suitable tiling mode
654 ****************************************************************************************************
655 */
656 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
657 ADDR_HANDLE hLib,
658 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
659 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
660
661
662
663 /**
664 ****************************************************************************************************
665 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
666 *
667 * @brief
668 * Input structure for AddrComputeSurfaceAddrFromCoord
669 ****************************************************************************************************
670 */
671 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
672 {
673 UINT_32 size; ///< Size of this structure in bytes
674
675 UINT_32 x; ///< X coordinate
676 UINT_32 y; ///< Y coordinate
677 UINT_32 slice; ///< Slice index
678 UINT_32 sample; ///< Sample index, use fragment index for EQAA
679
680 UINT_32 bpp; ///< Bits per pixel
681 UINT_32 pitch; ///< Surface pitch, in pixels
682 UINT_32 height; ///< Surface height, in pixels
683 UINT_32 numSlices; ///< Surface depth
684 UINT_32 numSamples; ///< Number of samples
685
686 AddrTileMode tileMode; ///< Tile mode
687 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within
688 /// micro tile. Textures can also choose depth sample order
689 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles
690 /// the case that components are stored separately
691 UINT_32 compBits; ///< The component bits actually needed(for planar surface)
692
693 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
694 /// number of samples for normal AA; Set it to the
695 /// number of fragments for EQAA
696 /// r800 and later HWL parameters
697 // Used for 1D tiling above
698 AddrTileType tileType; ///< See defintion of AddrTileType
699 struct
700 {
701 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture
702 /// only flag. Only non-RT texture can set this to TRUE
703 UINT_32 reserved :31; ///< Reserved for future use.
704 };
705 // 2D tiling needs following structure
706 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
707 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
708 /// while the global useTileIndex is set to 1
709 union
710 {
711 struct
712 {
713 UINT_32 bankSwizzle; ///< Bank swizzle
714 UINT_32 pipeSwizzle; ///< Pipe swizzle
715 };
716 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
717 };
718 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
719
720 /**
721 ****************************************************************************************************
722 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
723 *
724 * @brief
725 * Output structure for AddrComputeSurfaceAddrFromCoord
726 ****************************************************************************************************
727 */
728 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
729 {
730 UINT_32 size; ///< Size of this structure in bytes
731
732 UINT_64 addr; ///< Byte address
733 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.
734 /// For surface bpp < 8, e.g. FMT_1.
735 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)
736 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
737
738 /**
739 ****************************************************************************************************
740 * AddrComputeSurfaceAddrFromCoord
741 *
742 * @brief
743 * Compute surface address from a given coordinate.
744 ****************************************************************************************************
745 */
746 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
747 ADDR_HANDLE hLib,
748 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
749 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
750
751
752
753 /**
754 ****************************************************************************************************
755 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
756 *
757 * @brief
758 * Input structure for AddrComputeSurfaceCoordFromAddr
759 ****************************************************************************************************
760 */
761 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
762 {
763 UINT_32 size; ///< Size of this structure in bytes
764
765 UINT_64 addr; ///< Address in bytes
766 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,
767 /// e.g. FMT_1;
768 UINT_32 bpp; ///< Bits per pixel
769 UINT_32 pitch; ///< Pitch, in pixels
770 UINT_32 height; ///< Height in pixels
771 UINT_32 numSlices; ///< Surface depth
772 UINT_32 numSamples; ///< Number of samples
773
774 AddrTileMode tileMode; ///< Tile mode
775 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile.
776 /// Note: Textures can choose depth sample order as well.
777 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles
778 /// the case that components are stored separately
779 UINT_32 compBits; ///< The component bits actually needed(for planar surface)
780
781 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
782 /// number of samples for normal AA; Set it to the
783 /// number of fragments for EQAA
784 /// r800 and later HWL parameters
785 // Used for 1D tiling above
786 AddrTileType tileType; ///< See defintion of AddrTileType
787 struct
788 {
789 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture
790 /// only flag. Only non-RT texture can set this to TRUE
791 UINT_32 reserved :31; ///< Reserved for future use.
792 };
793 // 2D tiling needs following structure
794 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
795 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
796 /// while the global useTileIndex is set to 1
797 union
798 {
799 struct
800 {
801 UINT_32 bankSwizzle; ///< Bank swizzle
802 UINT_32 pipeSwizzle; ///< Pipe swizzle
803 };
804 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
805 };
806 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
807
808 /**
809 ****************************************************************************************************
810 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
811 *
812 * @brief
813 * Output structure for AddrComputeSurfaceCoordFromAddr
814 ****************************************************************************************************
815 */
816 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
817 {
818 UINT_32 size; ///< Size of this structure in bytes
819
820 UINT_32 x; ///< X coordinate
821 UINT_32 y; ///< Y coordinate
822 UINT_32 slice; ///< Index of slices
823 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
824 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
825
826 /**
827 ****************************************************************************************************
828 * AddrComputeSurfaceCoordFromAddr
829 *
830 * @brief
831 * Compute coordinate from a given surface address
832 ****************************************************************************************************
833 */
834 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
835 ADDR_HANDLE hLib,
836 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
837 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
838
839 ////////////////////////////////////////////////////////////////////////////////////////////////////
840 // HTile functions
841 ////////////////////////////////////////////////////////////////////////////////////////////////////
842
843 /**
844 ****************************************************************************************************
845 * ADDR_HTILE_FLAGS
846 *
847 * @brief
848 * HTILE flags
849 ****************************************************************************************************
850 */
851 typedef union _ADDR_HTILE_FLAGS
852 {
853 struct
854 {
855 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
856 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile
857 /// size to 256xBankxPipe when computing tc-compatible
858 /// htile info.
859 UINT_32 reserved : 30; ///< Reserved bits
860 };
861
862 UINT_32 value;
863 } ADDR_HTILE_FLAGS;
864
865 /**
866 ****************************************************************************************************
867 * ADDR_COMPUTE_HTILE_INFO_INPUT
868 *
869 * @brief
870 * Input structure of AddrComputeHtileInfo
871 ****************************************************************************************************
872 */
873 typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT
874 {
875 UINT_32 size; ///< Size of this structure in bytes
876
877 ADDR_HTILE_FLAGS flags; ///< HTILE flags
878 UINT_32 pitch; ///< Surface pitch, in pixels
879 UINT_32 height; ///< Surface height, in pixels
880 UINT_32 numSlices; ///< Number of slices
881 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
882 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8
883 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8
884 ADDR_TILEINFO* pTileInfo; ///< Tile info
885
886 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
887 /// while the global useTileIndex is set to 1
888 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
889 ///< README: When tileIndex is not -1, this must be valid
890 } ADDR_COMPUTE_HTILE_INFO_INPUT;
891
892 /**
893 ****************************************************************************************************
894 * ADDR_COMPUTE_HTILE_INFO_OUTPUT
895 *
896 * @brief
897 * Output structure of AddrComputeHtileInfo
898 ****************************************************************************************************
899 */
900 typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
901 {
902 UINT_32 size; ///< Size of this structure in bytes
903
904 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this
905 /// HTile buffer. This might be larger than original depth
906 /// buffer pitch when called with an unaligned pitch.
907 UINT_32 height; ///< Height in pixels, as above
908 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes
909 UINT_32 baseAlign; ///< Base alignment
910 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block!
911 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
912 UINT_32 macroHeight; ///< Macro height in pixels
913 UINT_64 sliceSize; ///< Slice size, in bytes.
914 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
915 /// Compute engine clear can't be used if htile is interleaved
916 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in
917 /// next mip level, it also indicates if memory set based
918 /// fast clear can be used for current mip level.
919 } ADDR_COMPUTE_HTILE_INFO_OUTPUT;
920
921 /**
922 ****************************************************************************************************
923 * AddrComputeHtileInfo
924 *
925 * @brief
926 * Compute Htile pitch, height, base alignment and size in bytes
927 ****************************************************************************************************
928 */
929 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
930 ADDR_HANDLE hLib,
931 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
932 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut);
933
934
935
936 /**
937 ****************************************************************************************************
938 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
939 *
940 * @brief
941 * Input structure for AddrComputeHtileAddrFromCoord
942 ****************************************************************************************************
943 */
944 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
945 {
946 UINT_32 size; ///< Size of this structure in bytes
947
948 UINT_32 pitch; ///< Pitch, in pixels
949 UINT_32 height; ///< Height in pixels
950 UINT_32 x; ///< X coordinate
951 UINT_32 y; ///< Y coordinate
952 UINT_32 slice; ///< Index of slice
953 UINT_32 numSlices; ///< Number of slices
954 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
955 ADDR_HTILE_FLAGS flags; ///< htile flags
956 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
957 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
958 ADDR_TILEINFO* pTileInfo; ///< Tile info
959
960 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
961 /// while the global useTileIndex is set to 1
962 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
963 ///< README: When tileIndex is not -1, this must be valid
964 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size
965 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address
966 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
967
968 /**
969 ****************************************************************************************************
970 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
971 *
972 * @brief
973 * Output structure for AddrComputeHtileAddrFromCoord
974 ****************************************************************************************************
975 */
976 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
977 {
978 UINT_32 size; ///< Size of this structure in bytes
979
980 UINT_64 addr; ///< Address in bytes
981 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method.
982 /// So we keep bitPosition for HTILE as well
983 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
984
985 /**
986 ****************************************************************************************************
987 * AddrComputeHtileAddrFromCoord
988 *
989 * @brief
990 * Compute Htile address according to coordinates (of depth buffer)
991 ****************************************************************************************************
992 */
993 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
994 ADDR_HANDLE hLib,
995 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
996 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
997
998
999
1000 /**
1001 ****************************************************************************************************
1002 * ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
1003 *
1004 * @brief
1005 * Input structure for AddrComputeHtileCoordFromAddr
1006 ****************************************************************************************************
1007 */
1008 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
1009 {
1010 UINT_32 size; ///< Size of this structure in bytes
1011
1012 UINT_64 addr; ///< Address
1013 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods
1014 /// so we keep bitPosition for HTILE as well
1015 UINT_32 pitch; ///< Pitch, in pixels
1016 UINT_32 height; ///< Height, in pixels
1017 UINT_32 numSlices; ///< Number of slices
1018 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
1019 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1020 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1021 ADDR_TILEINFO* pTileInfo; ///< Tile info
1022
1023 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1024 /// while the global useTileIndex is set to 1
1025 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1026 ///< README: When tileIndex is not -1, this must be valid
1027 } ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT;
1028
1029 /**
1030 ****************************************************************************************************
1031 * ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1032 *
1033 * @brief
1034 * Output structure for AddrComputeHtileCoordFromAddr
1035 ****************************************************************************************************
1036 */
1037 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1038 {
1039 UINT_32 size; ///< Size of this structure in bytes
1040
1041 UINT_32 x; ///< X coordinate
1042 UINT_32 y; ///< Y coordinate
1043 UINT_32 slice; ///< Slice index
1044 } ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
1045
1046 /**
1047 ****************************************************************************************************
1048 * AddrComputeHtileCoordFromAddr
1049 *
1050 * @brief
1051 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to
1052 * Htile address
1053 ****************************************************************************************************
1054 */
1055 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
1056 ADDR_HANDLE hLib,
1057 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
1058 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
1059
1060
1061
1062 ////////////////////////////////////////////////////////////////////////////////////////////////////
1063 // C-mask functions
1064 ////////////////////////////////////////////////////////////////////////////////////////////////////
1065
1066 /**
1067 ****************************************************************************************************
1068 * ADDR_CMASK_FLAGS
1069 *
1070 * @brief
1071 * CMASK flags
1072 ****************************************************************************************************
1073 */
1074 typedef union _ADDR_CMASK_FLAGS
1075 {
1076 struct
1077 {
1078 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
1079 UINT_32 reserved :31; ///< Reserved bits
1080 };
1081
1082 UINT_32 value;
1083 } ADDR_CMASK_FLAGS;
1084
1085 /**
1086 ****************************************************************************************************
1087 * ADDR_COMPUTE_CMASK_INFO_INPUT
1088 *
1089 * @brief
1090 * Input structure of AddrComputeCmaskInfo
1091 ****************************************************************************************************
1092 */
1093 typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT
1094 {
1095 UINT_32 size; ///< Size of this structure in bytes
1096
1097 ADDR_CMASK_FLAGS flags; ///< CMASK flags
1098 UINT_32 pitch; ///< Pitch, in pixels, of color buffer
1099 UINT_32 height; ///< Height, in pixels, of color buffer
1100 UINT_32 numSlices; ///< Number of slices, of color buffer
1101 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1102 ADDR_TILEINFO* pTileInfo; ///< Tile info
1103
1104 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1105 /// while the global useTileIndex is set to 1
1106 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1107 ///< README: When tileIndex is not -1, this must be valid
1108 } ADDR_COMPUTE_CMASK_INFO_INPUT;
1109
1110 /**
1111 ****************************************************************************************************
1112 * ADDR_COMPUTE_CMASK_INFO_OUTPUT
1113 *
1114 * @brief
1115 * Output structure of AddrComputeCmaskInfo
1116 ****************************************************************************************************
1117 */
1118 typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT
1119 {
1120 UINT_32 size; ///< Size of this structure in bytes
1121
1122 UINT_32 pitch; ///< Pitch in pixels of color buffer which
1123 /// this Cmask matches. The size might be larger than
1124 /// original color buffer pitch when called with
1125 /// an unaligned pitch.
1126 UINT_32 height; ///< Height in pixels, as above
1127 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer
1128 UINT_32 baseAlign; ///< Base alignment
1129 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register
1130 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
1131 UINT_32 macroHeight; ///< Macro height in pixels
1132 UINT_64 sliceSize; ///< Slice size, in bytes.
1133 } ADDR_COMPUTE_CMASK_INFO_OUTPUT;
1134
1135 /**
1136 ****************************************************************************************************
1137 * AddrComputeCmaskInfo
1138 *
1139 * @brief
1140 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer
1141 * info
1142 ****************************************************************************************************
1143 */
1144 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
1145 ADDR_HANDLE hLib,
1146 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
1147 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut);
1148
1149
1150
1151 /**
1152 ****************************************************************************************************
1153 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1154 *
1155 * @brief
1156 * Input structure for AddrComputeCmaskAddrFromCoord
1157 *
1158 ****************************************************************************************************
1159 */
1160 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1161 {
1162 UINT_32 size; ///< Size of this structure in bytes
1163 UINT_32 x; ///< X coordinate
1164 UINT_32 y; ///< Y coordinate
1165 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask
1166 UINT_32 slice; ///< Slice index
1167 UINT_32 pitch; ///< Pitch in pixels, of color buffer
1168 UINT_32 height; ///< Height in pixels, of color buffer
1169 UINT_32 numSlices; ///< Number of slices
1170 UINT_32 bpp;
1171 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1172 ADDR_CMASK_FLAGS flags; ///< CMASK flags
1173 ADDR_TILEINFO* pTileInfo; ///< Tile info
1174
1175 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1176 ///< while the global useTileIndex is set to 1
1177 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1178 ///< README: When tileIndex is not -1, this must be valid
1179 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
1180
1181 /**
1182 ****************************************************************************************************
1183 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1184 *
1185 * @brief
1186 * Output structure for AddrComputeCmaskAddrFromCoord
1187 ****************************************************************************************************
1188 */
1189 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1190 {
1191 UINT_32 size; ///< Size of this structure in bytes
1192
1193 UINT_64 addr; ///< CMASK address in bytes
1194 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1195 /// so the address may be located in bit 0 (0) or 4 (4)
1196 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
1197
1198 /**
1199 ****************************************************************************************************
1200 * AddrComputeCmaskAddrFromCoord
1201 *
1202 * @brief
1203 * Compute Cmask address according to coordinates (of MSAA color buffer)
1204 ****************************************************************************************************
1205 */
1206 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
1207 ADDR_HANDLE hLib,
1208 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
1209 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
1210
1211
1212
1213 /**
1214 ****************************************************************************************************
1215 * ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1216 *
1217 * @brief
1218 * Input structure for AddrComputeCmaskCoordFromAddr
1219 ****************************************************************************************************
1220 */
1221 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1222 {
1223 UINT_32 size; ///< Size of this structure in bytes
1224
1225 UINT_64 addr; ///< CMASK address in bytes
1226 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1227 /// so the address may be located in bit 0 (0) or 4 (4)
1228 UINT_32 pitch; ///< Pitch, in pixels
1229 UINT_32 height; ///< Height in pixels
1230 UINT_32 numSlices; ///< Number of slices
1231 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1232 ADDR_TILEINFO* pTileInfo; ///< Tile info
1233
1234 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1235 /// while the global useTileIndex is set to 1
1236 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1237 ///< README: When tileIndex is not -1, this must be valid
1238 } ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT;
1239
1240 /**
1241 ****************************************************************************************************
1242 * ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1243 *
1244 * @brief
1245 * Output structure for AddrComputeCmaskCoordFromAddr
1246 ****************************************************************************************************
1247 */
1248 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1249 {
1250 UINT_32 size; ///< Size of this structure in bytes
1251
1252 UINT_32 x; ///< X coordinate
1253 UINT_32 y; ///< Y coordinate
1254 UINT_32 slice; ///< Slice index
1255 } ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
1256
1257 /**
1258 ****************************************************************************************************
1259 * AddrComputeCmaskCoordFromAddr
1260 *
1261 * @brief
1262 * Compute coordinates within color buffer (1st pixel of a micro tile) according to
1263 * Cmask address
1264 ****************************************************************************************************
1265 */
1266 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
1267 ADDR_HANDLE hLib,
1268 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
1269 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
1270
1271
1272
1273 ////////////////////////////////////////////////////////////////////////////////////////////////////
1274 // F-mask functions
1275 ////////////////////////////////////////////////////////////////////////////////////////////////////
1276
1277 /**
1278 ****************************************************************************************************
1279 * ADDR_COMPUTE_FMASK_INFO_INPUT
1280 *
1281 * @brief
1282 * Input structure for AddrComputeFmaskInfo
1283 ****************************************************************************************************
1284 */
1285 typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT
1286 {
1287 UINT_32 size; ///< Size of this structure in bytes
1288
1289 AddrTileMode tileMode; ///< Tile mode
1290 UINT_32 pitch; ///< Surface pitch, in pixels
1291 UINT_32 height; ///< Surface height, in pixels
1292 UINT_32 numSlices; ///< Number of slice/depth
1293 UINT_32 numSamples; ///< Number of samples
1294 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
1295 /// number of samples for normal AA; Set it to the
1296 /// number of fragments for EQAA
1297 /// r800 and later HWL parameters
1298 struct
1299 {
1300 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used
1301 /// by H/W clients. S/W should always set it to FALSE.
1302 UINT_32 reserved: 31; ///< Reserved for future use.
1303 };
1304 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data
1305 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1306 /// while the global useTileIndex is set to 1
1307 } ADDR_COMPUTE_FMASK_INFO_INPUT;
1308
1309 /**
1310 ****************************************************************************************************
1311 * ADDR_COMPUTE_FMASK_INFO_OUTPUT
1312 *
1313 * @brief
1314 * Output structure for AddrComputeFmaskInfo
1315 ****************************************************************************************************
1316 */
1317 typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT
1318 {
1319 UINT_32 size; ///< Size of this structure in bytes
1320
1321 UINT_32 pitch; ///< Pitch of fmask in pixels
1322 UINT_32 height; ///< Height of fmask in pixels
1323 UINT_32 numSlices; ///< Slices of fmask
1324 UINT_64 fmaskBytes; ///< Size of fmask in bytes
1325 UINT_32 baseAlign; ///< Base address alignment
1326 UINT_32 pitchAlign; ///< Pitch alignment
1327 UINT_32 heightAlign; ///< Height alignment
1328 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes
1329 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input
1330 /// may be changed in 9xx and above
1331 /// r800 and later HWL parameters
1332 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different
1333 /// bank_height from color buffer
1334 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1335 /// while the global useTileIndex is set to 1
1336 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1337 UINT_64 sliceSize; ///< Size of slice in bytes
1338 } ADDR_COMPUTE_FMASK_INFO_OUTPUT;
1339
1340 /**
1341 ****************************************************************************************************
1342 * AddrComputeFmaskInfo
1343 *
1344 * @brief
1345 * Compute Fmask pitch/height/depth/alignments and size in bytes
1346 ****************************************************************************************************
1347 */
1348 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
1349 ADDR_HANDLE hLib,
1350 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
1351 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
1352
1353
1354
1355 /**
1356 ****************************************************************************************************
1357 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1358 *
1359 * @brief
1360 * Input structure for AddrComputeFmaskAddrFromCoord
1361 ****************************************************************************************************
1362 */
1363 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1364 {
1365 UINT_32 size; ///< Size of this structure in bytes
1366
1367 UINT_32 x; ///< X coordinate
1368 UINT_32 y; ///< Y coordinate
1369 UINT_32 slice; ///< Slice index
1370 UINT_32 plane; ///< Plane number
1371 UINT_32 sample; ///< Sample index (fragment index for EQAA)
1372
1373 UINT_32 pitch; ///< Surface pitch, in pixels
1374 UINT_32 height; ///< Surface height, in pixels
1375 UINT_32 numSamples; ///< Number of samples
1376 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
1377 /// number of samples for normal AA; Set it to the
1378 /// number of fragments for EQAA
1379
1380 AddrTileMode tileMode; ///< Tile mode
1381 union
1382 {
1383 struct
1384 {
1385 UINT_32 bankSwizzle; ///< Bank swizzle
1386 UINT_32 pipeSwizzle; ///< Pipe swizzle
1387 };
1388 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
1389 };
1390
1391 /// r800 and later HWL parameters
1392 struct
1393 {
1394 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients
1395 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.
1396 UINT_32 reserved: 30; ///< Reserved for future use.
1397 };
1398 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data
1399
1400 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
1401
1402 /**
1403 ****************************************************************************************************
1404 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1405 *
1406 * @brief
1407 * Output structure for AddrComputeFmaskAddrFromCoord
1408 ****************************************************************************************************
1409 */
1410 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1411 {
1412 UINT_32 size; ///< Size of this structure in bytes
1413
1414 UINT_64 addr; ///< Fmask address
1415 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.
1416 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
1417
1418 /**
1419 ****************************************************************************************************
1420 * AddrComputeFmaskAddrFromCoord
1421 *
1422 * @brief
1423 * Compute Fmask address according to coordinates (x,y,slice,sample,plane)
1424 ****************************************************************************************************
1425 */
1426 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
1427 ADDR_HANDLE hLib,
1428 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
1429 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
1430
1431
1432
1433 /**
1434 ****************************************************************************************************
1435 * ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1436 *
1437 * @brief
1438 * Input structure for AddrComputeFmaskCoordFromAddr
1439 ****************************************************************************************************
1440 */
1441 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1442 {
1443 UINT_32 size; ///< Size of this structure in bytes
1444
1445 UINT_64 addr; ///< Address
1446 UINT_32 bitPosition; ///< Bit position within addr, 0-7.
1447
1448 UINT_32 pitch; ///< Pitch, in pixels
1449 UINT_32 height; ///< Height in pixels
1450 UINT_32 numSamples; ///< Number of samples
1451 UINT_32 numFrags; ///< Number of fragments
1452 AddrTileMode tileMode; ///< Tile mode
1453 union
1454 {
1455 struct
1456 {
1457 UINT_32 bankSwizzle; ///< Bank swizzle
1458 UINT_32 pipeSwizzle; ///< Pipe swizzle
1459 };
1460 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
1461 };
1462
1463 /// r800 and later HWL parameters
1464 struct
1465 {
1466 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components
1467 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.
1468 UINT_32 reserved: 30; ///< Reserved for future use.
1469 };
1470 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1471
1472 } ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT;
1473
1474 /**
1475 ****************************************************************************************************
1476 * ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1477 *
1478 * @brief
1479 * Output structure for AddrComputeFmaskCoordFromAddr
1480 ****************************************************************************************************
1481 */
1482 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1483 {
1484 UINT_32 size; ///< Size of this structure in bytes
1485
1486 UINT_32 x; ///< X coordinate
1487 UINT_32 y; ///< Y coordinate
1488 UINT_32 slice; ///< Slice index
1489 UINT_32 plane; ///< Plane number
1490 UINT_32 sample; ///< Sample index (fragment index for EQAA)
1491 } ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
1492
1493 /**
1494 ****************************************************************************************************
1495 * AddrComputeFmaskCoordFromAddr
1496 *
1497 * @brief
1498 * Compute FMASK coordinate from an given address
1499 ****************************************************************************************************
1500 */
1501 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
1502 ADDR_HANDLE hLib,
1503 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
1504 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
1505
1506
1507
1508 ////////////////////////////////////////////////////////////////////////////////////////////////////
1509 // Element/utility functions
1510 ////////////////////////////////////////////////////////////////////////////////////////////////////
1511
1512 /**
1513 ****************************************************************************************************
1514 * AddrGetVersion
1515 *
1516 * @brief
1517 * Get AddrLib version number
1518 ****************************************************************************************************
1519 */
1520 UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib);
1521
1522 /**
1523 ****************************************************************************************************
1524 * AddrUseTileIndex
1525 *
1526 * @brief
1527 * Return TRUE if tileIndex is enabled in this address library
1528 ****************************************************************************************************
1529 */
1530 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);
1531
1532 /**
1533 ****************************************************************************************************
1534 * AddrUseCombinedSwizzle
1535 *
1536 * @brief
1537 * Return TRUE if combined swizzle is enabled in this address library
1538 ****************************************************************************************************
1539 */
1540 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);
1541
1542 /**
1543 ****************************************************************************************************
1544 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1545 *
1546 * @brief
1547 * Input structure of AddrExtractBankPipeSwizzle
1548 ****************************************************************************************************
1549 */
1550 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1551 {
1552 UINT_32 size; ///< Size of this structure in bytes
1553
1554 UINT_32 base256b; ///< Base256b value
1555
1556 /// r800 and later HWL parameters
1557 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1558
1559 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1560 /// while the global useTileIndex is set to 1
1561 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1562 ///< README: When tileIndex is not -1, this must be valid
1563 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT;
1564
1565 /**
1566 ****************************************************************************************************
1567 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1568 *
1569 * @brief
1570 * Output structure of AddrExtractBankPipeSwizzle
1571 ****************************************************************************************************
1572 */
1573 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1574 {
1575 UINT_32 size; ///< Size of this structure in bytes
1576
1577 UINT_32 bankSwizzle; ///< Bank swizzle
1578 UINT_32 pipeSwizzle; ///< Pipe swizzle
1579 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT;
1580
1581 /**
1582 ****************************************************************************************************
1583 * AddrExtractBankPipeSwizzle
1584 *
1585 * @brief
1586 * Extract Bank and Pipe swizzle from base256b
1587 * @return
1588 * ADDR_OK if no error
1589 ****************************************************************************************************
1590 */
1591 ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
1592 ADDR_HANDLE hLib,
1593 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
1594 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut);
1595
1596
1597 /**
1598 ****************************************************************************************************
1599 * ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1600 *
1601 * @brief
1602 * Input structure of AddrCombineBankPipeSwizzle
1603 ****************************************************************************************************
1604 */
1605 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1606 {
1607 UINT_32 size; ///< Size of this structure in bytes
1608
1609 UINT_32 bankSwizzle; ///< Bank swizzle
1610 UINT_32 pipeSwizzle; ///< Pipe swizzle
1611 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients)
1612
1613 /// r800 and later HWL parameters
1614 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1615
1616 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1617 /// while the global useTileIndex is set to 1
1618 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1619 ///< README: When tileIndex is not -1, this must be valid
1620 } ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT;
1621
1622 /**
1623 ****************************************************************************************************
1624 * ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1625 *
1626 * @brief
1627 * Output structure of AddrCombineBankPipeSwizzle
1628 ****************************************************************************************************
1629 */
1630 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1631 {
1632 UINT_32 size; ///< Size of this structure in bytes
1633
1634 UINT_32 tileSwizzle; ///< Combined swizzle
1635 } ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT;
1636
1637 /**
1638 ****************************************************************************************************
1639 * AddrCombineBankPipeSwizzle
1640 *
1641 * @brief
1642 * Combine Bank and Pipe swizzle
1643 * @return
1644 * ADDR_OK if no error
1645 * @note
1646 * baseAddr here is full MCAddress instead of base256b
1647 ****************************************************************************************************
1648 */
1649 ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
1650 ADDR_HANDLE hLib,
1651 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,
1652 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut);
1653
1654
1655
1656 /**
1657 ****************************************************************************************************
1658 * ADDR_COMPUTE_SLICESWIZZLE_INPUT
1659 *
1660 * @brief
1661 * Input structure of AddrComputeSliceSwizzle
1662 ****************************************************************************************************
1663 */
1664 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
1665 {
1666 UINT_32 size; ///< Size of this structure in bytes
1667
1668 AddrTileMode tileMode; ///< Tile Mode
1669 UINT_32 baseSwizzle; ///< Base tile swizzle
1670 UINT_32 slice; ///< Slice index
1671 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases
1672
1673 /// r800 and later HWL parameters
1674 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1675
1676 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1677 /// while the global useTileIndex is set to 1
1678 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1679 ///< README: When tileIndex is not -1, this must be valid
1680 } ADDR_COMPUTE_SLICESWIZZLE_INPUT;
1681
1682
1683
1684 /**
1685 ****************************************************************************************************
1686 * ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1687 *
1688 * @brief
1689 * Output structure of AddrComputeSliceSwizzle
1690 ****************************************************************************************************
1691 */
1692 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1693 {
1694 UINT_32 size; ///< Size of this structure in bytes
1695
1696 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value
1697 } ADDR_COMPUTE_SLICESWIZZLE_OUTPUT;
1698
1699 /**
1700 ****************************************************************************************************
1701 * AddrComputeSliceSwizzle
1702 *
1703 * @brief
1704 * Extract Bank and Pipe swizzle from base256b
1705 * @return
1706 * ADDR_OK if no error
1707 ****************************************************************************************************
1708 */
1709 ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
1710 ADDR_HANDLE hLib,
1711 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
1712 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut);
1713
1714
1715 /**
1716 ****************************************************************************************************
1717 * AddrSwizzleGenOption
1718 *
1719 * @brief
1720 * Which swizzle generating options: legacy or linear
1721 ****************************************************************************************************
1722 */
1723 typedef enum _AddrSwizzleGenOption
1724 {
1725 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle
1726 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle
1727 } AddrSwizzleGenOption;
1728
1729 /**
1730 ****************************************************************************************************
1731 * AddrSwizzleOption
1732 *
1733 * @brief
1734 * Controls how swizzle is generated
1735 ****************************************************************************************************
1736 */
1737 typedef union _ADDR_SWIZZLE_OPTION
1738 {
1739 struct
1740 {
1741 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption
1742 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits
1743 UINT_32 reserved :30; ///< Reserved bits
1744 };
1745
1746 UINT_32 value;
1747
1748 } ADDR_SWIZZLE_OPTION;
1749
1750 /**
1751 ****************************************************************************************************
1752 * ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1753 *
1754 * @brief
1755 * Input structure of AddrComputeBaseSwizzle
1756 ****************************************************************************************************
1757 */
1758 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1759 {
1760 UINT_32 size; ///< Size of this structure in bytes
1761
1762 ADDR_SWIZZLE_OPTION option; ///< Swizzle option
1763 UINT_32 surfIndex; ///< Index of this surface type
1764 AddrTileMode tileMode; ///< Tile Mode
1765
1766 /// r800 and later HWL parameters
1767 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1768
1769 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1770 /// while the global useTileIndex is set to 1
1771 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1772 ///< README: When tileIndex is not -1, this must be valid
1773 } ADDR_COMPUTE_BASE_SWIZZLE_INPUT;
1774
1775 /**
1776 ****************************************************************************************************
1777 * ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1778 *
1779 * @brief
1780 * Output structure of AddrComputeBaseSwizzle
1781 ****************************************************************************************************
1782 */
1783 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1784 {
1785 UINT_32 size; ///< Size of this structure in bytes
1786
1787 UINT_32 tileSwizzle; ///< Combined swizzle
1788 } ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT;
1789
1790 /**
1791 ****************************************************************************************************
1792 * AddrComputeBaseSwizzle
1793 *
1794 * @brief
1795 * Return a Combined Bank and Pipe swizzle base on surface based on surface type/index
1796 * @return
1797 * ADDR_OK if no error
1798 ****************************************************************************************************
1799 */
1800 ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
1801 ADDR_HANDLE hLib,
1802 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
1803 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut);
1804
1805
1806
1807 /**
1808 ****************************************************************************************************
1809 * ELEM_GETEXPORTNORM_INPUT
1810 *
1811 * @brief
1812 * Input structure for ElemGetExportNorm
1813 *
1814 ****************************************************************************************************
1815 */
1816 typedef struct _ELEM_GETEXPORTNORM_INPUT
1817 {
1818 UINT_32 size; ///< Size of this structure in bytes
1819
1820 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat
1821 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType
1822 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap
1823 UINT_32 numSamples; ///< Number of samples
1824 } ELEM_GETEXPORTNORM_INPUT;
1825
1826 /**
1827 ****************************************************************************************************
1828 * ElemGetExportNorm
1829 *
1830 * @brief
1831 * Helper function to check one format can be EXPORT_NUM, which is a register
1832 * CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600
1833 * family
1834 * @note
1835 * The implementation is only for r600.
1836 * 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two
1837 * clocks per export)
1838 * 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one
1839 * clock per export)
1840 *
1841 ****************************************************************************************************
1842 */
1843 BOOL_32 ADDR_API ElemGetExportNorm(
1844 ADDR_HANDLE hLib,
1845 const ELEM_GETEXPORTNORM_INPUT* pIn);
1846
1847
1848
1849 /**
1850 ****************************************************************************************************
1851 * ELEM_FLT32TODEPTHPIXEL_INPUT
1852 *
1853 * @brief
1854 * Input structure for addrFlt32ToDepthPixel
1855 *
1856 ****************************************************************************************************
1857 */
1858 typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT
1859 {
1860 UINT_32 size; ///< Size of this structure in bytes
1861
1862 AddrDepthFormat format; ///< Depth buffer format
1863 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil)
1864 } ELEM_FLT32TODEPTHPIXEL_INPUT;
1865
1866 /**
1867 ****************************************************************************************************
1868 * ELEM_FLT32TODEPTHPIXEL_INPUT
1869 *
1870 * @brief
1871 * Output structure for ElemFlt32ToDepthPixel
1872 *
1873 ****************************************************************************************************
1874 */
1875 typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT
1876 {
1877 UINT_32 size; ///< Size of this structure in bytes
1878
1879 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer.
1880 /// Client must provide enough storage for this type.
1881 UINT_32 depthBase; ///< Tile base in bits for depth bits
1882 UINT_32 stencilBase; ///< Tile base in bits for stencil bits
1883 UINT_32 depthBits; ///< Bits for depth
1884 UINT_32 stencilBits; ///< Bits for stencil
1885 } ELEM_FLT32TODEPTHPIXEL_OUTPUT;
1886
1887 /**
1888 ****************************************************************************************************
1889 * ElemFlt32ToDepthPixel
1890 *
1891 * @brief
1892 * Convert a FLT_32 value to a depth/stencil pixel value
1893 *
1894 * @return
1895 * Return code
1896 *
1897 ****************************************************************************************************
1898 */
1899 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
1900 ADDR_HANDLE hLib,
1901 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
1902 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut);
1903
1904
1905
1906 /**
1907 ****************************************************************************************************
1908 * ELEM_FLT32TOCOLORPIXEL_INPUT
1909 *
1910 * @brief
1911 * Input structure for addrFlt32ToColorPixel
1912 *
1913 ****************************************************************************************************
1914 */
1915 typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT
1916 {
1917 UINT_32 size; ///< Size of this structure in bytes
1918
1919 AddrColorFormat format; ///< Color buffer format
1920 AddrSurfaceNumber surfNum; ///< Surface number
1921 AddrSurfaceSwap surfSwap; ///< Surface swap
1922 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a)
1923 } ELEM_FLT32TOCOLORPIXEL_INPUT;
1924
1925 /**
1926 ****************************************************************************************************
1927 * ELEM_FLT32TOCOLORPIXEL_INPUT
1928 *
1929 * @brief
1930 * Output structure for ElemFlt32ToColorPixel
1931 *
1932 ****************************************************************************************************
1933 */
1934 typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT
1935 {
1936 UINT_32 size; ///< Size of this structure in bytes
1937
1938 UINT_8* pPixel; ///< Real color value. Same data type as color buffer.
1939 /// Client must provide enough storage for this type.
1940 } ELEM_FLT32TOCOLORPIXEL_OUTPUT;
1941
1942 /**
1943 ****************************************************************************************************
1944 * ElemFlt32ToColorPixel
1945 *
1946 * @brief
1947 * Convert a FLT_32 value to a red/green/blue/alpha pixel value
1948 *
1949 * @return
1950 * Return code
1951 *
1952 ****************************************************************************************************
1953 */
1954 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
1955 ADDR_HANDLE hLib,
1956 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
1957 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut);
1958
1959
1960 /**
1961 ****************************************************************************************************
1962 * ADDR_CONVERT_TILEINFOTOHW_INPUT
1963 *
1964 * @brief
1965 * Input structure for AddrConvertTileInfoToHW
1966 * @note
1967 * When reverse is TRUE, indices are igonred
1968 ****************************************************************************************************
1969 */
1970 typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT
1971 {
1972 UINT_32 size; ///< Size of this structure in bytes
1973 BOOL_32 reverse; ///< Convert control flag.
1974 /// FALSE: convert from real value to HW value;
1975 /// TRUE: convert from HW value to real value.
1976
1977 /// r800 and later HWL parameters
1978 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value
1979
1980 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1981 /// while the global useTileIndex is set to 1
1982 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1983 ///< README: When tileIndex is not -1, this must be valid
1984 UINT_32 bpp; ///< Bits per pixel
1985 } ADDR_CONVERT_TILEINFOTOHW_INPUT;
1986
1987 /**
1988 ****************************************************************************************************
1989 * ADDR_CONVERT_TILEINFOTOHW_OUTPUT
1990 *
1991 * @brief
1992 * Output structure for AddrConvertTileInfoToHW
1993 ****************************************************************************************************
1994 */
1995 typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT
1996 {
1997 UINT_32 size; ///< Size of this structure in bytes
1998
1999 /// r800 and later HWL parameters
2000 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value
2001
2002 } ADDR_CONVERT_TILEINFOTOHW_OUTPUT;
2003
2004 /**
2005 ****************************************************************************************************
2006 * AddrConvertTileInfoToHW
2007 *
2008 * @brief
2009 * Convert tile info from real value to hardware register value
2010 ****************************************************************************************************
2011 */
2012 ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
2013 ADDR_HANDLE hLib,
2014 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
2015 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut);
2016
2017
2018
2019 /**
2020 ****************************************************************************************************
2021 * ADDR_CONVERT_TILEINDEX_INPUT
2022 *
2023 * @brief
2024 * Input structure for AddrConvertTileIndex
2025 ****************************************************************************************************
2026 */
2027 typedef struct _ADDR_CONVERT_TILEINDEX_INPUT
2028 {
2029 UINT_32 size; ///< Size of this structure in bytes
2030
2031 INT_32 tileIndex; ///< Tile index
2032 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2033 UINT_32 bpp; ///< Bits per pixel
2034 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2035 } ADDR_CONVERT_TILEINDEX_INPUT;
2036
2037 /**
2038 ****************************************************************************************************
2039 * ADDR_CONVERT_TILEINDEX_OUTPUT
2040 *
2041 * @brief
2042 * Output structure for AddrConvertTileIndex
2043 ****************************************************************************************************
2044 */
2045 typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT
2046 {
2047 UINT_32 size; ///< Size of this structure in bytes
2048
2049 AddrTileMode tileMode; ///< Tile mode
2050 AddrTileType tileType; ///< Tile type
2051 ADDR_TILEINFO* pTileInfo; ///< Tile info
2052
2053 } ADDR_CONVERT_TILEINDEX_OUTPUT;
2054
2055 /**
2056 ****************************************************************************************************
2057 * AddrConvertTileIndex
2058 *
2059 * @brief
2060 * Convert tile index to tile mode/type/info
2061 ****************************************************************************************************
2062 */
2063 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex(
2064 ADDR_HANDLE hLib,
2065 const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
2066 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
2067
2068 /**
2069 ****************************************************************************************************
2070 * ADDR_GET_MACROMODEINDEX_INPUT
2071 *
2072 * @brief
2073 * Input structure for AddrGetMacroModeIndex
2074 ****************************************************************************************************
2075 */
2076 typedef struct _ADDR_GET_MACROMODEINDEX_INPUT
2077 {
2078 UINT_32 size; ///< Size of this structure in bytes
2079 ADDR_SURFACE_FLAGS flags; ///< Surface flag
2080 INT_32 tileIndex; ///< Tile index
2081 UINT_32 bpp; ///< Bits per pixel
2082 UINT_32 numFrags; ///< Number of color fragments
2083 } ADDR_GET_MACROMODEINDEX_INPUT;
2084
2085 /**
2086 ****************************************************************************************************
2087 * ADDR_GET_MACROMODEINDEX_OUTPUT
2088 *
2089 * @brief
2090 * Output structure for AddrGetMacroModeIndex
2091 ****************************************************************************************************
2092 */
2093 typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT
2094 {
2095 UINT_32 size; ///< Size of this structure in bytes
2096 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2097 } ADDR_GET_MACROMODEINDEX_OUTPUT;
2098
2099 /**
2100 ****************************************************************************************************
2101 * AddrGetMacroModeIndex
2102 *
2103 * @brief
2104 * Get macro mode index based on input parameters
2105 ****************************************************************************************************
2106 */
2107 ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex(
2108 ADDR_HANDLE hLib,
2109 const ADDR_GET_MACROMODEINDEX_INPUT* pIn,
2110 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut);
2111
2112 /**
2113 ****************************************************************************************************
2114 * ADDR_CONVERT_TILEINDEX1_INPUT
2115 *
2116 * @brief
2117 * Input structure for AddrConvertTileIndex1 (without macro mode index)
2118 ****************************************************************************************************
2119 */
2120 typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT
2121 {
2122 UINT_32 size; ///< Size of this structure in bytes
2123
2124 INT_32 tileIndex; ///< Tile index
2125 UINT_32 bpp; ///< Bits per pixel
2126 UINT_32 numSamples; ///< Number of samples
2127 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2128 } ADDR_CONVERT_TILEINDEX1_INPUT;
2129
2130 /**
2131 ****************************************************************************************************
2132 * AddrConvertTileIndex1
2133 *
2134 * @brief
2135 * Convert tile index to tile mode/type/info
2136 ****************************************************************************************************
2137 */
2138 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
2139 ADDR_HANDLE hLib,
2140 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
2141 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
2142
2143
2144
2145 /**
2146 ****************************************************************************************************
2147 * ADDR_GET_TILEINDEX_INPUT
2148 *
2149 * @brief
2150 * Input structure for AddrGetTileIndex
2151 ****************************************************************************************************
2152 */
2153 typedef struct _ADDR_GET_TILEINDEX_INPUT
2154 {
2155 UINT_32 size; ///< Size of this structure in bytes
2156
2157 AddrTileMode tileMode; ///< Tile mode
2158 AddrTileType tileType; ///< Tile-type: disp/non-disp/...
2159 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D
2160 } ADDR_GET_TILEINDEX_INPUT;
2161
2162 /**
2163 ****************************************************************************************************
2164 * ADDR_GET_TILEINDEX_OUTPUT
2165 *
2166 * @brief
2167 * Output structure for AddrGetTileIndex
2168 ****************************************************************************************************
2169 */
2170 typedef struct _ADDR_GET_TILEINDEX_OUTPUT
2171 {
2172 UINT_32 size; ///< Size of this structure in bytes
2173
2174 INT_32 index; ///< index in table
2175 } ADDR_GET_TILEINDEX_OUTPUT;
2176
2177 /**
2178 ****************************************************************************************************
2179 * AddrGetTileIndex
2180 *
2181 * @brief
2182 * Get the tiling mode index in table
2183 ****************************************************************************************************
2184 */
2185 ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
2186 ADDR_HANDLE hLib,
2187 const ADDR_GET_TILEINDEX_INPUT* pIn,
2188 ADDR_GET_TILEINDEX_OUTPUT* pOut);
2189
2190
2191
2192 /**
2193 ****************************************************************************************************
2194 * ADDR_PRT_INFO_INPUT
2195 *
2196 * @brief
2197 * Input structure for AddrComputePrtInfo
2198 ****************************************************************************************************
2199 */
2200 typedef struct _ADDR_PRT_INFO_INPUT
2201 {
2202 AddrFormat format; ///< Surface format
2203 UINT_32 baseMipWidth; ///< Base mipmap width
2204 UINT_32 baseMipHeight; ///< Base mipmap height
2205 UINT_32 baseMipDepth; ///< Base mipmap depth
2206 UINT_32 numFrags; ///< Number of fragments,
2207 } ADDR_PRT_INFO_INPUT;
2208
2209 /**
2210 ****************************************************************************************************
2211 * ADDR_PRT_INFO_OUTPUT
2212 *
2213 * @brief
2214 * Input structure for AddrComputePrtInfo
2215 ****************************************************************************************************
2216 */
2217 typedef struct _ADDR_PRT_INFO_OUTPUT
2218 {
2219 UINT_32 prtTileWidth;
2220 UINT_32 prtTileHeight;
2221 } ADDR_PRT_INFO_OUTPUT;
2222
2223 /**
2224 ****************************************************************************************************
2225 * AddrComputePrtInfo
2226 *
2227 * @brief
2228 * Compute prt surface related information
2229 ****************************************************************************************************
2230 */
2231 ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
2232 ADDR_HANDLE hLib,
2233 const ADDR_PRT_INFO_INPUT* pIn,
2234 ADDR_PRT_INFO_OUTPUT* pOut);
2235
2236
2237
2238 ////////////////////////////////////////////////////////////////////////////////////////////////////
2239 // DCC key functions
2240 ////////////////////////////////////////////////////////////////////////////////////////////////////
2241
2242 /**
2243 ****************************************************************************************************
2244 * _ADDR_COMPUTE_DCCINFO_INPUT
2245 *
2246 * @brief
2247 * Input structure of AddrComputeDccInfo
2248 ****************************************************************************************************
2249 */
2250 typedef struct _ADDR_COMPUTE_DCCINFO_INPUT
2251 {
2252 UINT_32 size; ///< Size of this structure in bytes
2253 UINT_32 bpp; ///< BitPP of color surface
2254 UINT_32 numSamples; ///< Sample number of color surface
2255 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound
2256 AddrTileMode tileMode; ///< Tile mode of color surface
2257 ADDR_TILEINFO tileInfo; ///< Tile info of color surface
2258 UINT_32 tileSwizzle; ///< Tile swizzle
2259 INT_32 tileIndex; ///< Tile index of color surface,
2260 ///< MUST be -1 if you don't want to use it
2261 ///< while the global useTileIndex is set to 1
2262 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2263 ///< README: When tileIndex is not -1, this must be valid
2264 } ADDR_COMPUTE_DCCINFO_INPUT;
2265
2266 /**
2267 ****************************************************************************************************
2268 * ADDR_COMPUTE_DCCINFO_OUTPUT
2269 *
2270 * @brief
2271 * Output structure of AddrComputeDccInfo
2272 ****************************************************************************************************
2273 */
2274 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
2275 {
2276 UINT_32 size; ///< Size of this structure in bytes
2277 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
2278 UINT_64 dccRamSize; ///< Size of dcc key
2279 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared
2280 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
2281 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned
2282 } ADDR_COMPUTE_DCCINFO_OUTPUT;
2283
2284 /**
2285 ****************************************************************************************************
2286 * AddrComputeDccInfo
2287 *
2288 * @brief
2289 * Compute DCC key size, base alignment
2290 * info
2291 ****************************************************************************************************
2292 */
2293 ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
2294 ADDR_HANDLE hLib,
2295 const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
2296 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);
2297
2298
2299
2300 /**
2301 ****************************************************************************************************
2302 * ADDR_GET_MAX_ALINGMENTS_OUTPUT
2303 *
2304 * @brief
2305 * Output structure of AddrGetMaxAlignments
2306 ****************************************************************************************************
2307 */
2308 typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
2309 {
2310 UINT_32 size; ///< Size of this structure in bytes
2311 UINT_32 baseAlign; ///< Maximum base alignment in bytes
2312 } ADDR_GET_MAX_ALINGMENTS_OUTPUT;
2313
2314 /**
2315 ****************************************************************************************************
2316 * AddrGetMaxAlignments
2317 *
2318 * @brief
2319 * Gets maximnum alignments
2320 ****************************************************************************************************
2321 */
2322 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
2323 ADDR_HANDLE hLib,
2324 ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
2325
2326 /**
2327 ****************************************************************************************************
2328 * AddrGetMaxMetaAlignments
2329 *
2330 * @brief
2331 * Gets maximnum alignments for metadata
2332 ****************************************************************************************************
2333 */
2334 ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
2335 ADDR_HANDLE hLib,
2336 ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
2337
2338 /**
2339 ****************************************************************************************************
2340 * Address library interface version 2
2341 * available from Gfx9 hardware
2342 ****************************************************************************************************
2343 * Addr2ComputeSurfaceInfo()
2344 * Addr2ComputeSurfaceAddrFromCoord()
2345 * Addr2ComputeSurfaceCoordFromAddr()
2346
2347 * Addr2ComputeHtileInfo()
2348 * Addr2ComputeHtileAddrFromCoord()
2349 * Addr2ComputeHtileCoordFromAddr()
2350 *
2351 * Addr2ComputeCmaskInfo()
2352 * Addr2ComputeCmaskAddrFromCoord()
2353 * Addr2ComputeCmaskCoordFromAddr()
2354 *
2355 * Addr2ComputeFmaskInfo()
2356 * Addr2ComputeFmaskAddrFromCoord()
2357 * Addr2ComputeFmaskCoordFromAddr()
2358 *
2359 * Addr2ComputeDccInfo()
2360 *
2361 **/
2362
2363
2364 ////////////////////////////////////////////////////////////////////////////////////////////////////
2365 // Surface functions for Gfx9
2366 ////////////////////////////////////////////////////////////////////////////////////////////////////
2367
2368 /**
2369 ****************************************************************************************************
2370 * ADDR2_SURFACE_FLAGS
2371 *
2372 * @brief
2373 * Surface flags
2374 ****************************************************************************************************
2375 */
2376 typedef union _ADDR2_SURFACE_FLAGS
2377 {
2378 struct
2379 {
2380 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV
2381 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV
2382 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV
2383 UINT_32 fmask : 1; ///< This is an fmask surface
2384 UINT_32 overlay : 1; ///< This is an overlay surface
2385 UINT_32 display : 1; ///< This resource is displable, can be used with DRV
2386 UINT_32 prt : 1; ///< This is a partially resident texture
2387 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface
2388 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
2389 UINT_32 texture : 1; ///< This resource can be used with SRV
2390 UINT_32 unordered : 1; ///< This resource can be used with UAV
2391 UINT_32 rotated : 1; ///< This resource is rotated and displable
2392 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible
2393 UINT_32 opt4space : 1; ///< This resource should be optimized for space
2394 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment
2395 UINT_32 noMetadata : 1; ///< This resource has no metadata
2396 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata
2397 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata
2398 UINT_32 reserved : 14; ///< Reserved bits
2399 };
2400
2401 UINT_32 value;
2402 } ADDR2_SURFACE_FLAGS;
2403
2404 /**
2405 ****************************************************************************************************
2406 * ADDR2_COMPUTE_SURFACE_INFO_INPUT
2407 *
2408 * @brief
2409 * Input structure for Addr2ComputeSurfaceInfo
2410 ****************************************************************************************************
2411 */
2412 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT
2413 {
2414 UINT_32 size; ///< Size of this structure in bytes
2415
2416 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2417 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9
2418 AddrResourceType resourceType; ///< Surface type
2419 AddrFormat format; ///< Surface format
2420 UINT_32 bpp; ///< bits per pixel
2421 UINT_32 width; ///< Width (of mip0), in pixels
2422 UINT_32 height; ///< Height (of mip0), in pixels
2423 UINT_32 numSlices; ///< Number surface slice/depth (of mip0),
2424 UINT_32 numMipLevels; ///< Total mipmap levels.
2425 UINT_32 numSamples; ///< Number of samples
2426 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2427 /// number of samples for normal AA; Set it to the
2428 /// number of fragments for EQAA
2429 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2430 UINT_32 sliceAlign; ///< Required slice size in bytes
2431 } ADDR2_COMPUTE_SURFACE_INFO_INPUT;
2432
2433 /**
2434 ****************************************************************************************************
2435 * ADDR2_MIP_INFO
2436 *
2437 * @brief
2438 * Structure that contains information for mip level
2439 *
2440 ****************************************************************************************************
2441 */
2442 typedef struct _ADDR2_MIP_INFO
2443 {
2444 UINT_32 pitch; ///< Pitch in elements
2445 UINT_32 height; ///< Padded height in elements
2446 UINT_32 depth; ///< Padded depth
2447 UINT_32 pixelPitch; ///< Pitch in pixels
2448 UINT_32 pixelHeight; ///< Padded height in pixels
2449 UINT_32 equationIndex; ///< Equation index in the equation table
2450 UINT_64 offset; ///< Offset in bytes from mip base, should only be used
2451 ///< to setup vam surface descriptor, can't be used
2452 ///< to setup swizzle pattern
2453 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base
2454 UINT_32 mipTailOffset; ///< mip tail offset in bytes
2455 UINT_32 mipTailCoordX; ///< mip tail coord x
2456 UINT_32 mipTailCoordY; ///< mip tail coord y
2457 UINT_32 mipTailCoordZ; ///< mip tail coord z
2458 } ADDR2_MIP_INFO;
2459
2460 /**
2461 ****************************************************************************************************
2462 * ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2463 *
2464 * @brief
2465 * Output structure for Addr2ComputeSurfInfo
2466 * @note
2467 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
2468 Pixel: Original pixel
2469 ****************************************************************************************************
2470 */
2471 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2472 {
2473 UINT_32 size; ///< Size of this structure in bytes
2474
2475 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats)
2476 UINT_32 height; ///< Padded height (of mip0) in elements
2477 UINT_32 numSlices; ///< Padded depth for 3d resource
2478 ///< or padded number of slices for 2d array resource
2479 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements
2480 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements
2481 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain)
2482 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes
2483 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes
2484 UINT_32 baseAlign; ///< Base address alignment
2485 UINT_32 bpp; ///< Bits per elements
2486 /// (e.g. blocks for BCn, 1/3 for 96bit)
2487 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels
2488 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels
2489 UINT_32 pixelPitch; ///< Pitch in original pixels
2490 UINT_32 pixelHeight; ///< Height in original pixels
2491 UINT_32 pixelBits; ///< Original bits per pixel, passed from input
2492
2493 UINT_32 blockWidth; ///< Width in element inside one block
2494 UINT_32 blockHeight; ///< Height in element inside one block
2495 UINT_32 blockSlices; ///< Slice number inside one block
2496 ///< Prt tile is one block, its width/height/slice
2497 ///< equals to blcok width/height/slice
2498
2499 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register
2500 /// Stereo info
2501 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE
2502 /// Mip info
2503 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array
2504 /// if it is not NULL, the array is assumed to
2505 /// contain numMipLevels entries
2506
2507 UINT_32 equationIndex; ///< Equation index in the equation table of mip0
2508 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block
2509 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip
2510 /// in tail, it will be set to number of mip levels
2511 } ADDR2_COMPUTE_SURFACE_INFO_OUTPUT;
2512
2513 /**
2514 ****************************************************************************************************
2515 * Addr2ComputeSurfaceInfo
2516 *
2517 * @brief
2518 * Compute surface width/height/slices/alignments and suitable tiling mode
2519 ****************************************************************************************************
2520 */
2521 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
2522 ADDR_HANDLE hLib,
2523 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
2524 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
2525
2526
2527
2528 /**
2529 ****************************************************************************************************
2530 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2531 *
2532 * @brief
2533 * Input structure for Addr2ComputeSurfaceAddrFromCoord
2534 ****************************************************************************************************
2535 */
2536 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2537 {
2538 UINT_32 size; ///< Size of this structure in bytes
2539
2540 UINT_32 x; ///< X coordinate
2541 UINT_32 y; ///< Y coordinate
2542 UINT_32 slice; ///< Slice index
2543 UINT_32 sample; ///< Sample index, use fragment index for EQAA
2544 UINT_32 mipId; ///< the mip ID in mip chain
2545
2546 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9
2547 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2548 AddrResourceType resourceType; ///< Surface type
2549 UINT_32 bpp; ///< Bits per pixel
2550 UINT_32 unalignedWidth; ///< Surface original width (of mip0)
2551 UINT_32 unalignedHeight; ///< Surface original height (of mip0)
2552 UINT_32 numSlices; ///< Surface original slices (of mip0)
2553 UINT_32 numMipLevels; ///< Total mipmap levels
2554 UINT_32 numSamples; ///< Number of samples
2555 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2556 /// number of samples for normal AA; Set it to the
2557 /// number of fragments for EQAA
2558
2559 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
2560 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2561 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
2562
2563 /**
2564 ****************************************************************************************************
2565 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2566 *
2567 * @brief
2568 * Output structure for Addr2ComputeSurfaceAddrFromCoord
2569 ****************************************************************************************************
2570 */
2571 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2572 {
2573 UINT_32 size; ///< Size of this structure in bytes
2574
2575 UINT_64 addr; ///< Byte address
2576 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.
2577 /// For surface bpp < 8, e.g. FMT_1.
2578 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)
2579 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
2580
2581 /**
2582 ****************************************************************************************************
2583 * Addr2ComputeSurfaceAddrFromCoord
2584 *
2585 * @brief
2586 * Compute surface address from a given coordinate.
2587 ****************************************************************************************************
2588 */
2589 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
2590 ADDR_HANDLE hLib,
2591 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
2592 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
2593
2594
2595
2596 /**
2597 ****************************************************************************************************
2598 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2599 *
2600 * @brief
2601 * Input structure for Addr2ComputeSurfaceCoordFromAddr
2602 ****************************************************************************************************
2603 */
2604 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2605 {
2606 UINT_32 size; ///< Size of this structure in bytes
2607
2608 UINT_64 addr; ///< Address in bytes
2609 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,
2610 /// e.g. FMT_1;
2611
2612 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9
2613 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2614 AddrResourceType resourceType; ///< Surface type
2615 UINT_32 bpp; ///< Bits per pixel
2616 UINT_32 unalignedWidth; ///< Surface original width (of mip0)
2617 UINT_32 unalignedHeight; ///< Surface original height (of mip0)
2618 UINT_32 numSlices; ///< Surface original slices (of mip0)
2619 UINT_32 numMipLevels; ///< Total mipmap levels.
2620 UINT_32 numSamples; ///< Number of samples
2621 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2622 /// number of samples for normal AA; Set it to the
2623 /// number of fragments for EQAA
2624
2625 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
2626 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2627 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
2628
2629 /**
2630 ****************************************************************************************************
2631 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2632 *
2633 * @brief
2634 * Output structure for Addr2ComputeSurfaceCoordFromAddr
2635 ****************************************************************************************************
2636 */
2637 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2638 {
2639 UINT_32 size; ///< Size of this structure in bytes
2640
2641 UINT_32 x; ///< X coordinate
2642 UINT_32 y; ///< Y coordinate
2643 UINT_32 slice; ///< Index of slices
2644 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
2645 UINT_32 mipId; ///< mipmap level id
2646 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
2647
2648 /**
2649 ****************************************************************************************************
2650 * Addr2ComputeSurfaceCoordFromAddr
2651 *
2652 * @brief
2653 * Compute coordinate from a given surface address
2654 ****************************************************************************************************
2655 */
2656 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
2657 ADDR_HANDLE hLib,
2658 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
2659 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
2660
2661
2662
2663 ////////////////////////////////////////////////////////////////////////////////////////////////////
2664 // HTile functions for Gfx9
2665 ////////////////////////////////////////////////////////////////////////////////////////////////////
2666
2667 /**
2668 ****************************************************************************************************
2669 * ADDR2_META_FLAGS
2670 *
2671 * @brief
2672 * Metadata flags
2673 ****************************************************************************************************
2674 */
2675 typedef union _ADDR2_META_FLAGS
2676 {
2677 struct
2678 {
2679 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned
2680 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned
2681 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this!
2682 UINT_32 reserved : 29; ///< Reserved bits
2683 };
2684
2685 UINT_32 value;
2686 } ADDR2_META_FLAGS;
2687
2688 /**
2689 ****************************************************************************************************
2690 * ADDR2_META_MIP_INFO
2691 *
2692 * @brief
2693 * Structure to store per mip metadata information
2694 ****************************************************************************************************
2695 */
2696 typedef struct _ADDR2_META_MIP_INFO
2697 {
2698 BOOL_32 inMiptail;
2699 union
2700 {
2701 struct
2702 {
2703 UINT_32 startX;
2704 UINT_32 startY;
2705 UINT_32 startZ;
2706 UINT_32 width;
2707 UINT_32 height;
2708 UINT_32 depth;
2709 };
2710
2711 struct
2712 {
2713 UINT_32 offset;
2714 UINT_32 sliceSize;
2715 };
2716 };
2717 } ADDR2_META_MIP_INFO;
2718
2719 /**
2720 ****************************************************************************************************
2721 * ADDR2_COMPUTE_HTILE_INFO_INPUT
2722 *
2723 * @brief
2724 * Input structure of Addr2ComputeHtileInfo
2725 ****************************************************************************************************
2726 */
2727 typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
2728 {
2729 UINT_32 size; ///< Size of this structure in bytes
2730
2731 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2732 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags
2733 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2734 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2735 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2736 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)
2737 UINT_32 numMipLevels; ///< Total mipmap levels of color surface
2738 UINT_32 firstMipIdInTail;
2739 } ADDR2_COMPUTE_HTILE_INFO_INPUT;
2740
2741 /**
2742 ****************************************************************************************************
2743 * ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2744 *
2745 * @brief
2746 * Output structure of Addr2ComputeHtileInfo
2747 ****************************************************************************************************
2748 */
2749 typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2750 {
2751 UINT_32 size; ///< Size of this structure in bytes
2752
2753 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this
2754 /// HTile buffer. This might be larger than original depth
2755 /// buffer pitch when called with an unaligned pitch.
2756 UINT_32 height; ///< Height in pixels, as above
2757 UINT_32 baseAlign; ///< Base alignment
2758 UINT_32 sliceSize; ///< Slice size, in bytes.
2759 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes
2760 UINT_32 metaBlkWidth; ///< Meta block width
2761 UINT_32 metaBlkHeight; ///< Meta block height
2762 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
2763
2764 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information
2765 } ADDR2_COMPUTE_HTILE_INFO_OUTPUT;
2766
2767 /**
2768 ****************************************************************************************************
2769 * Addr2ComputeHtileInfo
2770 *
2771 * @brief
2772 * Compute Htile pitch, height, base alignment and size in bytes
2773 ****************************************************************************************************
2774 */
2775 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
2776 ADDR_HANDLE hLib,
2777 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
2778 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut);
2779
2780
2781
2782 /**
2783 ****************************************************************************************************
2784 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2785 *
2786 * @brief
2787 * Input structure for Addr2ComputeHtileAddrFromCoord
2788 ****************************************************************************************************
2789 */
2790 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2791 {
2792 UINT_32 size; ///< Size of this structure in bytes
2793
2794 UINT_32 x; ///< X coordinate
2795 UINT_32 y; ///< Y coordinate
2796 UINT_32 slice; ///< Index of slices
2797 UINT_32 mipId; ///< mipmap level id
2798
2799 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2800 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags
2801 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2802 UINT_32 bpp; ///< Depth surface bits per pixel
2803 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2804 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2805 UINT_32 numSlices; ///< Depth surface original depth (of mip0)
2806 UINT_32 numMipLevels; ///< Depth surface total mipmap levels
2807 UINT_32 numSamples; ///< Depth surface number of samples
2808 UINT_32 pipeXor; ///< Pipe xor setting
2809 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
2810
2811 /**
2812 ****************************************************************************************************
2813 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2814 *
2815 * @brief
2816 * Output structure for Addr2ComputeHtileAddrFromCoord
2817 ****************************************************************************************************
2818 */
2819 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2820 {
2821 UINT_32 size; ///< Size of this structure in bytes
2822
2823 UINT_64 addr; ///< Address in bytes
2824 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
2825
2826 /**
2827 ****************************************************************************************************
2828 * Addr2ComputeHtileAddrFromCoord
2829 *
2830 * @brief
2831 * Compute Htile address according to coordinates (of depth buffer)
2832 ****************************************************************************************************
2833 */
2834 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
2835 ADDR_HANDLE hLib,
2836 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
2837 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
2838
2839
2840
2841 /**
2842 ****************************************************************************************************
2843 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2844 *
2845 * @brief
2846 * Input structure for Addr2ComputeHtileCoordFromAddr
2847 ****************************************************************************************************
2848 */
2849 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2850 {
2851 UINT_32 size; ///< Size of this structure in bytes
2852
2853 UINT_64 addr; ///< Address
2854
2855 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2856 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags
2857 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2858 UINT_32 bpp; ///< Depth surface bits per pixel
2859 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2860 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2861 UINT_32 numSlices; ///< Depth surface original depth (of mip0)
2862 UINT_32 numMipLevels; ///< Depth surface total mipmap levels
2863 UINT_32 numSamples; ///< Depth surface number of samples
2864 UINT_32 pipeXor; ///< Pipe xor setting
2865 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT;
2866
2867 /**
2868 ****************************************************************************************************
2869 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2870 *
2871 * @brief
2872 * Output structure for Addr2ComputeHtileCoordFromAddr
2873 ****************************************************************************************************
2874 */
2875 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2876 {
2877 UINT_32 size; ///< Size of this structure in bytes
2878
2879 UINT_32 x; ///< X coordinate
2880 UINT_32 y; ///< Y coordinate
2881 UINT_32 slice; ///< Index of slices
2882 UINT_32 mipId; ///< mipmap level id
2883 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
2884
2885 /**
2886 ****************************************************************************************************
2887 * Addr2ComputeHtileCoordFromAddr
2888 *
2889 * @brief
2890 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to
2891 * Htile address
2892 ****************************************************************************************************
2893 */
2894 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
2895 ADDR_HANDLE hLib,
2896 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
2897 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
2898
2899
2900
2901 ////////////////////////////////////////////////////////////////////////////////////////////////////
2902 // C-mask functions for Gfx9
2903 ////////////////////////////////////////////////////////////////////////////////////////////////////
2904
2905 /**
2906 ****************************************************************************************************
2907 * ADDR2_COMPUTE_CMASK_INFO_INPUT
2908 *
2909 * @brief
2910 * Input structure of Addr2ComputeCmaskInfo
2911 ****************************************************************************************************
2912 */
2913 typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT
2914 {
2915 UINT_32 size; ///< Size of this structure in bytes
2916
2917 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
2918 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
2919 AddrResourceType resourceType; ///< Color surface type
2920 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
2921 UINT_32 unalignedWidth; ///< Color surface original width
2922 UINT_32 unalignedHeight; ///< Color surface original height
2923 UINT_32 numSlices; ///< Number of slices of color buffer
2924 } ADDR2_COMPUTE_CMASK_INFO_INPUT;
2925
2926 /**
2927 ****************************************************************************************************
2928 * ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2929 *
2930 * @brief
2931 * Output structure of Addr2ComputeCmaskInfo
2932 ****************************************************************************************************
2933 */
2934 typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2935 {
2936 UINT_32 size; ///< Size of this structure in bytes
2937
2938 UINT_32 pitch; ///< Pitch in pixels of color buffer which
2939 /// this Cmask matches. The size might be larger than
2940 /// original color buffer pitch when called with
2941 /// an unaligned pitch.
2942 UINT_32 height; ///< Height in pixels, as above
2943 UINT_32 baseAlign; ///< Base alignment
2944 UINT_32 sliceSize; ///< Slice size, in bytes.
2945 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer
2946 UINT_32 metaBlkWidth; ///< Meta block width
2947 UINT_32 metaBlkHeight; ///< Meta block height
2948
2949 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
2950 } ADDR2_COMPUTE_CMASK_INFO_OUTPUT;
2951
2952 /**
2953 ****************************************************************************************************
2954 * Addr2ComputeCmaskInfo
2955 *
2956 * @brief
2957 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer
2958 * info
2959 ****************************************************************************************************
2960 */
2961 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
2962 ADDR_HANDLE hLib,
2963 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
2964 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut);
2965
2966
2967
2968 /**
2969 ****************************************************************************************************
2970 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
2971 *
2972 * @brief
2973 * Input structure for Addr2ComputeCmaskAddrFromCoord
2974 *
2975 ****************************************************************************************************
2976 */
2977 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
2978 {
2979 UINT_32 size; ///< Size of this structure in bytes
2980
2981 UINT_32 x; ///< X coordinate
2982 UINT_32 y; ///< Y coordinate
2983 UINT_32 slice; ///< Index of slices
2984
2985 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
2986 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
2987 AddrResourceType resourceType; ///< Color surface type
2988 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
2989
2990 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
2991 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
2992 UINT_32 numSlices; ///< Color surface original slices (of mip0)
2993
2994 UINT_32 numSamples; ///< Color surfae sample number
2995 UINT_32 numFrags; ///< Color surface fragment number
2996
2997 UINT_32 pipeXor; ///< pipe Xor setting
2998 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
2999
3000 /**
3001 ****************************************************************************************************
3002 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
3003 *
3004 * @brief
3005 * Output structure for Addr2ComputeCmaskAddrFromCoord
3006 ****************************************************************************************************
3007 */
3008 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
3009 {
3010 UINT_32 size; ///< Size of this structure in bytes
3011
3012 UINT_64 addr; ///< CMASK address in bytes
3013 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
3014 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
3015
3016 /**
3017 ****************************************************************************************************
3018 * Addr2ComputeCmaskAddrFromCoord
3019 *
3020 * @brief
3021 * Compute Cmask address according to coordinates (of MSAA color buffer)
3022 ****************************************************************************************************
3023 */
3024 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
3025 ADDR_HANDLE hLib,
3026 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
3027 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
3028
3029
3030
3031 /**
3032 ****************************************************************************************************
3033 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
3034 *
3035 * @brief
3036 * Input structure for Addr2ComputeCmaskCoordFromAddr
3037 ****************************************************************************************************
3038 */
3039 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
3040 {
3041 UINT_32 size; ///< Size of this structure in bytes
3042
3043 UINT_64 addr; ///< CMASK address in bytes
3044 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
3045
3046 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
3047 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3048 AddrResourceType resourceType; ///< Color surface type
3049 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3050
3051 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3052 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3053 UINT_32 numSlices; ///< Color surface original slices (of mip0)
3054 UINT_32 numMipLevels; ///< Color surface total mipmap levels.
3055 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT;
3056
3057 /**
3058 ****************************************************************************************************
3059 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3060 *
3061 * @brief
3062 * Output structure for Addr2ComputeCmaskCoordFromAddr
3063 ****************************************************************************************************
3064 */
3065 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3066 {
3067 UINT_32 size; ///< Size of this structure in bytes
3068
3069 UINT_32 x; ///< X coordinate
3070 UINT_32 y; ///< Y coordinate
3071 UINT_32 slice; ///< Index of slices
3072 UINT_32 mipId; ///< mipmap level id
3073 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
3074
3075 /**
3076 ****************************************************************************************************
3077 * Addr2ComputeCmaskCoordFromAddr
3078 *
3079 * @brief
3080 * Compute coordinates within color buffer (1st pixel of a micro tile) according to
3081 * Cmask address
3082 ****************************************************************************************************
3083 */
3084 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
3085 ADDR_HANDLE hLib,
3086 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
3087 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
3088
3089
3090
3091 ////////////////////////////////////////////////////////////////////////////////////////////////////
3092 // F-mask functions for Gfx9
3093 ////////////////////////////////////////////////////////////////////////////////////////////////////
3094
3095 /**
3096 ****************************************************************************************************
3097 * ADDR2_FMASK_FLAGS
3098 *
3099 * @brief
3100 * FMASK flags
3101 ****************************************************************************************************
3102 */
3103 typedef union _ADDR2_FMASK_FLAGS
3104 {
3105 struct
3106 {
3107 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients
3108 /// by H/W clients. S/W should always set it to FALSE.
3109 UINT_32 reserved : 31; ///< Reserved for future use.
3110 };
3111
3112 UINT_32 value;
3113 } ADDR2_FMASK_FLAGS;
3114
3115 /**
3116 ****************************************************************************************************
3117 * ADDR2_COMPUTE_FMASK_INFO_INPUT
3118 *
3119 * @brief
3120 * Input structure for Addr2ComputeFmaskInfo
3121 ****************************************************************************************************
3122 */
3123 typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT
3124 {
3125 UINT_32 size; ///< Size of this structure in bytes
3126
3127 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3128 UINT_32 unalignedWidth; ///< Color surface original width
3129 UINT_32 unalignedHeight; ///< Color surface original height
3130 UINT_32 numSlices; ///< Number of slices/depth
3131 UINT_32 numSamples; ///< Number of samples
3132 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3133 /// number of samples for normal AA; Set it to the
3134 /// number of fragments for EQAA
3135 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3136 } ADDR2_COMPUTE_FMASK_INFO_INPUT;
3137
3138 /**
3139 ****************************************************************************************************
3140 * ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3141 *
3142 * @brief
3143 * Output structure for Addr2ComputeFmaskInfo
3144 ****************************************************************************************************
3145 */
3146 typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3147 {
3148 UINT_32 size; ///< Size of this structure in bytes
3149
3150 UINT_32 pitch; ///< Pitch of fmask in pixels
3151 UINT_32 height; ///< Height of fmask in pixels
3152 UINT_32 baseAlign; ///< Base alignment
3153 UINT_32 numSlices; ///< Slices of fmask
3154 UINT_32 fmaskBytes; ///< Size of fmask in bytes
3155 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes
3156 UINT_32 numSamples; ///< Number of samples
3157 UINT_32 sliceSize; ///< Size of slice in bytes
3158 } ADDR2_COMPUTE_FMASK_INFO_OUTPUT;
3159
3160 /**
3161 ****************************************************************************************************
3162 * Addr2ComputeFmaskInfo
3163 *
3164 * @brief
3165 * Compute Fmask pitch/height/slices/alignments and size in bytes
3166 ****************************************************************************************************
3167 */
3168 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
3169 ADDR_HANDLE hLib,
3170 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
3171 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
3172
3173
3174
3175 /**
3176 ****************************************************************************************************
3177 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3178 *
3179 * @brief
3180 * Input structure for Addr2ComputeFmaskAddrFromCoord
3181 ****************************************************************************************************
3182 */
3183 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3184 {
3185 UINT_32 size; ///< Size of this structure in bytes
3186
3187 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3188 UINT_32 x; ///< X coordinate
3189 UINT_32 y; ///< Y coordinate
3190 UINT_32 slice; ///< Slice index
3191 UINT_32 sample; ///< Sample index (fragment index for EQAA)
3192 UINT_32 plane; ///< Plane number
3193
3194 UINT_32 unalignedWidth; ///< Color surface original width
3195 UINT_32 unalignedHeight; ///< Color surface original height
3196 UINT_32 numSamples; ///< Number of samples
3197 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3198 /// number of samples for normal AA; Set it to the
3199 /// number of fragments for EQAA
3200 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
3201
3202 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3203 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
3204
3205 /**
3206 ****************************************************************************************************
3207 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3208 *
3209 * @brief
3210 * Output structure for Addr2ComputeFmaskAddrFromCoord
3211 ****************************************************************************************************
3212 */
3213 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3214 {
3215 UINT_32 size; ///< Size of this structure in bytes
3216
3217 UINT_64 addr; ///< Fmask address
3218 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.
3219 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
3220
3221 /**
3222 ****************************************************************************************************
3223 * Addr2ComputeFmaskAddrFromCoord
3224 *
3225 * @brief
3226 * Compute Fmask address according to coordinates (x,y,slice,sample,plane)
3227 ****************************************************************************************************
3228 */
3229 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
3230 ADDR_HANDLE hLib,
3231 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
3232 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
3233
3234
3235
3236 /**
3237 ****************************************************************************************************
3238 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3239 *
3240 * @brief
3241 * Input structure for Addr2ComputeFmaskCoordFromAddr
3242 ****************************************************************************************************
3243 */
3244 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3245 {
3246 UINT_32 size; ///< Size of this structure in bytes
3247
3248 UINT_64 addr; ///< Address
3249 UINT_32 bitPosition; ///< Bit position within addr, 0-7.
3250 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3251
3252 UINT_32 unalignedWidth; ///< Color surface original width
3253 UINT_32 unalignedHeight; ///< Color surface original height
3254 UINT_32 numSamples; ///< Number of samples
3255 UINT_32 numFrags; ///< Number of fragments
3256
3257 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
3258
3259 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3260 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT;
3261
3262 /**
3263 ****************************************************************************************************
3264 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3265 *
3266 * @brief
3267 * Output structure for Addr2ComputeFmaskCoordFromAddr
3268 ****************************************************************************************************
3269 */
3270 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3271 {
3272 UINT_32 size; ///< Size of this structure in bytes
3273
3274 UINT_32 x; ///< X coordinate
3275 UINT_32 y; ///< Y coordinate
3276 UINT_32 slice; ///< Slice index
3277 UINT_32 sample; ///< Sample index (fragment index for EQAA)
3278 UINT_32 plane; ///< Plane number
3279 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
3280
3281 /**
3282 ****************************************************************************************************
3283 * Addr2ComputeFmaskCoordFromAddr
3284 *
3285 * @brief
3286 * Compute FMASK coordinate from an given address
3287 ****************************************************************************************************
3288 */
3289 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
3290 ADDR_HANDLE hLib,
3291 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
3292 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
3293
3294
3295
3296 ////////////////////////////////////////////////////////////////////////////////////////////////////
3297 // DCC key functions for Gfx9
3298 ////////////////////////////////////////////////////////////////////////////////////////////////////
3299
3300 /**
3301 ****************************************************************************************************
3302 * _ADDR2_COMPUTE_DCCINFO_INPUT
3303 *
3304 * @brief
3305 * Input structure of Addr2ComputeDccInfo
3306 ****************************************************************************************************
3307 */
3308 typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
3309 {
3310 UINT_32 size; ///< Size of this structure in bytes
3311
3312 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags
3313 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3314 AddrResourceType resourceType; ///< Color surface type
3315 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
3316 UINT_32 bpp; ///< bits per pixel
3317 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3318 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3319 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0)
3320 UINT_32 numFrags; ///< Fragment number of color surface
3321 UINT_32 numMipLevels; ///< Total mipmap levels of color surface
3322 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels
3323 ///< useful in meta linear case
3324 UINT_32 firstMipIdInTail;
3325 } ADDR2_COMPUTE_DCCINFO_INPUT;
3326
3327 /**
3328 ****************************************************************************************************
3329 * ADDR2_COMPUTE_DCCINFO_OUTPUT
3330 *
3331 * @brief
3332 * Output structure of Addr2ComputeDccInfo
3333 ****************************************************************************************************
3334 */
3335 typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
3336 {
3337 UINT_32 size; ///< Size of this structure in bytes
3338
3339 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
3340 UINT_32 dccRamSize; ///< Size of dcc key
3341
3342 UINT_32 pitch; ///< DCC surface mip chain pitch
3343 UINT_32 height; ///< DCC surface mip chain height
3344 UINT_32 depth; ///< DCC surface mip chain depth
3345
3346 UINT_32 compressBlkWidth; ///< DCC compress block width
3347 UINT_32 compressBlkHeight; ///< DCC compress block height
3348 UINT_32 compressBlkDepth; ///< DCC compress block depth
3349
3350 UINT_32 metaBlkWidth; ///< DCC meta block width
3351 UINT_32 metaBlkHeight; ///< DCC meta block height
3352 UINT_32 metaBlkDepth; ///< DCC meta block depth
3353
3354 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
3355
3356 union
3357 {
3358 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
3359 UINT_32 dccRamSliceSize;
3360 };
3361
3362 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information
3363 } ADDR2_COMPUTE_DCCINFO_OUTPUT;
3364
3365 /**
3366 ****************************************************************************************************
3367 * Addr2ComputeDccInfo
3368 *
3369 * @brief
3370 * Compute DCC key size, base alignment
3371 * info
3372 ****************************************************************************************************
3373 */
3374 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
3375 ADDR_HANDLE hLib,
3376 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
3377 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);
3378
3379
3380 /**
3381 ****************************************************************************************************
3382 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3383 *
3384 * @brief
3385 * Input structure for Addr2ComputeDccAddrFromCoord
3386 *
3387 ****************************************************************************************************
3388 */
3389 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3390 {
3391 UINT_32 size; ///< Size of this structure in bytes
3392
3393 UINT_32 x; ///< X coordinate
3394 UINT_32 y; ///< Y coordinate
3395 UINT_32 slice; ///< Index of slices
3396 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
3397 UINT_32 mipId; ///< mipmap level id
3398
3399 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags
3400 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3401 AddrResourceType resourceType; ///< Color surface type
3402 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
3403 UINT_32 bpp; ///< Color surface bits per pixel
3404 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3405 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3406 UINT_32 numSlices; ///< Color surface original slices (of mip0)
3407 UINT_32 numMipLevels; ///< Color surface mipmap levels
3408 UINT_32 numFrags; ///< Color surface fragment number
3409
3410 UINT_32 pipeXor; ///< pipe Xor setting
3411 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;
3412
3413 /**
3414 ****************************************************************************************************
3415 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3416 *
3417 * @brief
3418 * Output structure for Addr2ComputeDccAddrFromCoord
3419 ****************************************************************************************************
3420 */
3421 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3422 {
3423 UINT_32 size; ///< Size of this structure in bytes
3424
3425 UINT_64 addr; ///< DCC address in bytes
3426 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT;
3427
3428 /**
3429 ****************************************************************************************************
3430 * Addr2ComputeDccAddrFromCoord
3431 *
3432 * @brief
3433 * Compute DCC address according to coordinates (of MSAA color buffer)
3434 ****************************************************************************************************
3435 */
3436 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(
3437 ADDR_HANDLE hLib,
3438 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
3439 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
3440
3441 ////////////////////////////////////////////////////////////////////////////////////////////////////
3442 // Misc functions for Gfx9
3443 ////////////////////////////////////////////////////////////////////////////////////////////////////
3444
3445 /**
3446 ****************************************************************************************************
3447 * ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3448 *
3449 * @brief
3450 * Input structure of Addr2ComputePipebankXor
3451 ****************************************************************************************************
3452 */
3453 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3454 {
3455 UINT_32 size; ///< Size of this structure in bytes
3456 UINT_32 surfIndex; ///< Input surface index
3457 ADDR2_SURFACE_FLAGS flags; ///< Surface flag
3458 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3459 AddrResourceType resourceType; ///< Surface resource type
3460 AddrFormat format; ///< Surface format
3461 UINT_32 numSamples; ///< Number of samples
3462 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3463 /// number of samples for normal AA; Set it to the
3464 /// number of fragments for EQAA
3465 } ADDR2_COMPUTE_PIPEBANKXOR_INPUT;
3466
3467 /**
3468 ****************************************************************************************************
3469 * ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3470 *
3471 * @brief
3472 * Output structure of Addr2ComputePipebankXor
3473 ****************************************************************************************************
3474 */
3475 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3476 {
3477 UINT_32 size; ///< Size of this structure in bytes
3478 UINT_32 pipeBankXor; ///< Pipe bank xor
3479 } ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT;
3480
3481 /**
3482 ****************************************************************************************************
3483 * Addr2ComputePipeBankXor
3484 *
3485 * @brief
3486 * Calculate a valid bank pipe xor value for client to use.
3487 ****************************************************************************************************
3488 */
3489 ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor(
3490 ADDR_HANDLE hLib,
3491 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
3492 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
3493
3494 /**
3495 ****************************************************************************************************
3496 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3497 *
3498 * @brief
3499 * Input structure of Addr2ComputeSlicePipeBankXor
3500 ****************************************************************************************************
3501 */
3502 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3503 {
3504 UINT_32 size; ///< Size of this structure in bytes
3505 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3506 AddrResourceType resourceType; ///< Surface resource type
3507 UINT_32 basePipeBankXor; ///< Base pipe bank xor
3508 UINT_32 slice; ///< Slice id
3509 UINT_32 numSamples; ///< Number of samples
3510 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT;
3511
3512 /**
3513 ****************************************************************************************************
3514 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3515 *
3516 * @brief
3517 * Output structure of Addr2ComputeSlicePipeBankXor
3518 ****************************************************************************************************
3519 */
3520 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3521 {
3522 UINT_32 size; ///< Size of this structure in bytes
3523 UINT_32 pipeBankXor; ///< Pipe bank xor
3524 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT;
3525
3526 /**
3527 ****************************************************************************************************
3528 * Addr2ComputeSlicePipeBankXor
3529 *
3530 * @brief
3531 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id.
3532 ****************************************************************************************************
3533 */
3534 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(
3535 ADDR_HANDLE hLib,
3536 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
3537 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
3538
3539 /**
3540 ****************************************************************************************************
3541 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3542 *
3543 * @brief
3544 * Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3545 ****************************************************************************************************
3546 */
3547 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3548 {
3549 UINT_32 size; ///< Size of this structure in bytes
3550 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3551 AddrResourceType resourceType; ///< Surface resource type
3552 UINT_32 pipeBankXor; ///< Per resource xor
3553 UINT_32 slice; ///< Slice id
3554 UINT_64 sliceSize; ///< Slice size of a mip chain
3555 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO
3556 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO
3557 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT;
3558
3559 /**
3560 ****************************************************************************************************
3561 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3562 *
3563 * @brief
3564 * Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3565 ****************************************************************************************************
3566 */
3567 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3568 {
3569 UINT_32 size; ///< Size of this structure in bytes
3570 UINT_64 offset; ///< offset
3571 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT;
3572
3573 /**
3574 ****************************************************************************************************
3575 * Addr2ComputeSubResourceOffsetForSwizzlePattern
3576 *
3577 * @brief
3578 * Calculate sub resource offset to support swizzle pattern.
3579 ****************************************************************************************************
3580 */
3581 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
3582 ADDR_HANDLE hLib,
3583 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
3584 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
3585
3586 /**
3587 ****************************************************************************************************
3588 * ADDR2_BLOCK_SET
3589 *
3590 * @brief
3591 * Bit field that defines block type
3592 ****************************************************************************************************
3593 */
3594 typedef union _ADDR2_BLOCK_SET
3595 {
3596 struct
3597 {
3598 UINT_32 micro : 1; // 256B block for 2D resource
3599 UINT_32 macro4KB : 1; // 4KB for 2D/3D resource
3600 UINT_32 macro64KB : 1; // 64KB for 2D/3D resource
3601 UINT_32 var : 1; // VAR block
3602 UINT_32 linear : 1; // Linear block
3603 UINT_32 reserved : 27;
3604 };
3605
3606 UINT_32 value;
3607 } ADDR2_BLOCK_SET;
3608
3609 /**
3610 ****************************************************************************************************
3611 * ADDR2_SWTYPE_SET
3612 *
3613 * @brief
3614 * Bit field that defines swizzle type
3615 ****************************************************************************************************
3616 */
3617 typedef union _ADDR2_SWTYPE_SET
3618 {
3619 struct
3620 {
3621 UINT_32 sw_Z : 1; // SW_*_Z_*
3622 UINT_32 sw_S : 1; // SW_*_S_*
3623 UINT_32 sw_D : 1; // SW_*_D_*
3624 UINT_32 sw_R : 1; // SW_*_R_*
3625 UINT_32 reserved : 28;
3626 };
3627
3628 UINT_32 value;
3629 } ADDR2_SWTYPE_SET;
3630
3631 /**
3632 ****************************************************************************************************
3633 * ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3634 *
3635 * @brief
3636 * Input structure of Addr2GetPreferredSurfaceSetting
3637 ****************************************************************************************************
3638 */
3639 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3640 {
3641 UINT_32 size; ///< Size of this structure in bytes
3642
3643 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
3644 AddrResourceType resourceType; ///< Surface type
3645 AddrFormat format; ///< Surface format
3646 AddrResrouceLocation resourceLoction; ///< Surface heap choice
3647 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting
3648 ///< such as linear for DXTn, tiled for YUV
3649 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted
3650 BOOL_32 noXor; ///< Do not use xor mode for this resource
3651 UINT_32 bpp; ///< bits per pixel
3652 UINT_32 width; ///< Width (of mip0), in pixels
3653 UINT_32 height; ///< Height (of mip0), in pixels
3654 UINT_32 numSlices; ///< Number surface slice/depth (of mip0),
3655 UINT_32 numMipLevels; ///< Total mipmap levels.
3656 UINT_32 numSamples; ///< Number of samples
3657 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3658 /// number of samples for normal AA; Set it to the
3659 /// number of fragments for EQAA
3660 UINT_32 maxAlign; ///< maximum base/size alignment requested by client
3661 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will
3662 /// be padded to multiple of this value (in bytes)
3663 } ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;
3664
3665 /**
3666 ****************************************************************************************************
3667 * ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3668 *
3669 * @brief
3670 * Output structure of Addr2GetPreferredSurfaceSetting
3671 ****************************************************************************************************
3672 */
3673 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3674 {
3675 UINT_32 size; ///< Size of this structure in bytes
3676
3677 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used
3678 AddrResourceType resourceType; ///< Suggested resource type to program HW
3679 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination
3680 BOOL_32 canXor; ///< If client can use xor on a valid macro block
3681 /// type
3682 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination
3683 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
3684 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
3685
3686 /**
3687 ****************************************************************************************************
3688 * Addr2GetPreferredSurfaceSetting
3689 *
3690 * @brief
3691 * Suggest a preferred setting for client driver to program HW register
3692 ****************************************************************************************************
3693 */
3694 ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(
3695 ADDR_HANDLE hLib,
3696 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
3697 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut);
3698
3699 /**
3700 ****************************************************************************************************
3701 * Addr2IsValidDisplaySwizzleMode
3702 *
3703 * @brief
3704 * Return whether the swizzle mode is supported by DCE / DCN.
3705 ****************************************************************************************************
3706 */
3707 ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
3708 ADDR_HANDLE hLib,
3709 AddrSwizzleMode swizzleMode,
3710 UINT_32 bpp,
3711 bool *result);
3712
3713 #if defined(__cplusplus)
3714 }
3715 #endif
3716
3717 #endif // __ADDR_INTERFACE_H__