736604e7cc5dce34ca90ebb91679c10ddf203413
[mesa.git] / src / amd / addrlib / core / addrlib.h
1 /*
2 * Copyright © 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 /**
28 ****************************************************************************************************
29 * @file addrlib.h
30 * @brief Contains the Addr::Lib base class definition.
31 ****************************************************************************************************
32 */
33
34 #ifndef __ADDR_LIB_H__
35 #define __ADDR_LIB_H__
36
37 #include "addrinterface.h"
38 #include "addrobject.h"
39 #include "addrelemlib.h"
40
41 #if BRAHMA_BUILD
42 #include "amdgpu_id.h"
43 #else
44 #include "atiid.h"
45 #endif
46
47 #ifndef CIASICIDGFXENGINE_R600
48 #define CIASICIDGFXENGINE_R600 0x00000006
49 #endif
50
51 #ifndef CIASICIDGFXENGINE_R800
52 #define CIASICIDGFXENGINE_R800 0x00000008
53 #endif
54
55 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
56 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
57 #endif
58
59 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
60 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
61 #endif
62
63 namespace Addr
64 {
65
66 /**
67 ****************************************************************************************************
68 * @brief Neutral enums that define pipeinterleave
69 ****************************************************************************************************
70 */
71 enum PipeInterleave
72 {
73 ADDR_PIPEINTERLEAVE_256B = 256,
74 ADDR_PIPEINTERLEAVE_512B = 512,
75 ADDR_PIPEINTERLEAVE_1KB = 1024,
76 ADDR_PIPEINTERLEAVE_2KB = 2048,
77 };
78
79 /**
80 ****************************************************************************************************
81 * @brief Neutral enums that define DRAM row size
82 ****************************************************************************************************
83 */
84 enum RowSize
85 {
86 ADDR_ROWSIZE_1KB = 1024,
87 ADDR_ROWSIZE_2KB = 2048,
88 ADDR_ROWSIZE_4KB = 4096,
89 ADDR_ROWSIZE_8KB = 8192,
90 };
91
92 /**
93 ****************************************************************************************************
94 * @brief Neutral enums that define bank interleave
95 ****************************************************************************************************
96 */
97 enum BankInterleave
98 {
99 ADDR_BANKINTERLEAVE_1 = 1,
100 ADDR_BANKINTERLEAVE_2 = 2,
101 ADDR_BANKINTERLEAVE_4 = 4,
102 ADDR_BANKINTERLEAVE_8 = 8,
103 };
104
105 /**
106 ****************************************************************************************************
107 * @brief Neutral enums that define shader engine tile size
108 ****************************************************************************************************
109 */
110 enum ShaderEngineTileSize
111 {
112 ADDR_SE_TILESIZE_16 = 16,
113 ADDR_SE_TILESIZE_32 = 32,
114 };
115
116 /**
117 ****************************************************************************************************
118 * @brief Neutral enums that define bank swap size
119 ****************************************************************************************************
120 */
121 enum BankSwapSize
122 {
123 ADDR_BANKSWAP_128B = 128,
124 ADDR_BANKSWAP_256B = 256,
125 ADDR_BANKSWAP_512B = 512,
126 ADDR_BANKSWAP_1KB = 1024,
127 };
128
129 /**
130 ****************************************************************************************************
131 * @brief This class contains asic independent address lib functionalities
132 ****************************************************************************************************
133 */
134 class Lib : public Object
135 {
136 public:
137 virtual ~Lib();
138
139 static ADDR_E_RETURNCODE Create(
140 const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut);
141
142 /// Pair of Create
143 VOID Destroy()
144 {
145 delete this;
146 }
147
148 static Lib* GetLib(ADDR_HANDLE hLib);
149
150 /// Returns AddrLib version (from compiled binary instead include file)
151 UINT_32 GetVersion()
152 {
153 return m_version;
154 }
155
156 /// Returns asic chip family name defined by AddrLib
157 ChipFamily GetChipFamily()
158 {
159 return m_chipFamily;
160 }
161
162 ADDR_E_RETURNCODE Flt32ToDepthPixel(
163 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
164 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const;
165
166 ADDR_E_RETURNCODE Flt32ToColorPixel(
167 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
168 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const;
169
170 BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const;
171
172 ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
173
174 protected:
175 Lib(); // Constructor is protected
176 Lib(const Client* pClient);
177
178 /// Pure virtual function to get max alignments
179 virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const = 0;
180
181 //
182 // Initialization
183 //
184 /// Pure Virtual function for Hwl computing internal global parameters from h/w registers
185 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0;
186
187 /// Pure Virtual function for Hwl converting chip family
188 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
189
190 /// Get equation table pointer and number of equations
191 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
192 {
193 *ppEquationTable = NULL;
194
195 return 0;
196 }
197
198 //
199 // Misc helper
200 //
201 static UINT_32 Bits2Number(UINT_32 bitNum, ...);
202
203 static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags)
204 {
205 return (numFrags != 0) ? numFrags : Max(1u, numSamples);
206 }
207
208 /// Returns pointer of ElemLib
209 ElemLib* GetElemLib() const
210 {
211 return m_pElemLib;
212 }
213
214 /// Returns fillSizeFields flag
215 UINT_32 GetFillSizeFieldsFlags() const
216 {
217 return m_configFlags.fillSizeFields;
218 }
219
220 private:
221 // Disallow the copy constructor
222 Lib(const Lib& a);
223
224 // Disallow the assignment operator
225 Lib& operator=(const Lib& a);
226
227 VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
228
229 VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
230
231 protected:
232 LibClass m_class; ///< Store class type (HWL type)
233
234 ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h
235
236 UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
237
238 UINT_32 m_version; ///< Current version
239
240 //
241 // Global parameters
242 //
243 ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by
244 /// AddrLib instead of Client except forceLinearAligned
245
246 UINT_32 m_pipes; ///< Number of pipes
247 UINT_32 m_banks; ///< Number of banks
248 /// For r800 this is MC_ARB_RAMCFG.NOOFBANK
249 /// Keep it here to do default parameter calculation
250
251 UINT_32 m_pipeInterleaveBytes;
252 ///< Specifies the size of contiguous address space
253 /// within each tiling pipe when making linear
254 /// accesses. (Formerly Group Size)
255
256 UINT_32 m_rowSize; ///< DRAM row size, in bytes
257
258 UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
259 UINT_32 m_maxSamples; ///< Max numSamples
260 private:
261 ElemLib* m_pElemLib; ///< Element Lib pointer
262 };
263
264 Lib* SiHwlInit (const Client* pClient);
265 Lib* CiHwlInit (const Client* pClient);
266 Lib* Gfx9HwlInit (const Client* pClient);
267
268 } // Addr
269
270 #endif