2 * Copyright © 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
28 ************************************************************************************************************************
30 * @brief Contains the Addr::V2::Lib class definition.
31 ************************************************************************************************************************
34 #ifndef __ADDR2_LIB2_H__
35 #define __ADDR2_LIB2_H__
45 ************************************************************************************************************************
46 * @brief Flags for SwizzleModeTable
47 ************************************************************************************************************************
49 struct SwizzleModeFlags
52 UINT_32 isLinear
: 1; // Linear
55 UINT_32 is256b
: 1; // Block size is 256B
56 UINT_32 is4kb
: 1; // Block size is 4KB
57 UINT_32 is64kb
: 1; // Block size is 64KB
58 UINT_32 isVar
: 1; // Block size is variable
60 UINT_32 isZ
: 1; // Z order swizzle mode
61 UINT_32 isStd
: 1; // Standard swizzle mode
62 UINT_32 isDisp
: 1; // Display swizzle mode
63 UINT_32 isRot
: 1; // Rotate swizzle mode
66 UINT_32 isXor
: 1; // XOR after swizzle if set
68 UINT_32 isT
: 1; // T mode
70 UINT_32 isRtOpt
: 1; // mode opt for render target
87 ************************************************************************************************************************
88 * @brief This class contains asic independent address lib functionalities
89 ************************************************************************************************************************
91 class Lib
: public Addr::Lib
104 ADDR_E_RETURNCODE
ComputeSurfaceInfo(
105 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
,
106 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
) const;
108 ADDR_E_RETURNCODE
ComputeSurfaceAddrFromCoord(
109 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
* pIn
,
110 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
* pOut
) const;
112 ADDR_E_RETURNCODE
ComputeSurfaceCoordFromAddr(
113 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
* pIn
,
114 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
* pOut
) const;
117 ADDR_E_RETURNCODE
ComputeHtileInfo(
118 const ADDR2_COMPUTE_HTILE_INFO_INPUT
* pIn
,
119 ADDR2_COMPUTE_HTILE_INFO_OUTPUT
* pOut
) const;
121 ADDR_E_RETURNCODE
ComputeHtileAddrFromCoord(
122 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
* pIn
,
123 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
* pOut
);
125 ADDR_E_RETURNCODE
ComputeHtileCoordFromAddr(
126 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
* pIn
,
127 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
* pOut
);
130 ADDR_E_RETURNCODE
ComputeCmaskInfo(
131 const ADDR2_COMPUTE_CMASK_INFO_INPUT
* pIn
,
132 ADDR2_COMPUTE_CMASK_INFO_OUTPUT
* pOut
) const;
134 ADDR_E_RETURNCODE
ComputeCmaskAddrFromCoord(
135 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
* pIn
,
136 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
* pOut
);
138 ADDR_E_RETURNCODE
ComputeCmaskCoordFromAddr(
139 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
* pIn
,
140 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
* pOut
) const;
143 ADDR_E_RETURNCODE
ComputeFmaskInfo(
144 const ADDR2_COMPUTE_FMASK_INFO_INPUT
* pIn
,
145 ADDR2_COMPUTE_FMASK_INFO_OUTPUT
* pOut
);
147 ADDR_E_RETURNCODE
ComputeFmaskAddrFromCoord(
148 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
* pIn
,
149 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
* pOut
) const;
151 ADDR_E_RETURNCODE
ComputeFmaskCoordFromAddr(
152 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
* pIn
,
153 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
* pOut
) const;
156 ADDR_E_RETURNCODE
ComputeDccInfo(
157 const ADDR2_COMPUTE_DCCINFO_INPUT
* pIn
,
158 ADDR2_COMPUTE_DCCINFO_OUTPUT
* pOut
) const;
160 ADDR_E_RETURNCODE
ComputeDccAddrFromCoord(
161 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
* pIn
,
162 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
* pOut
);
165 ADDR_E_RETURNCODE
ComputePipeBankXor(
166 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT
* pIn
,
167 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
* pOut
);
169 ADDR_E_RETURNCODE
ComputeSlicePipeBankXor(
170 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
* pIn
,
171 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
* pOut
);
173 ADDR_E_RETURNCODE
ComputeSubResourceOffsetForSwizzlePattern(
174 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
* pIn
,
175 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
* pOut
);
177 ADDR_E_RETURNCODE
Addr2GetPreferredSurfaceSetting(
178 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
* pIn
,
179 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
* pOut
) const;
181 virtual BOOL_32
IsValidDisplaySwizzleMode(
182 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
) const
184 ADDR_NOT_IMPLEMENTED();
185 return ADDR_NOTIMPLEMENTED
;
189 Lib(); // Constructor is protected
190 Lib(const Client
* pClient
);
192 static const UINT_32 MaxNumOfBpp
= 5;
194 static const Dim2d Block256_2d
[MaxNumOfBpp
];
195 static const Dim3d Block1K_3d
[MaxNumOfBpp
];
197 static const UINT_32 PrtAlignment
= 64 * 1024;
198 static const UINT_32 MaxMacroBits
= 20;
200 static const UINT_32 MaxMipLevels
= 16;
202 // Checking block size
203 BOOL_32
IsBlock256b(AddrSwizzleMode swizzleMode
) const
205 return m_swizzleModeTable
[swizzleMode
].is256b
;
208 BOOL_32
IsBlock4kb(AddrSwizzleMode swizzleMode
) const
210 return m_swizzleModeTable
[swizzleMode
].is4kb
;
213 BOOL_32
IsBlock64kb(AddrSwizzleMode swizzleMode
) const
215 return m_swizzleModeTable
[swizzleMode
].is64kb
;
218 BOOL_32
IsBlockVariable(AddrSwizzleMode swizzleMode
) const
220 return m_swizzleModeTable
[swizzleMode
].isVar
;
223 // Checking swizzle mode
224 BOOL_32
IsLinear(AddrSwizzleMode swizzleMode
) const
226 return m_swizzleModeTable
[swizzleMode
].isLinear
;
229 BOOL_32
IsRtOptSwizzle(AddrSwizzleMode swizzleMode
) const
231 return m_swizzleModeTable
[swizzleMode
].isRtOpt
;
234 BOOL_32
IsZOrderSwizzle(AddrSwizzleMode swizzleMode
) const
236 return m_swizzleModeTable
[swizzleMode
].isZ
;
239 BOOL_32
IsStandardSwizzle(AddrResourceType resourceType
, AddrSwizzleMode swizzleMode
) const
241 return HwlIsStandardSwizzle(resourceType
, swizzleMode
);
244 BOOL_32
IsDisplaySwizzle(AddrResourceType resourceType
, AddrSwizzleMode swizzleMode
) const
246 return HwlIsDisplaySwizzle(resourceType
, swizzleMode
);
249 BOOL_32
IsRotateSwizzle(AddrSwizzleMode swizzleMode
) const
251 return m_swizzleModeTable
[swizzleMode
].isRot
;
254 BOOL_32
IsXor(AddrSwizzleMode swizzleMode
) const
256 return m_swizzleModeTable
[swizzleMode
].isXor
;
259 BOOL_32
IsPrt(AddrSwizzleMode swizzleMode
) const
261 return m_swizzleModeTable
[swizzleMode
].isT
;
264 BOOL_32
IsNonPrtXor(AddrSwizzleMode swizzleMode
) const
266 return (IsXor(swizzleMode
) && (IsPrt(swizzleMode
) == FALSE
));
269 // Checking resource type
270 static BOOL_32
IsTex1d(AddrResourceType resourceType
)
272 return (resourceType
== ADDR_RSRC_TEX_1D
);
275 static BOOL_32
IsTex2d(AddrResourceType resourceType
)
277 return (resourceType
== ADDR_RSRC_TEX_2D
);
280 static BOOL_32
IsTex3d(AddrResourceType resourceType
)
282 return (resourceType
== ADDR_RSRC_TEX_3D
);
285 BOOL_32
IsThick(AddrResourceType resourceType
, AddrSwizzleMode swizzleMode
) const
287 return HwlIsThick(resourceType
, swizzleMode
);
290 BOOL_32
IsThin(AddrResourceType resourceType
, AddrSwizzleMode swizzleMode
) const
292 return HwlIsThin(resourceType
, swizzleMode
);
295 UINT_32
GetBlockSizeLog2(AddrSwizzleMode swizzleMode
) const
297 UINT_32 blockSizeLog2
= 0;
299 if (IsBlock256b(swizzleMode
) || IsLinear(swizzleMode
))
303 else if (IsBlock4kb(swizzleMode
))
307 else if (IsBlock64kb(swizzleMode
))
311 else if (IsBlockVariable(swizzleMode
))
313 blockSizeLog2
= m_blockVarSizeLog2
;
317 ADDR_ASSERT_ALWAYS();
320 return blockSizeLog2
;
323 UINT_32
GetBlockSize(AddrSwizzleMode swizzleMode
) const
325 return (1 << GetBlockSizeLog2(swizzleMode
));
328 static UINT_32
GetFmaskBpp(UINT_32 sample
, UINT_32 frag
)
330 sample
= (sample
== 0) ? 1 : sample
;
331 frag
= (frag
== 0) ? sample
: frag
;
333 UINT_32 fmaskBpp
= QLog2(frag
);
345 fmaskBpp
= Max(8u, fmaskBpp
* sample
);
350 virtual BOOL_32
HwlIsStandardSwizzle(
351 AddrResourceType resourceType
,
352 AddrSwizzleMode swizzleMode
) const
354 ADDR_NOT_IMPLEMENTED();
358 virtual BOOL_32
HwlIsDisplaySwizzle(
359 AddrResourceType resourceType
,
360 AddrSwizzleMode swizzleMode
) const
362 ADDR_NOT_IMPLEMENTED();
366 virtual BOOL_32
HwlIsThin(
367 AddrResourceType resourceType
,
368 AddrSwizzleMode swizzleMode
) const
370 ADDR_NOT_IMPLEMENTED();
374 virtual BOOL_32
HwlIsThick(
375 AddrResourceType resourceType
,
376 AddrSwizzleMode swizzleMode
) const
378 ADDR_NOT_IMPLEMENTED();
382 virtual ADDR_E_RETURNCODE
HwlComputeHtileInfo(
383 const ADDR2_COMPUTE_HTILE_INFO_INPUT
* pIn
,
384 ADDR2_COMPUTE_HTILE_INFO_OUTPUT
* pOut
) const
386 ADDR_NOT_IMPLEMENTED();
387 return ADDR_NOTSUPPORTED
;
390 virtual ADDR_E_RETURNCODE
HwlComputeCmaskInfo(
391 const ADDR2_COMPUTE_CMASK_INFO_INPUT
* pIn
,
392 ADDR2_COMPUTE_CMASK_INFO_OUTPUT
* pOut
) const
394 ADDR_NOT_IMPLEMENTED();
395 return ADDR_NOTSUPPORTED
;
398 virtual ADDR_E_RETURNCODE
HwlComputeDccInfo(
399 const ADDR2_COMPUTE_DCCINFO_INPUT
* pIn
,
400 ADDR2_COMPUTE_DCCINFO_OUTPUT
* pOut
) const
402 ADDR_NOT_IMPLEMENTED();
403 return ADDR_NOTSUPPORTED
;
406 virtual ADDR_E_RETURNCODE
HwlComputeDccAddrFromCoord(
407 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
* pIn
,
408 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
* pOut
)
410 ADDR_NOT_IMPLEMENTED();
411 return ADDR_NOTSUPPORTED
;
414 virtual ADDR_E_RETURNCODE
HwlComputeCmaskAddrFromCoord(
415 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
* pIn
,
416 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
* pOut
)
418 ADDR_NOT_IMPLEMENTED();
419 return ADDR_NOTSUPPORTED
;
422 virtual ADDR_E_RETURNCODE
HwlComputeHtileAddrFromCoord(
423 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
* pIn
,
424 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
* pOut
)
426 ADDR_NOT_IMPLEMENTED();
427 return ADDR_NOTSUPPORTED
;
430 virtual ADDR_E_RETURNCODE
HwlComputeHtileCoordFromAddr(
431 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
* pIn
,
432 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
* pOut
)
434 ADDR_NOT_IMPLEMENTED();
435 return ADDR_NOTSUPPORTED
;
438 virtual ADDR_E_RETURNCODE
HwlComputeBlock256Equation(
439 AddrResourceType rsrcType
,
440 AddrSwizzleMode swMode
,
441 UINT_32 elementBytesLog2
,
442 ADDR_EQUATION
* pEquation
) const
444 ADDR_NOT_IMPLEMENTED();
445 return ADDR_NOTSUPPORTED
;
448 virtual ADDR_E_RETURNCODE
HwlComputeThinEquation(
449 AddrResourceType rsrcType
,
450 AddrSwizzleMode swMode
,
451 UINT_32 elementBytesLog2
,
452 ADDR_EQUATION
* pEquation
) const
454 ADDR_NOT_IMPLEMENTED();
455 return ADDR_NOTSUPPORTED
;
458 virtual ADDR_E_RETURNCODE
HwlComputeThickEquation(
459 AddrResourceType rsrcType
,
460 AddrSwizzleMode swMode
,
461 UINT_32 elementBytesLog2
,
462 ADDR_EQUATION
* pEquation
) const
464 ADDR_NOT_IMPLEMENTED();
465 return ADDR_NOTSUPPORTED
;
468 virtual UINT_32
HwlGetEquationIndex(
469 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
,
470 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
) const
472 ADDR_NOT_IMPLEMENTED();
473 return ADDR_INVALID_EQUATION_INDEX
;
476 UINT_32
GetEquationIndex(
477 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
,
478 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
) const
480 return HwlGetEquationIndex(pIn
, pOut
);
483 virtual ADDR_E_RETURNCODE
HwlComputePipeBankXor(
484 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT
* pIn
,
485 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
* pOut
) const
487 ADDR_NOT_IMPLEMENTED();
488 return ADDR_NOTSUPPORTED
;
491 virtual ADDR_E_RETURNCODE
HwlComputeSlicePipeBankXor(
492 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
* pIn
,
493 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
* pOut
) const
495 ADDR_NOT_IMPLEMENTED();
496 return ADDR_NOTSUPPORTED
;
500 virtual ADDR_E_RETURNCODE
HwlComputeSubResourceOffsetForSwizzlePattern(
501 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
* pIn
,
502 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
* pOut
) const
504 ADDR_NOT_IMPLEMENTED();
505 return ADDR_NOTSUPPORTED
;
508 virtual ADDR_E_RETURNCODE
HwlGetPreferredSurfaceSetting(
509 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
* pIn
,
510 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
* pOut
) const
512 ADDR_NOT_IMPLEMENTED();
513 return ADDR_NOTSUPPORTED
;
516 virtual ADDR_E_RETURNCODE
HwlComputeSurfaceInfoSanityCheck(
517 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
) const
519 ADDR_NOT_IMPLEMENTED();
520 return ADDR_NOTSUPPORTED
;
523 virtual ADDR_E_RETURNCODE
HwlComputeSurfaceInfoTiled(
524 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
,
525 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
) const
527 ADDR_NOT_IMPLEMENTED();
528 return ADDR_NOTIMPLEMENTED
;
531 virtual ADDR_E_RETURNCODE
HwlComputeSurfaceInfoLinear(
532 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
,
533 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
) const
535 ADDR_NOT_IMPLEMENTED();
536 return ADDR_NOTIMPLEMENTED
;
539 virtual ADDR_E_RETURNCODE
HwlComputeSurfaceAddrFromCoordTiled(
540 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
* pIn
,
541 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
* pOut
) const
543 ADDR_NOT_IMPLEMENTED();
544 return ADDR_NOTIMPLEMENTED
;
547 ADDR_E_RETURNCODE
ComputeBlock256Equation(
548 AddrResourceType rsrcType
,
549 AddrSwizzleMode swMode
,
550 UINT_32 elementBytesLog2
,
551 ADDR_EQUATION
* pEquation
) const;
553 ADDR_E_RETURNCODE
ComputeThinEquation(
554 AddrResourceType rsrcType
,
555 AddrSwizzleMode swMode
,
556 UINT_32 elementBytesLog2
,
557 ADDR_EQUATION
* pEquation
) const;
559 ADDR_E_RETURNCODE
ComputeThickEquation(
560 AddrResourceType rsrcType
,
561 AddrSwizzleMode swMode
,
562 UINT_32 elementBytesLog2
,
563 ADDR_EQUATION
* pEquation
) const;
565 ADDR_E_RETURNCODE
ComputeSurfaceInfoSanityCheck(
566 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
) const;
568 ADDR_E_RETURNCODE
ComputeSurfaceInfoLinear(
569 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
,
570 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
) const;
572 ADDR_E_RETURNCODE
ComputeSurfaceInfoTiled(
573 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
,
574 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
) const;
576 ADDR_E_RETURNCODE
ComputeSurfaceAddrFromCoordLinear(
577 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
* pIn
,
578 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
* pOut
) const;
580 ADDR_E_RETURNCODE
ComputeSurfaceAddrFromCoordTiled(
581 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
* pIn
,
582 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
* pOut
) const;
584 ADDR_E_RETURNCODE
ComputeSurfaceCoordFromAddrLinear(
585 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
* pIn
,
586 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
* pOut
) const;
588 ADDR_E_RETURNCODE
ComputeSurfaceCoordFromAddrTiled(
589 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
* pIn
,
590 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
* pOut
) const;
592 UINT_32
ComputeSurface2DMicroBlockOffset(
593 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
* pIn
) const;
595 UINT_32
ComputeSurface3DMicroBlockOffset(
596 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
* pIn
) const;
599 ADDR_E_RETURNCODE
ComputeBlockDimensionForSurf(
605 AddrResourceType resourceType
,
606 AddrSwizzleMode swizzleMode
) const;
608 ADDR_E_RETURNCODE
ComputeBlockDimension(
613 AddrResourceType resourceType
,
614 AddrSwizzleMode swizzleMode
) const;
616 static UINT_64
ComputePadSize(
617 const Dim3d
* pBlkDim
,
623 pPadDim
->w
= PowTwoAlign(width
,pBlkDim
->w
);
624 pPadDim
->h
= PowTwoAlign(height
,pBlkDim
->h
);
625 pPadDim
->d
= PowTwoAlign(numSlices
, pBlkDim
->d
);
626 return static_cast<UINT_64
>(pPadDim
->w
) * pPadDim
->h
* pPadDim
->d
;
629 static ADDR_E_RETURNCODE
ExtractPipeBankXor(
636 static BOOL_32
Valid3DMipSliceIdConstraint(
641 return (Max((numSlices
>> mipId
), 1u) > slice
);
645 AddrResourceType resourceType
,
646 AddrSwizzleMode swizzleMode
,
649 UINT_32 blockDepth
) const;
652 AddrResourceType resourceType
,
653 AddrSwizzleMode swizzleMode
,
659 BOOL_32 inTail
= ((width
<= mipTailDim
.w
) &&
660 (height
<= mipTailDim
.h
) &&
661 (IsThin(resourceType
, swizzleMode
) || (depth
<= mipTailDim
.d
)));
666 static BOOL_32
IsLocalHeap(AddrResrouceLocation resourceType
)
668 return ((resourceType
== ADDR_RSRC_LOC_LOCAL
) ||
669 (resourceType
== ADDR_RSRC_LOC_INVIS
));
672 static BOOL_32
IsInvisibleHeap(AddrResrouceLocation resourceType
)
674 return (resourceType
== ADDR_RSRC_LOC_INVIS
);
677 static BOOL_32
IsNonlocalHeap(AddrResrouceLocation resourceType
)
679 return ((resourceType
== ADDR_RSRC_LOC_USWC
) ||
680 (resourceType
== ADDR_RSRC_LOC_CACHED
));
683 UINT_32
GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned
, AddrSwizzleMode swizzleMode
) const
685 UINT_32 numPipeLog2
= pipeAligned
? Min(m_pipesLog2
+ m_seLog2
, 5u) : 0;
687 if (IsXor(swizzleMode
))
689 UINT_32 maxPipeLog2
= GetBlockSizeLog2(swizzleMode
) - m_pipeInterleaveLog2
;
691 numPipeLog2
= Min(numPipeLog2
, maxPipeLog2
);
697 UINT_32
GetPipeNumForMetaAddressing(BOOL_32 pipeAligned
, AddrSwizzleMode swizzleMode
) const
699 return (1 << GetPipeLog2ForMetaAddressing(pipeAligned
, swizzleMode
));
702 VOID
VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
) const
705 if (pIn
->numMipLevels
> 1)
707 UINT_32 actualMipLevels
= 1;
708 switch (pIn
->resourceType
)
710 case ADDR_RSRC_TEX_3D
:
711 // Fall through to share 2D case
712 actualMipLevels
= Max(actualMipLevels
, Log2NonPow2(pIn
->numSlices
) + 1);
713 case ADDR_RSRC_TEX_2D
:
714 // Fall through to share 1D case
715 actualMipLevels
= Max(actualMipLevels
, Log2NonPow2(pIn
->height
) + 1);
716 case ADDR_RSRC_TEX_1D
:
718 actualMipLevels
= Max(actualMipLevels
, Log2NonPow2(pIn
->width
) + 1);
721 ADDR_ASSERT_ALWAYS();
724 // Client pass wrong number of MipLevels to addrlib and result will be bad.
725 // Not sure if we should fail this calling instead of putting an assertion here.
726 ADDR_ASSERT(actualMipLevels
>= pIn
->numMipLevels
);
731 ADDR_E_RETURNCODE
ApplyCustomerPipeBankXor(
732 AddrSwizzleMode swizzleMode
,
736 UINT_32
* pBlockOffset
) const
738 ADDR_E_RETURNCODE returnCode
= ADDR_OK
;
740 if (IsXor(swizzleMode
))
742 // Apply driver set bankPipeXor
745 returnCode
= ExtractPipeBankXor(pipeBankXor
, bankBits
, pipeBits
, &bankX
, &pipeX
);
746 *pBlockOffset
^= (pipeX
<< m_pipeInterleaveLog2
);
747 *pBlockOffset
^= (bankX
<< (m_pipeInterleaveLog2
+ pipeBits
));
753 UINT_32
GetPipeXorBits(UINT_32 macroBlockBits
) const;
754 UINT_32
GetBankXorBits(UINT_32 macroBlockBits
) const;
756 ADDR_E_RETURNCODE
ApplyCustomizedPitchHeight(
757 const ADDR2_COMPUTE_SURFACE_INFO_INPUT
* pIn
,
758 UINT_32 elementBytes
,
759 UINT_32 pitchAlignInElement
,
761 UINT_32
* pHeight
) const;
763 VOID
ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
) const;
765 UINT_32 m_se
; ///< Number of shader engine
766 UINT_32 m_rbPerSe
; ///< Number of render backend per shader engine
767 UINT_32 m_maxCompFrag
; ///< Number of max compressed fragment
769 UINT_32 m_banksLog2
; ///< Number of bank Log2
770 UINT_32 m_pipesLog2
; ///< Number of pipe per shader engine Log2
771 UINT_32 m_seLog2
; ///< Number of shader engine Log2
772 UINT_32 m_rbPerSeLog2
; ///< Number of render backend per shader engine Log2
773 UINT_32 m_maxCompFragLog2
; ///< Number of max compressed fragment Log2
775 UINT_32 m_pipeInterleaveLog2
; ///< Log2 of pipe interleave bytes
777 UINT_32 m_blockVarSizeLog2
; ///< Log2 of block var size
779 SwizzleModeFlags m_swizzleModeTable
[ADDR_SW_MAX_TYPE
]; ///< Swizzle mode table
782 // Disallow the copy constructor
785 // Disallow the assignment operator
786 Lib
& operator=(const Lib
& a
);