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amd/addrlib: update Mesa's copy of addrlib
[mesa.git] / src / amd / addrlib / inc / addrinterface.h
1 /*
2 * Copyright © 2007-2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 /**
28 ****************************************************************************************************
29 * @file addrinterface.h
30 * @brief Contains the addrlib interfaces declaration and parameter defines
31 ****************************************************************************************************
32 */
33 #ifndef __ADDR_INTERFACE_H__
34 #define __ADDR_INTERFACE_H__
35
36 #include "addrtypes.h"
37
38 #if defined(__cplusplus)
39 extern "C"
40 {
41 #endif
42
43 #define ADDRLIB_VERSION_MAJOR 6
44 #define ADDRLIB_VERSION_MINOR 2
45 #define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR)
46
47 /// Virtually all interface functions need ADDR_HANDLE as first parameter
48 typedef VOID* ADDR_HANDLE;
49
50 /// Client handle used in callbacks
51 typedef VOID* ADDR_CLIENT_HANDLE;
52
53 /**
54 * /////////////////////////////////////////////////////////////////////////////////////////////////
55 * // Callback functions
56 * /////////////////////////////////////////////////////////////////////////////////////////////////
57 * typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
58 * const ADDR_ALLOCSYSMEM_INPUT* pInput);
59 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
60 * VOID* pVirtAddr);
61 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
62 * const ADDR_DEBUGPRINT_INPUT* pInput);
63 *
64 * /////////////////////////////////////////////////////////////////////////////////////////////////
65 * // Create/Destroy/Config functions
66 * /////////////////////////////////////////////////////////////////////////////////////////////////
67 * AddrCreate()
68 * AddrDestroy()
69 *
70 * /////////////////////////////////////////////////////////////////////////////////////////////////
71 * // Surface functions
72 * /////////////////////////////////////////////////////////////////////////////////////////////////
73 * AddrComputeSurfaceInfo()
74 * AddrComputeSurfaceAddrFromCoord()
75 * AddrComputeSurfaceCoordFromAddr()
76 *
77 * /////////////////////////////////////////////////////////////////////////////////////////////////
78 * // HTile functions
79 * /////////////////////////////////////////////////////////////////////////////////////////////////
80 * AddrComputeHtileInfo()
81 * AddrComputeHtileAddrFromCoord()
82 * AddrComputeHtileCoordFromAddr()
83 *
84 * /////////////////////////////////////////////////////////////////////////////////////////////////
85 * // C-mask functions
86 * /////////////////////////////////////////////////////////////////////////////////////////////////
87 * AddrComputeCmaskInfo()
88 * AddrComputeCmaskAddrFromCoord()
89 * AddrComputeCmaskCoordFromAddr()
90 *
91 * /////////////////////////////////////////////////////////////////////////////////////////////////
92 * // F-mask functions
93 * /////////////////////////////////////////////////////////////////////////////////////////////////
94 * AddrComputeFmaskInfo()
95 * AddrComputeFmaskAddrFromCoord()
96 * AddrComputeFmaskCoordFromAddr()
97 *
98 * /////////////////////////////////////////////////////////////////////////////////////////////////
99 * // Element/Utility functions
100 * /////////////////////////////////////////////////////////////////////////////////////////////////
101 * ElemFlt32ToDepthPixel()
102 * ElemFlt32ToColorPixel()
103 * AddrExtractBankPipeSwizzle()
104 * AddrCombineBankPipeSwizzle()
105 * AddrComputeSliceSwizzle()
106 * AddrConvertTileInfoToHW()
107 * AddrConvertTileIndex()
108 * AddrConvertTileIndex1()
109 * AddrGetTileIndex()
110 * AddrComputeBaseSwizzle()
111 * AddrUseTileIndex()
112 * AddrUseCombinedSwizzle()
113 *
114 **/
115
116 ////////////////////////////////////////////////////////////////////////////////////////////////////
117 // Callback functions
118 ////////////////////////////////////////////////////////////////////////////////////////////////////
119
120 /**
121 ****************************************************************************************************
122 * @brief channel setting structure
123 ****************************************************************************************************
124 */
125 typedef union _ADDR_CHANNEL_SETTING
126 {
127 struct
128 {
129 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid
130 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel
131 UINT_8 index : 5; ///< Channel index
132 };
133 UINT_8 value; ///< Value
134 } ADDR_CHANNEL_SETTING;
135
136 /**
137 ****************************************************************************************************
138 * @brief address equation key structure
139 ****************************************************************************************************
140 */
141 typedef union _ADDR_EQUATION_KEY
142 {
143 struct
144 {
145 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel
146 UINT_32 tileMode : 5; ///< Tile mode
147 UINT_32 microTileType : 3; ///< Micro tile type
148 UINT_32 pipeConfig : 5; ///< pipe config
149 UINT_32 numBanksLog2 : 3; ///< Number of banks log2
150 UINT_32 bankWidth : 4; ///< Bank width
151 UINT_32 bankHeight : 4; ///< Bank height
152 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio
153 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt
154 UINT_32 reserved : 1; ///< Reserved bit
155 } fields;
156 UINT_32 value;
157 } ADDR_EQUATION_KEY;
158
159 /**
160 ****************************************************************************************************
161 * @brief address equation structure
162 ****************************************************************************************************
163 */
164 #define ADDR_MAX_EQUATION_BIT 20u
165
166 // Invalid equation index
167 #define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF
168
169 typedef struct _ADDR_EQUATION
170 {
171 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting
172 ///< each bit is result of addr ^ xor ^ xor2
173 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting
174 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting
175 UINT_32 numBits; ///< The number of bits in equation
176 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being
177 ///< stacked vertically prior to swizzling
178 } ADDR_EQUATION;
179
180 /**
181 ****************************************************************************************************
182 * @brief Alloc system memory flags.
183 * @note These flags are reserved for future use and if flags are added will minimize the impact
184 * of the client.
185 ****************************************************************************************************
186 */
187 typedef union _ADDR_ALLOCSYSMEM_FLAGS
188 {
189 struct
190 {
191 UINT_32 reserved : 32; ///< Reserved for future use.
192 } fields;
193 UINT_32 value;
194
195 } ADDR_ALLOCSYSMEM_FLAGS;
196
197 /**
198 ****************************************************************************************************
199 * @brief Alloc system memory input structure
200 ****************************************************************************************************
201 */
202 typedef struct _ADDR_ALLOCSYSMEM_INPUT
203 {
204 UINT_32 size; ///< Size of this structure in bytes
205
206 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags.
207 UINT_32 sizeInBytes; ///< System memory allocation size in bytes.
208 ADDR_CLIENT_HANDLE hClient; ///< Client handle
209 } ADDR_ALLOCSYSMEM_INPUT;
210
211 /**
212 ****************************************************************************************************
213 * ADDR_ALLOCSYSMEM
214 * @brief
215 * Allocate system memory callback function. Returns valid pointer on success.
216 ****************************************************************************************************
217 */
218 typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
219 const ADDR_ALLOCSYSMEM_INPUT* pInput);
220
221 /**
222 ****************************************************************************************************
223 * @brief Free system memory input structure
224 ****************************************************************************************************
225 */
226 typedef struct _ADDR_FREESYSMEM_INPUT
227 {
228 UINT_32 size; ///< Size of this structure in bytes
229
230 VOID* pVirtAddr; ///< Virtual address
231 ADDR_CLIENT_HANDLE hClient; ///< Client handle
232 } ADDR_FREESYSMEM_INPUT;
233
234 /**
235 ****************************************************************************************************
236 * ADDR_FREESYSMEM
237 * @brief
238 * Free system memory callback function.
239 * Returns ADDR_OK on success.
240 ****************************************************************************************************
241 */
242 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
243 const ADDR_FREESYSMEM_INPUT* pInput);
244
245 /**
246 ****************************************************************************************************
247 * @brief Print debug message input structure
248 ****************************************************************************************************
249 */
250 typedef struct _ADDR_DEBUGPRINT_INPUT
251 {
252 UINT_32 size; ///< Size of this structure in bytes
253
254 CHAR* pDebugString; ///< Debug print string
255 va_list ap; ///< Variable argument list
256 ADDR_CLIENT_HANDLE hClient; ///< Client handle
257 } ADDR_DEBUGPRINT_INPUT;
258
259 /**
260 ****************************************************************************************************
261 * ADDR_DEBUGPRINT
262 * @brief
263 * Print debug message callback function.
264 * Returns ADDR_OK on success.
265 ****************************************************************************************************
266 */
267 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
268 const ADDR_DEBUGPRINT_INPUT* pInput);
269
270 /**
271 ****************************************************************************************************
272 * ADDR_CALLBACKS
273 *
274 * @brief
275 * Address Library needs client to provide system memory alloc/free routines.
276 ****************************************************************************************************
277 */
278 typedef struct _ADDR_CALLBACKS
279 {
280 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory
281 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory
282 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message
283 } ADDR_CALLBACKS;
284
285 ////////////////////////////////////////////////////////////////////////////////////////////////////
286 // Create/Destroy functions
287 ////////////////////////////////////////////////////////////////////////////////////////////////////
288
289 /**
290 ****************************************************************************************************
291 * ADDR_CREATE_FLAGS
292 *
293 * @brief
294 * This structure is used to pass some setup in creation of AddrLib
295 * @note
296 ****************************************************************************************************
297 */
298 typedef union _ADDR_CREATE_FLAGS
299 {
300 struct
301 {
302 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off
303 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and
304 /// output structure
305 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid
306 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle
307 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level
308 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
309 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
310 UINT_32 reserved : 25; ///< Reserved bits for future use
311 };
312
313 UINT_32 value;
314 } ADDR_CREATE_FLAGS;
315
316 /**
317 ****************************************************************************************************
318 * ADDR_REGISTER_VALUE
319 *
320 * @brief
321 * Data from registers to setup AddrLib global data, used in AddrCreate
322 ****************************************************************************************************
323 */
324 typedef struct _ADDR_REGISTER_VALUE
325 {
326 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value.
327 /// For R6xx/R7xx, use GB_TILING_CONFIG.
328 /// But they can be treated as the same.
329 /// if this value is 0, use chip to set default value
330 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled.
331 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE
332
333 /// R800 registers-----------------------------------------------
334 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK
335 /// No enums for this value in h/w header files
336 /// 0: 4
337 /// 1: 8
338 /// 2: 16
339 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK
340 /// 0: 1
341 /// 1: 2
342 /// SI (R1000) registers-----------------------------------------
343 const UINT_32* pTileConfig; ///< Global tile setting tables
344 UINT_32 noOfEntries; ///< Number of entries in pTileConfig
345
346 ///< CI registers-------------------------------------------------
347 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table
348 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig
349
350 ///< GFX9 HW parameters
351 UINT_32 blockVarSizeLog2; ///< SW_VAR_* block size
352 } ADDR_REGISTER_VALUE;
353
354 /**
355 ****************************************************************************************************
356 * ADDR_CREATE_INPUT
357 *
358 * @brief
359 * Parameters use to create an AddrLib Object. Caller must provide all fields.
360 *
361 ****************************************************************************************************
362 */
363 typedef struct _ADDR_CREATE_INPUT
364 {
365 UINT_32 size; ///< Size of this structure in bytes
366
367 UINT_32 chipEngine; ///< Chip Engine
368 UINT_32 chipFamily; ///< Chip Family
369 UINT_32 chipRevision; ///< Chip Revision
370 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print
371 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib
372 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data
373 ADDR_CLIENT_HANDLE hClient; ///< Client handle
374 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels
375 } ADDR_CREATE_INPUT;
376
377 /**
378 ****************************************************************************************************
379 * ADDR_CREATEINFO_OUTPUT
380 *
381 * @brief
382 * Return AddrLib handle to client driver
383 *
384 ****************************************************************************************************
385 */
386 typedef struct _ADDR_CREATE_OUTPUT
387 {
388 UINT_32 size; ///< Size of this structure in bytes
389
390 ADDR_HANDLE hLib; ///< Address lib handle
391
392 UINT_32 numEquations; ///< Number of equations in the table
393 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table
394 } ADDR_CREATE_OUTPUT;
395
396 /**
397 ****************************************************************************************************
398 * AddrCreate
399 *
400 * @brief
401 * Create AddrLib object, must be called before any interface calls
402 *
403 * @return
404 * ADDR_OK if successful
405 ****************************************************************************************************
406 */
407 ADDR_E_RETURNCODE ADDR_API AddrCreate(
408 const ADDR_CREATE_INPUT* pAddrCreateIn,
409 ADDR_CREATE_OUTPUT* pAddrCreateOut);
410
411 /**
412 ****************************************************************************************************
413 * AddrDestroy
414 *
415 * @brief
416 * Destroy AddrLib object, must be called to free internally allocated resources.
417 *
418 * @return
419 * ADDR_OK if successful
420 ****************************************************************************************************
421 */
422 ADDR_E_RETURNCODE ADDR_API AddrDestroy(
423 ADDR_HANDLE hLib);
424
425 ////////////////////////////////////////////////////////////////////////////////////////////////////
426 // Surface functions
427 ////////////////////////////////////////////////////////////////////////////////////////////////////
428
429 /**
430 ****************************************************************************************************
431 * @brief
432 * Bank/tiling parameters. On function input, these can be set as desired or
433 * left 0 for AddrLib to calculate/default. On function output, these are the actual
434 * parameters used.
435 * @note
436 * Valid bankWidth/bankHeight value:
437 * 1,2,4,8. They are factors instead of pixels or bytes.
438 *
439 * The bank number remains constant across each row of the
440 * macro tile as each pipe is selected, so the number of
441 * tiles in the x direction with the same bank number will
442 * be bank_width * num_pipes.
443 ****************************************************************************************************
444 */
445 typedef struct _ADDR_TILEINFO
446 {
447 /// Any of these parameters can be set to 0 to use the HW default.
448 UINT_32 banks; ///< Number of banks, numerical value
449 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank
450 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank
451 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1
452 UINT_32 tileSplitBytes; ///< Tile split size, in bytes
453 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1
454 } ADDR_TILEINFO;
455
456 // Create a define to avoid client change. The removal of R800 is because we plan to implement SI
457 // within 800 HWL - An AddrPipeCfg is added in above data structure
458 typedef ADDR_TILEINFO ADDR_R800_TILEINFO;
459
460 /**
461 ****************************************************************************************************
462 * @brief
463 * Information needed by quad buffer stereo support
464 ****************************************************************************************************
465 */
466 typedef struct _ADDR_QBSTEREOINFO
467 {
468 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye
469 UINT_32 rightOffset; ///< Offset (in bytes) to right eye
470 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes
471 } ADDR_QBSTEREOINFO;
472
473 /**
474 ****************************************************************************************************
475 * ADDR_SURFACE_FLAGS
476 *
477 * @brief
478 * Surface flags
479 ****************************************************************************************************
480 */
481 typedef union _ADDR_SURFACE_FLAGS
482 {
483 struct
484 {
485 UINT_32 color : 1; ///< Flag indicates this is a color buffer
486 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer
487 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer
488 UINT_32 texture : 1; ///< Flag indicates this is a texture
489 UINT_32 cube : 1; ///< Flag indicates this is a cubemap
490 UINT_32 volume : 1; ///< Flag indicates this is a volume texture
491 UINT_32 fmask : 1; ///< Flag indicates this is an fmask
492 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays
493 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed
494 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface
495 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil
496 UINT_32 display : 1; ///< Flag indicates this should match display controller req.
497 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space
498 /// i.e. save some memory but may lose performance
499 UINT_32 prt : 1; ///< Flag for partially resident texture
500 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface
501 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)
502 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
503 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
504 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce
505 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear
506 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that
507 /// dcc can't be enabled if pipe config of tile mode
508 /// is different from that of ASIC, this flag
509 /// is address lib internal flag, client should ignore it
510 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment.
511 /// This flag indicates we need to follow the
512 /// alignment with CZ families or other ASICs under
513 /// PX configuration + CZ.
514 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split
515 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear
516 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible.
517 /// This flag indicates we need to override tile
518 /// mode to PRT_* tile mode to disable slice rotation,
519 /// which is needed by swizzle pattern equation.
520 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output.
521 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type
522 UINT_32 minimizeAlignment : 1; ///< Minimize alignment
523 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode
524 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface
525 /// to make sure they share same tile config parameters
526 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade
527 UINT_32 reserved : 1; ///< Reserved bits
528 };
529
530 UINT_32 value;
531 } ADDR_SURFACE_FLAGS;
532
533 /**
534 ****************************************************************************************************
535 * ADDR_COMPUTE_SURFACE_INFO_INPUT
536 *
537 * @brief
538 * Input structure for AddrComputeSurfaceInfo
539 ****************************************************************************************************
540 */
541 typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT
542 {
543 UINT_32 size; ///< Size of this structure in bytes
544
545 AddrTileMode tileMode; ///< Tile mode
546 AddrFormat format; ///< If format is set to valid one, bpp/width/height
547 /// might be overwritten
548 UINT_32 bpp; ///< Bits per pixel
549 UINT_32 numSamples; ///< Number of samples
550 UINT_32 width; ///< Width, in pixels
551 UINT_32 height; ///< Height, in pixels
552 UINT_32 numSlices; ///< Number of surface slices or depth
553 UINT_32 slice; ///< Slice index
554 UINT_32 mipLevel; ///< Current mipmap level
555 UINT_32 numMipLevels; ///< Number of mips in mip chain
556 ADDR_SURFACE_FLAGS flags; ///< Surface type flags
557 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
558 /// number of samples for normal AA; Set it to the
559 /// number of fragments for EQAA
560 /// r800 and later HWL parameters
561 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's
562 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate
563 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1
564 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
565 /// while the global useTileIndex is set to 1
566 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a
567 /// must for mip levels from SI+.
568 /// Don't use pitch in blocks for compressed formats!
569 UINT_32 maxBaseAlign; ///< Max base alignment request from client
570 UINT_32 pitchAlign; ///< Pitch alignment request from client
571 UINT_32 heightAlign; ///< Height alignment request from client
572 } ADDR_COMPUTE_SURFACE_INFO_INPUT;
573
574 /**
575 ****************************************************************************************************
576 * ADDR_COMPUTE_SURFACE_INFO_OUTPUT
577 *
578 * @brief
579 * Output structure for AddrComputeSurfInfo
580 * @note
581 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
582 Pixel: Original pixel
583 ****************************************************************************************************
584 */
585 typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
586 {
587 UINT_32 size; ///< Size of this structure in bytes
588
589 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats)
590 UINT_32 height; ///< Height in elements (in blocks for compressed formats)
591 UINT_32 depth; ///< Number of slice/depth
592 UINT_64 surfSize; ///< Surface size in bytes
593 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input
594 UINT_32 baseAlign; ///< Base address alignment
595 UINT_32 pitchAlign; ///< Pitch alignment, in elements
596 UINT_32 heightAlign; ///< Height alignment, in elements
597 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture
598 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit)
599 UINT_32 pixelPitch; ///< Pitch in original pixels
600 UINT_32 pixelHeight; ///< Height in original pixels
601 UINT_32 pixelBits; ///< Original bits per pixel, passed from input
602 UINT_64 sliceSize; ///< Size of slice specified by input's slice
603 /// The result is controlled by surface flags & createFlags
604 /// By default this value equals to surfSize for volume
605 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register
606 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register
607 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register
608
609 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call
610
611 /// r800 and later HWL parameters
612 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input
613 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1
614 INT_32 tileIndex; ///< Tile index, MAY be "downgraded"
615
616 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
617 /// Output flags
618 struct
619 {
620 /// Special information to work around SI mipmap swizzle bug UBTS #317508
621 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled
622 ///< Only meaningful when create flag checkLast2DLevel is set
623 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible
624 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering
625 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT
626 ///< If address lib return true for mip 0, client should set prt flag
627 ///< for child mips in subsequent compute surface info calls
628 UINT_32 reserved :28; ///< Reserved bits
629 };
630
631 UINT_32 equationIndex; ///< Equation index in the equation table;
632
633 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro)
634 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro)
635 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro)
636
637 /// Stereo info
638 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
639
640 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set
641 } ADDR_COMPUTE_SURFACE_INFO_OUTPUT;
642
643 /**
644 ****************************************************************************************************
645 * AddrComputeSurfaceInfo
646 *
647 * @brief
648 * Compute surface width/height/depth/alignments and suitable tiling mode
649 ****************************************************************************************************
650 */
651 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
652 ADDR_HANDLE hLib,
653 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
654 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
655
656 /**
657 ****************************************************************************************************
658 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
659 *
660 * @brief
661 * Input structure for AddrComputeSurfaceAddrFromCoord
662 ****************************************************************************************************
663 */
664 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
665 {
666 UINT_32 size; ///< Size of this structure in bytes
667
668 UINT_32 x; ///< X coordinate
669 UINT_32 y; ///< Y coordinate
670 UINT_32 slice; ///< Slice index
671 UINT_32 sample; ///< Sample index, use fragment index for EQAA
672
673 UINT_32 bpp; ///< Bits per pixel
674 UINT_32 pitch; ///< Surface pitch, in pixels
675 UINT_32 height; ///< Surface height, in pixels
676 UINT_32 numSlices; ///< Surface depth
677 UINT_32 numSamples; ///< Number of samples
678
679 AddrTileMode tileMode; ///< Tile mode
680 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within
681 /// micro tile. Textures can also choose depth sample order
682 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles
683 /// the case that components are stored separately
684 UINT_32 compBits; ///< The component bits actually needed(for planar surface)
685
686 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
687 /// number of samples for normal AA; Set it to the
688 /// number of fragments for EQAA
689 /// r800 and later HWL parameters
690 // Used for 1D tiling above
691 AddrTileType tileType; ///< See defintion of AddrTileType
692 struct
693 {
694 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture
695 /// only flag. Only non-RT texture can set this to TRUE
696 UINT_32 reserved :31; ///< Reserved for future use.
697 };
698 // 2D tiling needs following structure
699 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
700 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
701 /// while the global useTileIndex is set to 1
702 union
703 {
704 struct
705 {
706 UINT_32 bankSwizzle; ///< Bank swizzle
707 UINT_32 pipeSwizzle; ///< Pipe swizzle
708 };
709 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
710 };
711 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
712
713 /**
714 ****************************************************************************************************
715 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
716 *
717 * @brief
718 * Output structure for AddrComputeSurfaceAddrFromCoord
719 ****************************************************************************************************
720 */
721 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
722 {
723 UINT_32 size; ///< Size of this structure in bytes
724
725 UINT_64 addr; ///< Byte address
726 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.
727 /// For surface bpp < 8, e.g. FMT_1.
728 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)
729 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
730
731 /**
732 ****************************************************************************************************
733 * AddrComputeSurfaceAddrFromCoord
734 *
735 * @brief
736 * Compute surface address from a given coordinate.
737 ****************************************************************************************************
738 */
739 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
740 ADDR_HANDLE hLib,
741 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
742 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
743
744 /**
745 ****************************************************************************************************
746 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
747 *
748 * @brief
749 * Input structure for AddrComputeSurfaceCoordFromAddr
750 ****************************************************************************************************
751 */
752 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
753 {
754 UINT_32 size; ///< Size of this structure in bytes
755
756 UINT_64 addr; ///< Address in bytes
757 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,
758 /// e.g. FMT_1;
759 UINT_32 bpp; ///< Bits per pixel
760 UINT_32 pitch; ///< Pitch, in pixels
761 UINT_32 height; ///< Height in pixels
762 UINT_32 numSlices; ///< Surface depth
763 UINT_32 numSamples; ///< Number of samples
764
765 AddrTileMode tileMode; ///< Tile mode
766 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile.
767 /// Note: Textures can choose depth sample order as well.
768 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles
769 /// the case that components are stored separately
770 UINT_32 compBits; ///< The component bits actually needed(for planar surface)
771
772 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
773 /// number of samples for normal AA; Set it to the
774 /// number of fragments for EQAA
775 /// r800 and later HWL parameters
776 // Used for 1D tiling above
777 AddrTileType tileType; ///< See defintion of AddrTileType
778 struct
779 {
780 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture
781 /// only flag. Only non-RT texture can set this to TRUE
782 UINT_32 reserved :31; ///< Reserved for future use.
783 };
784 // 2D tiling needs following structure
785 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
786 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
787 /// while the global useTileIndex is set to 1
788 union
789 {
790 struct
791 {
792 UINT_32 bankSwizzle; ///< Bank swizzle
793 UINT_32 pipeSwizzle; ///< Pipe swizzle
794 };
795 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
796 };
797 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
798
799 /**
800 ****************************************************************************************************
801 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
802 *
803 * @brief
804 * Output structure for AddrComputeSurfaceCoordFromAddr
805 ****************************************************************************************************
806 */
807 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
808 {
809 UINT_32 size; ///< Size of this structure in bytes
810
811 UINT_32 x; ///< X coordinate
812 UINT_32 y; ///< Y coordinate
813 UINT_32 slice; ///< Index of slices
814 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
815 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
816
817 /**
818 ****************************************************************************************************
819 * AddrComputeSurfaceCoordFromAddr
820 *
821 * @brief
822 * Compute coordinate from a given surface address
823 ****************************************************************************************************
824 */
825 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
826 ADDR_HANDLE hLib,
827 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
828 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
829
830 ////////////////////////////////////////////////////////////////////////////////////////////////////
831 // HTile functions
832 ////////////////////////////////////////////////////////////////////////////////////////////////////
833
834 /**
835 ****************************************************************************************************
836 * ADDR_HTILE_FLAGS
837 *
838 * @brief
839 * HTILE flags
840 ****************************************************************************************************
841 */
842 typedef union _ADDR_HTILE_FLAGS
843 {
844 struct
845 {
846 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
847 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile
848 /// size to 256xBankxPipe when computing tc-compatible
849 /// htile info.
850 UINT_32 reserved : 30; ///< Reserved bits
851 };
852
853 UINT_32 value;
854 } ADDR_HTILE_FLAGS;
855
856 /**
857 ****************************************************************************************************
858 * ADDR_COMPUTE_HTILE_INFO_INPUT
859 *
860 * @brief
861 * Input structure of AddrComputeHtileInfo
862 ****************************************************************************************************
863 */
864 typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT
865 {
866 UINT_32 size; ///< Size of this structure in bytes
867
868 ADDR_HTILE_FLAGS flags; ///< HTILE flags
869 UINT_32 pitch; ///< Surface pitch, in pixels
870 UINT_32 height; ///< Surface height, in pixels
871 UINT_32 numSlices; ///< Number of slices
872 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
873 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8
874 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8
875 ADDR_TILEINFO* pTileInfo; ///< Tile info
876
877 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
878 /// while the global useTileIndex is set to 1
879 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
880 ///< README: When tileIndex is not -1, this must be valid
881 } ADDR_COMPUTE_HTILE_INFO_INPUT;
882
883 /**
884 ****************************************************************************************************
885 * ADDR_COMPUTE_HTILE_INFO_OUTPUT
886 *
887 * @brief
888 * Output structure of AddrComputeHtileInfo
889 ****************************************************************************************************
890 */
891 typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
892 {
893 UINT_32 size; ///< Size of this structure in bytes
894
895 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this
896 /// HTile buffer. This might be larger than original depth
897 /// buffer pitch when called with an unaligned pitch.
898 UINT_32 height; ///< Height in pixels, as above
899 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes
900 UINT_32 baseAlign; ///< Base alignment
901 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block!
902 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
903 UINT_32 macroHeight; ///< Macro height in pixels
904 UINT_64 sliceSize; ///< Slice size, in bytes.
905 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
906 /// Compute engine clear can't be used if htile is interleaved
907 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in
908 /// next mip level, it also indicates if memory set based
909 /// fast clear can be used for current mip level.
910 } ADDR_COMPUTE_HTILE_INFO_OUTPUT;
911
912 /**
913 ****************************************************************************************************
914 * AddrComputeHtileInfo
915 *
916 * @brief
917 * Compute Htile pitch, height, base alignment and size in bytes
918 ****************************************************************************************************
919 */
920 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
921 ADDR_HANDLE hLib,
922 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
923 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut);
924
925 /**
926 ****************************************************************************************************
927 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
928 *
929 * @brief
930 * Input structure for AddrComputeHtileAddrFromCoord
931 ****************************************************************************************************
932 */
933 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
934 {
935 UINT_32 size; ///< Size of this structure in bytes
936
937 UINT_32 pitch; ///< Pitch, in pixels
938 UINT_32 height; ///< Height in pixels
939 UINT_32 x; ///< X coordinate
940 UINT_32 y; ///< Y coordinate
941 UINT_32 slice; ///< Index of slice
942 UINT_32 numSlices; ///< Number of slices
943 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
944 ADDR_HTILE_FLAGS flags; ///< htile flags
945 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
946 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
947 ADDR_TILEINFO* pTileInfo; ///< Tile info
948
949 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
950 /// while the global useTileIndex is set to 1
951 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
952 ///< README: When tileIndex is not -1, this must be valid
953 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size
954 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address
955 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
956
957 /**
958 ****************************************************************************************************
959 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
960 *
961 * @brief
962 * Output structure for AddrComputeHtileAddrFromCoord
963 ****************************************************************************************************
964 */
965 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
966 {
967 UINT_32 size; ///< Size of this structure in bytes
968
969 UINT_64 addr; ///< Address in bytes
970 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method.
971 /// So we keep bitPosition for HTILE as well
972 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
973
974 /**
975 ****************************************************************************************************
976 * AddrComputeHtileAddrFromCoord
977 *
978 * @brief
979 * Compute Htile address according to coordinates (of depth buffer)
980 ****************************************************************************************************
981 */
982 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
983 ADDR_HANDLE hLib,
984 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
985 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
986
987 /**
988 ****************************************************************************************************
989 * ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
990 *
991 * @brief
992 * Input structure for AddrComputeHtileCoordFromAddr
993 ****************************************************************************************************
994 */
995 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
996 {
997 UINT_32 size; ///< Size of this structure in bytes
998
999 UINT_64 addr; ///< Address
1000 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods
1001 /// so we keep bitPosition for HTILE as well
1002 UINT_32 pitch; ///< Pitch, in pixels
1003 UINT_32 height; ///< Height, in pixels
1004 UINT_32 numSlices; ///< Number of slices
1005 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
1006 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1007 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1008 ADDR_TILEINFO* pTileInfo; ///< Tile info
1009
1010 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1011 /// while the global useTileIndex is set to 1
1012 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1013 ///< README: When tileIndex is not -1, this must be valid
1014 } ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT;
1015
1016 /**
1017 ****************************************************************************************************
1018 * ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1019 *
1020 * @brief
1021 * Output structure for AddrComputeHtileCoordFromAddr
1022 ****************************************************************************************************
1023 */
1024 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1025 {
1026 UINT_32 size; ///< Size of this structure in bytes
1027
1028 UINT_32 x; ///< X coordinate
1029 UINT_32 y; ///< Y coordinate
1030 UINT_32 slice; ///< Slice index
1031 } ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
1032
1033 /**
1034 ****************************************************************************************************
1035 * AddrComputeHtileCoordFromAddr
1036 *
1037 * @brief
1038 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to
1039 * Htile address
1040 ****************************************************************************************************
1041 */
1042 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
1043 ADDR_HANDLE hLib,
1044 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
1045 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
1046
1047 ////////////////////////////////////////////////////////////////////////////////////////////////////
1048 // C-mask functions
1049 ////////////////////////////////////////////////////////////////////////////////////////////////////
1050
1051 /**
1052 ****************************************************************************************************
1053 * ADDR_CMASK_FLAGS
1054 *
1055 * @brief
1056 * CMASK flags
1057 ****************************************************************************************************
1058 */
1059 typedef union _ADDR_CMASK_FLAGS
1060 {
1061 struct
1062 {
1063 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
1064 UINT_32 reserved :31; ///< Reserved bits
1065 };
1066
1067 UINT_32 value;
1068 } ADDR_CMASK_FLAGS;
1069
1070 /**
1071 ****************************************************************************************************
1072 * ADDR_COMPUTE_CMASK_INFO_INPUT
1073 *
1074 * @brief
1075 * Input structure of AddrComputeCmaskInfo
1076 ****************************************************************************************************
1077 */
1078 typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT
1079 {
1080 UINT_32 size; ///< Size of this structure in bytes
1081
1082 ADDR_CMASK_FLAGS flags; ///< CMASK flags
1083 UINT_32 pitch; ///< Pitch, in pixels, of color buffer
1084 UINT_32 height; ///< Height, in pixels, of color buffer
1085 UINT_32 numSlices; ///< Number of slices, of color buffer
1086 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1087 ADDR_TILEINFO* pTileInfo; ///< Tile info
1088
1089 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1090 /// while the global useTileIndex is set to 1
1091 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1092 ///< README: When tileIndex is not -1, this must be valid
1093 } ADDR_COMPUTE_CMASK_INFO_INPUT;
1094
1095 /**
1096 ****************************************************************************************************
1097 * ADDR_COMPUTE_CMASK_INFO_OUTPUT
1098 *
1099 * @brief
1100 * Output structure of AddrComputeCmaskInfo
1101 ****************************************************************************************************
1102 */
1103 typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT
1104 {
1105 UINT_32 size; ///< Size of this structure in bytes
1106
1107 UINT_32 pitch; ///< Pitch in pixels of color buffer which
1108 /// this Cmask matches. The size might be larger than
1109 /// original color buffer pitch when called with
1110 /// an unaligned pitch.
1111 UINT_32 height; ///< Height in pixels, as above
1112 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer
1113 UINT_32 baseAlign; ///< Base alignment
1114 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register
1115 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
1116 UINT_32 macroHeight; ///< Macro height in pixels
1117 UINT_64 sliceSize; ///< Slice size, in bytes.
1118 } ADDR_COMPUTE_CMASK_INFO_OUTPUT;
1119
1120 /**
1121 ****************************************************************************************************
1122 * AddrComputeCmaskInfo
1123 *
1124 * @brief
1125 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer
1126 * info
1127 ****************************************************************************************************
1128 */
1129 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
1130 ADDR_HANDLE hLib,
1131 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
1132 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut);
1133
1134 /**
1135 ****************************************************************************************************
1136 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1137 *
1138 * @brief
1139 * Input structure for AddrComputeCmaskAddrFromCoord
1140 *
1141 ****************************************************************************************************
1142 */
1143 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1144 {
1145 UINT_32 size; ///< Size of this structure in bytes
1146 UINT_32 x; ///< X coordinate
1147 UINT_32 y; ///< Y coordinate
1148 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask
1149 UINT_32 slice; ///< Slice index
1150 UINT_32 pitch; ///< Pitch in pixels, of color buffer
1151 UINT_32 height; ///< Height in pixels, of color buffer
1152 UINT_32 numSlices; ///< Number of slices
1153 UINT_32 bpp;
1154 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1155 ADDR_CMASK_FLAGS flags; ///< CMASK flags
1156 ADDR_TILEINFO* pTileInfo; ///< Tile info
1157
1158 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1159 ///< while the global useTileIndex is set to 1
1160 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1161 ///< README: When tileIndex is not -1, this must be valid
1162 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
1163
1164 /**
1165 ****************************************************************************************************
1166 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1167 *
1168 * @brief
1169 * Output structure for AddrComputeCmaskAddrFromCoord
1170 ****************************************************************************************************
1171 */
1172 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1173 {
1174 UINT_32 size; ///< Size of this structure in bytes
1175
1176 UINT_64 addr; ///< CMASK address in bytes
1177 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1178 /// so the address may be located in bit 0 (0) or 4 (4)
1179 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
1180
1181 /**
1182 ****************************************************************************************************
1183 * AddrComputeCmaskAddrFromCoord
1184 *
1185 * @brief
1186 * Compute Cmask address according to coordinates (of MSAA color buffer)
1187 ****************************************************************************************************
1188 */
1189 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
1190 ADDR_HANDLE hLib,
1191 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
1192 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
1193
1194 /**
1195 ****************************************************************************************************
1196 * ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1197 *
1198 * @brief
1199 * Input structure for AddrComputeCmaskCoordFromAddr
1200 ****************************************************************************************************
1201 */
1202 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1203 {
1204 UINT_32 size; ///< Size of this structure in bytes
1205
1206 UINT_64 addr; ///< CMASK address in bytes
1207 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1208 /// so the address may be located in bit 0 (0) or 4 (4)
1209 UINT_32 pitch; ///< Pitch, in pixels
1210 UINT_32 height; ///< Height in pixels
1211 UINT_32 numSlices; ///< Number of slices
1212 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1213 ADDR_TILEINFO* pTileInfo; ///< Tile info
1214
1215 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1216 /// while the global useTileIndex is set to 1
1217 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1218 ///< README: When tileIndex is not -1, this must be valid
1219 } ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT;
1220
1221 /**
1222 ****************************************************************************************************
1223 * ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1224 *
1225 * @brief
1226 * Output structure for AddrComputeCmaskCoordFromAddr
1227 ****************************************************************************************************
1228 */
1229 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1230 {
1231 UINT_32 size; ///< Size of this structure in bytes
1232
1233 UINT_32 x; ///< X coordinate
1234 UINT_32 y; ///< Y coordinate
1235 UINT_32 slice; ///< Slice index
1236 } ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
1237
1238 /**
1239 ****************************************************************************************************
1240 * AddrComputeCmaskCoordFromAddr
1241 *
1242 * @brief
1243 * Compute coordinates within color buffer (1st pixel of a micro tile) according to
1244 * Cmask address
1245 ****************************************************************************************************
1246 */
1247 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
1248 ADDR_HANDLE hLib,
1249 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
1250 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
1251
1252 ////////////////////////////////////////////////////////////////////////////////////////////////////
1253 // F-mask functions
1254 ////////////////////////////////////////////////////////////////////////////////////////////////////
1255
1256 /**
1257 ****************************************************************************************************
1258 * ADDR_COMPUTE_FMASK_INFO_INPUT
1259 *
1260 * @brief
1261 * Input structure for AddrComputeFmaskInfo
1262 ****************************************************************************************************
1263 */
1264 typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT
1265 {
1266 UINT_32 size; ///< Size of this structure in bytes
1267
1268 AddrTileMode tileMode; ///< Tile mode
1269 UINT_32 pitch; ///< Surface pitch, in pixels
1270 UINT_32 height; ///< Surface height, in pixels
1271 UINT_32 numSlices; ///< Number of slice/depth
1272 UINT_32 numSamples; ///< Number of samples
1273 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
1274 /// number of samples for normal AA; Set it to the
1275 /// number of fragments for EQAA
1276 /// r800 and later HWL parameters
1277 struct
1278 {
1279 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used
1280 /// by H/W clients. S/W should always set it to FALSE.
1281 UINT_32 reserved: 31; ///< Reserved for future use.
1282 };
1283 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data
1284 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1285 /// while the global useTileIndex is set to 1
1286 } ADDR_COMPUTE_FMASK_INFO_INPUT;
1287
1288 /**
1289 ****************************************************************************************************
1290 * ADDR_COMPUTE_FMASK_INFO_OUTPUT
1291 *
1292 * @brief
1293 * Output structure for AddrComputeFmaskInfo
1294 ****************************************************************************************************
1295 */
1296 typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT
1297 {
1298 UINT_32 size; ///< Size of this structure in bytes
1299
1300 UINT_32 pitch; ///< Pitch of fmask in pixels
1301 UINT_32 height; ///< Height of fmask in pixels
1302 UINT_32 numSlices; ///< Slices of fmask
1303 UINT_64 fmaskBytes; ///< Size of fmask in bytes
1304 UINT_32 baseAlign; ///< Base address alignment
1305 UINT_32 pitchAlign; ///< Pitch alignment
1306 UINT_32 heightAlign; ///< Height alignment
1307 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes
1308 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input
1309 /// may be changed in 9xx and above
1310 /// r800 and later HWL parameters
1311 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different
1312 /// bank_height from color buffer
1313 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1314 /// while the global useTileIndex is set to 1
1315 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1316 UINT_64 sliceSize; ///< Size of slice in bytes
1317 } ADDR_COMPUTE_FMASK_INFO_OUTPUT;
1318
1319 /**
1320 ****************************************************************************************************
1321 * AddrComputeFmaskInfo
1322 *
1323 * @brief
1324 * Compute Fmask pitch/height/depth/alignments and size in bytes
1325 ****************************************************************************************************
1326 */
1327 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
1328 ADDR_HANDLE hLib,
1329 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
1330 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
1331
1332 /**
1333 ****************************************************************************************************
1334 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1335 *
1336 * @brief
1337 * Input structure for AddrComputeFmaskAddrFromCoord
1338 ****************************************************************************************************
1339 */
1340 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1341 {
1342 UINT_32 size; ///< Size of this structure in bytes
1343
1344 UINT_32 x; ///< X coordinate
1345 UINT_32 y; ///< Y coordinate
1346 UINT_32 slice; ///< Slice index
1347 UINT_32 plane; ///< Plane number
1348 UINT_32 sample; ///< Sample index (fragment index for EQAA)
1349
1350 UINT_32 pitch; ///< Surface pitch, in pixels
1351 UINT_32 height; ///< Surface height, in pixels
1352 UINT_32 numSamples; ///< Number of samples
1353 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
1354 /// number of samples for normal AA; Set it to the
1355 /// number of fragments for EQAA
1356
1357 AddrTileMode tileMode; ///< Tile mode
1358 union
1359 {
1360 struct
1361 {
1362 UINT_32 bankSwizzle; ///< Bank swizzle
1363 UINT_32 pipeSwizzle; ///< Pipe swizzle
1364 };
1365 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
1366 };
1367
1368 /// r800 and later HWL parameters
1369 struct
1370 {
1371 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients
1372 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.
1373 UINT_32 reserved: 30; ///< Reserved for future use.
1374 };
1375 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data
1376
1377 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
1378
1379 /**
1380 ****************************************************************************************************
1381 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1382 *
1383 * @brief
1384 * Output structure for AddrComputeFmaskAddrFromCoord
1385 ****************************************************************************************************
1386 */
1387 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1388 {
1389 UINT_32 size; ///< Size of this structure in bytes
1390
1391 UINT_64 addr; ///< Fmask address
1392 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.
1393 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
1394
1395 /**
1396 ****************************************************************************************************
1397 * AddrComputeFmaskAddrFromCoord
1398 *
1399 * @brief
1400 * Compute Fmask address according to coordinates (x,y,slice,sample,plane)
1401 ****************************************************************************************************
1402 */
1403 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
1404 ADDR_HANDLE hLib,
1405 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
1406 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
1407
1408 /**
1409 ****************************************************************************************************
1410 * ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1411 *
1412 * @brief
1413 * Input structure for AddrComputeFmaskCoordFromAddr
1414 ****************************************************************************************************
1415 */
1416 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1417 {
1418 UINT_32 size; ///< Size of this structure in bytes
1419
1420 UINT_64 addr; ///< Address
1421 UINT_32 bitPosition; ///< Bit position within addr, 0-7.
1422
1423 UINT_32 pitch; ///< Pitch, in pixels
1424 UINT_32 height; ///< Height in pixels
1425 UINT_32 numSamples; ///< Number of samples
1426 UINT_32 numFrags; ///< Number of fragments
1427 AddrTileMode tileMode; ///< Tile mode
1428 union
1429 {
1430 struct
1431 {
1432 UINT_32 bankSwizzle; ///< Bank swizzle
1433 UINT_32 pipeSwizzle; ///< Pipe swizzle
1434 };
1435 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
1436 };
1437
1438 /// r800 and later HWL parameters
1439 struct
1440 {
1441 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components
1442 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.
1443 UINT_32 reserved: 30; ///< Reserved for future use.
1444 };
1445 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1446
1447 } ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT;
1448
1449 /**
1450 ****************************************************************************************************
1451 * ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1452 *
1453 * @brief
1454 * Output structure for AddrComputeFmaskCoordFromAddr
1455 ****************************************************************************************************
1456 */
1457 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1458 {
1459 UINT_32 size; ///< Size of this structure in bytes
1460
1461 UINT_32 x; ///< X coordinate
1462 UINT_32 y; ///< Y coordinate
1463 UINT_32 slice; ///< Slice index
1464 UINT_32 plane; ///< Plane number
1465 UINT_32 sample; ///< Sample index (fragment index for EQAA)
1466 } ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
1467
1468 /**
1469 ****************************************************************************************************
1470 * AddrComputeFmaskCoordFromAddr
1471 *
1472 * @brief
1473 * Compute FMASK coordinate from an given address
1474 ****************************************************************************************************
1475 */
1476 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
1477 ADDR_HANDLE hLib,
1478 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
1479 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
1480
1481 ////////////////////////////////////////////////////////////////////////////////////////////////////
1482 // Element/utility functions
1483 ////////////////////////////////////////////////////////////////////////////////////////////////////
1484
1485 /**
1486 ****************************************************************************************************
1487 * AddrGetVersion
1488 *
1489 * @brief
1490 * Get AddrLib version number
1491 ****************************************************************************************************
1492 */
1493 UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib);
1494
1495 /**
1496 ****************************************************************************************************
1497 * AddrUseTileIndex
1498 *
1499 * @brief
1500 * Return TRUE if tileIndex is enabled in this address library
1501 ****************************************************************************************************
1502 */
1503 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);
1504
1505 /**
1506 ****************************************************************************************************
1507 * AddrUseCombinedSwizzle
1508 *
1509 * @brief
1510 * Return TRUE if combined swizzle is enabled in this address library
1511 ****************************************************************************************************
1512 */
1513 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);
1514
1515 /**
1516 ****************************************************************************************************
1517 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1518 *
1519 * @brief
1520 * Input structure of AddrExtractBankPipeSwizzle
1521 ****************************************************************************************************
1522 */
1523 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1524 {
1525 UINT_32 size; ///< Size of this structure in bytes
1526
1527 UINT_32 base256b; ///< Base256b value
1528
1529 /// r800 and later HWL parameters
1530 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1531
1532 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1533 /// while the global useTileIndex is set to 1
1534 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1535 ///< README: When tileIndex is not -1, this must be valid
1536 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT;
1537
1538 /**
1539 ****************************************************************************************************
1540 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1541 *
1542 * @brief
1543 * Output structure of AddrExtractBankPipeSwizzle
1544 ****************************************************************************************************
1545 */
1546 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1547 {
1548 UINT_32 size; ///< Size of this structure in bytes
1549
1550 UINT_32 bankSwizzle; ///< Bank swizzle
1551 UINT_32 pipeSwizzle; ///< Pipe swizzle
1552 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT;
1553
1554 /**
1555 ****************************************************************************************************
1556 * AddrExtractBankPipeSwizzle
1557 *
1558 * @brief
1559 * Extract Bank and Pipe swizzle from base256b
1560 * @return
1561 * ADDR_OK if no error
1562 ****************************************************************************************************
1563 */
1564 ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
1565 ADDR_HANDLE hLib,
1566 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
1567 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut);
1568
1569 /**
1570 ****************************************************************************************************
1571 * ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1572 *
1573 * @brief
1574 * Input structure of AddrCombineBankPipeSwizzle
1575 ****************************************************************************************************
1576 */
1577 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1578 {
1579 UINT_32 size; ///< Size of this structure in bytes
1580
1581 UINT_32 bankSwizzle; ///< Bank swizzle
1582 UINT_32 pipeSwizzle; ///< Pipe swizzle
1583 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients)
1584
1585 /// r800 and later HWL parameters
1586 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1587
1588 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1589 /// while the global useTileIndex is set to 1
1590 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1591 ///< README: When tileIndex is not -1, this must be valid
1592 } ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT;
1593
1594 /**
1595 ****************************************************************************************************
1596 * ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1597 *
1598 * @brief
1599 * Output structure of AddrCombineBankPipeSwizzle
1600 ****************************************************************************************************
1601 */
1602 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1603 {
1604 UINT_32 size; ///< Size of this structure in bytes
1605
1606 UINT_32 tileSwizzle; ///< Combined swizzle
1607 } ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT;
1608
1609 /**
1610 ****************************************************************************************************
1611 * AddrCombineBankPipeSwizzle
1612 *
1613 * @brief
1614 * Combine Bank and Pipe swizzle
1615 * @return
1616 * ADDR_OK if no error
1617 * @note
1618 * baseAddr here is full MCAddress instead of base256b
1619 ****************************************************************************************************
1620 */
1621 ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
1622 ADDR_HANDLE hLib,
1623 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,
1624 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut);
1625
1626 /**
1627 ****************************************************************************************************
1628 * ADDR_COMPUTE_SLICESWIZZLE_INPUT
1629 *
1630 * @brief
1631 * Input structure of AddrComputeSliceSwizzle
1632 ****************************************************************************************************
1633 */
1634 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
1635 {
1636 UINT_32 size; ///< Size of this structure in bytes
1637
1638 AddrTileMode tileMode; ///< Tile Mode
1639 UINT_32 baseSwizzle; ///< Base tile swizzle
1640 UINT_32 slice; ///< Slice index
1641 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases
1642
1643 /// r800 and later HWL parameters
1644 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1645
1646 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1647 /// while the global useTileIndex is set to 1
1648 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1649 ///< README: When tileIndex is not -1, this must be valid
1650 } ADDR_COMPUTE_SLICESWIZZLE_INPUT;
1651
1652 /**
1653 ****************************************************************************************************
1654 * ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1655 *
1656 * @brief
1657 * Output structure of AddrComputeSliceSwizzle
1658 ****************************************************************************************************
1659 */
1660 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1661 {
1662 UINT_32 size; ///< Size of this structure in bytes
1663
1664 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value
1665 } ADDR_COMPUTE_SLICESWIZZLE_OUTPUT;
1666
1667 /**
1668 ****************************************************************************************************
1669 * AddrComputeSliceSwizzle
1670 *
1671 * @brief
1672 * Extract Bank and Pipe swizzle from base256b
1673 * @return
1674 * ADDR_OK if no error
1675 ****************************************************************************************************
1676 */
1677 ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
1678 ADDR_HANDLE hLib,
1679 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
1680 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut);
1681
1682 /**
1683 ****************************************************************************************************
1684 * AddrSwizzleGenOption
1685 *
1686 * @brief
1687 * Which swizzle generating options: legacy or linear
1688 ****************************************************************************************************
1689 */
1690 typedef enum _AddrSwizzleGenOption
1691 {
1692 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle
1693 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle
1694 } AddrSwizzleGenOption;
1695
1696 /**
1697 ****************************************************************************************************
1698 * AddrSwizzleOption
1699 *
1700 * @brief
1701 * Controls how swizzle is generated
1702 ****************************************************************************************************
1703 */
1704 typedef union _ADDR_SWIZZLE_OPTION
1705 {
1706 struct
1707 {
1708 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption
1709 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits
1710 UINT_32 reserved :30; ///< Reserved bits
1711 };
1712
1713 UINT_32 value;
1714
1715 } ADDR_SWIZZLE_OPTION;
1716
1717 /**
1718 ****************************************************************************************************
1719 * ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1720 *
1721 * @brief
1722 * Input structure of AddrComputeBaseSwizzle
1723 ****************************************************************************************************
1724 */
1725 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1726 {
1727 UINT_32 size; ///< Size of this structure in bytes
1728
1729 ADDR_SWIZZLE_OPTION option; ///< Swizzle option
1730 UINT_32 surfIndex; ///< Index of this surface type
1731 AddrTileMode tileMode; ///< Tile Mode
1732
1733 /// r800 and later HWL parameters
1734 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1735
1736 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1737 /// while the global useTileIndex is set to 1
1738 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1739 ///< README: When tileIndex is not -1, this must be valid
1740 } ADDR_COMPUTE_BASE_SWIZZLE_INPUT;
1741
1742 /**
1743 ****************************************************************************************************
1744 * ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1745 *
1746 * @brief
1747 * Output structure of AddrComputeBaseSwizzle
1748 ****************************************************************************************************
1749 */
1750 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1751 {
1752 UINT_32 size; ///< Size of this structure in bytes
1753
1754 UINT_32 tileSwizzle; ///< Combined swizzle
1755 } ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT;
1756
1757 /**
1758 ****************************************************************************************************
1759 * AddrComputeBaseSwizzle
1760 *
1761 * @brief
1762 * Return a Combined Bank and Pipe swizzle base on surface based on surface type/index
1763 * @return
1764 * ADDR_OK if no error
1765 ****************************************************************************************************
1766 */
1767 ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
1768 ADDR_HANDLE hLib,
1769 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
1770 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut);
1771
1772 /**
1773 ****************************************************************************************************
1774 * ELEM_GETEXPORTNORM_INPUT
1775 *
1776 * @brief
1777 * Input structure for ElemGetExportNorm
1778 *
1779 ****************************************************************************************************
1780 */
1781 typedef struct _ELEM_GETEXPORTNORM_INPUT
1782 {
1783 UINT_32 size; ///< Size of this structure in bytes
1784
1785 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat
1786 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType
1787 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap
1788 UINT_32 numSamples; ///< Number of samples
1789 } ELEM_GETEXPORTNORM_INPUT;
1790
1791 /**
1792 ****************************************************************************************************
1793 * ElemGetExportNorm
1794 *
1795 * @brief
1796 * Helper function to check one format can be EXPORT_NUM, which is a register
1797 * CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600
1798 * family
1799 * @note
1800 * The implementation is only for r600.
1801 * 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two
1802 * clocks per export)
1803 * 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one
1804 * clock per export)
1805 *
1806 ****************************************************************************************************
1807 */
1808 BOOL_32 ADDR_API ElemGetExportNorm(
1809 ADDR_HANDLE hLib,
1810 const ELEM_GETEXPORTNORM_INPUT* pIn);
1811
1812 /**
1813 ****************************************************************************************************
1814 * ELEM_FLT32TODEPTHPIXEL_INPUT
1815 *
1816 * @brief
1817 * Input structure for addrFlt32ToDepthPixel
1818 *
1819 ****************************************************************************************************
1820 */
1821 typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT
1822 {
1823 UINT_32 size; ///< Size of this structure in bytes
1824
1825 AddrDepthFormat format; ///< Depth buffer format
1826 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil)
1827 } ELEM_FLT32TODEPTHPIXEL_INPUT;
1828
1829 /**
1830 ****************************************************************************************************
1831 * ELEM_FLT32TODEPTHPIXEL_INPUT
1832 *
1833 * @brief
1834 * Output structure for ElemFlt32ToDepthPixel
1835 *
1836 ****************************************************************************************************
1837 */
1838 typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT
1839 {
1840 UINT_32 size; ///< Size of this structure in bytes
1841
1842 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer.
1843 /// Client must provide enough storage for this type.
1844 UINT_32 depthBase; ///< Tile base in bits for depth bits
1845 UINT_32 stencilBase; ///< Tile base in bits for stencil bits
1846 UINT_32 depthBits; ///< Bits for depth
1847 UINT_32 stencilBits; ///< Bits for stencil
1848 } ELEM_FLT32TODEPTHPIXEL_OUTPUT;
1849
1850 /**
1851 ****************************************************************************************************
1852 * ElemFlt32ToDepthPixel
1853 *
1854 * @brief
1855 * Convert a FLT_32 value to a depth/stencil pixel value
1856 *
1857 * @return
1858 * Return code
1859 *
1860 ****************************************************************************************************
1861 */
1862 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
1863 ADDR_HANDLE hLib,
1864 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
1865 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut);
1866
1867 /**
1868 ****************************************************************************************************
1869 * ELEM_FLT32TOCOLORPIXEL_INPUT
1870 *
1871 * @brief
1872 * Input structure for addrFlt32ToColorPixel
1873 *
1874 ****************************************************************************************************
1875 */
1876 typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT
1877 {
1878 UINT_32 size; ///< Size of this structure in bytes
1879
1880 AddrColorFormat format; ///< Color buffer format
1881 AddrSurfaceNumber surfNum; ///< Surface number
1882 AddrSurfaceSwap surfSwap; ///< Surface swap
1883 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a)
1884 } ELEM_FLT32TOCOLORPIXEL_INPUT;
1885
1886 /**
1887 ****************************************************************************************************
1888 * ELEM_FLT32TOCOLORPIXEL_INPUT
1889 *
1890 * @brief
1891 * Output structure for ElemFlt32ToColorPixel
1892 *
1893 ****************************************************************************************************
1894 */
1895 typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT
1896 {
1897 UINT_32 size; ///< Size of this structure in bytes
1898
1899 UINT_8* pPixel; ///< Real color value. Same data type as color buffer.
1900 /// Client must provide enough storage for this type.
1901 } ELEM_FLT32TOCOLORPIXEL_OUTPUT;
1902
1903 /**
1904 ****************************************************************************************************
1905 * ElemFlt32ToColorPixel
1906 *
1907 * @brief
1908 * Convert a FLT_32 value to a red/green/blue/alpha pixel value
1909 *
1910 * @return
1911 * Return code
1912 *
1913 ****************************************************************************************************
1914 */
1915 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
1916 ADDR_HANDLE hLib,
1917 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
1918 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut);
1919
1920 /**
1921 ****************************************************************************************************
1922 * ElemSize
1923 *
1924 * @brief
1925 * Get bits-per-element for specified format
1926 *
1927 * @return
1928 * Bits-per-element of specified format
1929 *
1930 ****************************************************************************************************
1931 */
1932 UINT_32 ADDR_API ElemSize(
1933 ADDR_HANDLE hLib,
1934 AddrFormat format);
1935
1936 /**
1937 ****************************************************************************************************
1938 * ADDR_CONVERT_TILEINFOTOHW_INPUT
1939 *
1940 * @brief
1941 * Input structure for AddrConvertTileInfoToHW
1942 * @note
1943 * When reverse is TRUE, indices are igonred
1944 ****************************************************************************************************
1945 */
1946 typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT
1947 {
1948 UINT_32 size; ///< Size of this structure in bytes
1949 BOOL_32 reverse; ///< Convert control flag.
1950 /// FALSE: convert from real value to HW value;
1951 /// TRUE: convert from HW value to real value.
1952
1953 /// r800 and later HWL parameters
1954 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value
1955
1956 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1957 /// while the global useTileIndex is set to 1
1958 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1959 ///< README: When tileIndex is not -1, this must be valid
1960 UINT_32 bpp; ///< Bits per pixel
1961 } ADDR_CONVERT_TILEINFOTOHW_INPUT;
1962
1963 /**
1964 ****************************************************************************************************
1965 * ADDR_CONVERT_TILEINFOTOHW_OUTPUT
1966 *
1967 * @brief
1968 * Output structure for AddrConvertTileInfoToHW
1969 ****************************************************************************************************
1970 */
1971 typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT
1972 {
1973 UINT_32 size; ///< Size of this structure in bytes
1974
1975 /// r800 and later HWL parameters
1976 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value
1977
1978 } ADDR_CONVERT_TILEINFOTOHW_OUTPUT;
1979
1980 /**
1981 ****************************************************************************************************
1982 * AddrConvertTileInfoToHW
1983 *
1984 * @brief
1985 * Convert tile info from real value to hardware register value
1986 ****************************************************************************************************
1987 */
1988 ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
1989 ADDR_HANDLE hLib,
1990 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
1991 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut);
1992
1993 /**
1994 ****************************************************************************************************
1995 * ADDR_CONVERT_TILEINDEX_INPUT
1996 *
1997 * @brief
1998 * Input structure for AddrConvertTileIndex
1999 ****************************************************************************************************
2000 */
2001 typedef struct _ADDR_CONVERT_TILEINDEX_INPUT
2002 {
2003 UINT_32 size; ///< Size of this structure in bytes
2004
2005 INT_32 tileIndex; ///< Tile index
2006 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2007 UINT_32 bpp; ///< Bits per pixel
2008 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2009 } ADDR_CONVERT_TILEINDEX_INPUT;
2010
2011 /**
2012 ****************************************************************************************************
2013 * ADDR_CONVERT_TILEINDEX_OUTPUT
2014 *
2015 * @brief
2016 * Output structure for AddrConvertTileIndex
2017 ****************************************************************************************************
2018 */
2019 typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT
2020 {
2021 UINT_32 size; ///< Size of this structure in bytes
2022
2023 AddrTileMode tileMode; ///< Tile mode
2024 AddrTileType tileType; ///< Tile type
2025 ADDR_TILEINFO* pTileInfo; ///< Tile info
2026
2027 } ADDR_CONVERT_TILEINDEX_OUTPUT;
2028
2029 /**
2030 ****************************************************************************************************
2031 * AddrConvertTileIndex
2032 *
2033 * @brief
2034 * Convert tile index to tile mode/type/info
2035 ****************************************************************************************************
2036 */
2037 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex(
2038 ADDR_HANDLE hLib,
2039 const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
2040 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
2041
2042 /**
2043 ****************************************************************************************************
2044 * ADDR_GET_MACROMODEINDEX_INPUT
2045 *
2046 * @brief
2047 * Input structure for AddrGetMacroModeIndex
2048 ****************************************************************************************************
2049 */
2050 typedef struct _ADDR_GET_MACROMODEINDEX_INPUT
2051 {
2052 UINT_32 size; ///< Size of this structure in bytes
2053 ADDR_SURFACE_FLAGS flags; ///< Surface flag
2054 INT_32 tileIndex; ///< Tile index
2055 UINT_32 bpp; ///< Bits per pixel
2056 UINT_32 numFrags; ///< Number of color fragments
2057 } ADDR_GET_MACROMODEINDEX_INPUT;
2058
2059 /**
2060 ****************************************************************************************************
2061 * ADDR_GET_MACROMODEINDEX_OUTPUT
2062 *
2063 * @brief
2064 * Output structure for AddrGetMacroModeIndex
2065 ****************************************************************************************************
2066 */
2067 typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT
2068 {
2069 UINT_32 size; ///< Size of this structure in bytes
2070 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2071 } ADDR_GET_MACROMODEINDEX_OUTPUT;
2072
2073 /**
2074 ****************************************************************************************************
2075 * AddrGetMacroModeIndex
2076 *
2077 * @brief
2078 * Get macro mode index based on input parameters
2079 ****************************************************************************************************
2080 */
2081 ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex(
2082 ADDR_HANDLE hLib,
2083 const ADDR_GET_MACROMODEINDEX_INPUT* pIn,
2084 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut);
2085
2086 /**
2087 ****************************************************************************************************
2088 * ADDR_CONVERT_TILEINDEX1_INPUT
2089 *
2090 * @brief
2091 * Input structure for AddrConvertTileIndex1 (without macro mode index)
2092 ****************************************************************************************************
2093 */
2094 typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT
2095 {
2096 UINT_32 size; ///< Size of this structure in bytes
2097
2098 INT_32 tileIndex; ///< Tile index
2099 UINT_32 bpp; ///< Bits per pixel
2100 UINT_32 numSamples; ///< Number of samples
2101 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2102 } ADDR_CONVERT_TILEINDEX1_INPUT;
2103
2104 /**
2105 ****************************************************************************************************
2106 * AddrConvertTileIndex1
2107 *
2108 * @brief
2109 * Convert tile index to tile mode/type/info
2110 ****************************************************************************************************
2111 */
2112 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
2113 ADDR_HANDLE hLib,
2114 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
2115 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
2116
2117 /**
2118 ****************************************************************************************************
2119 * ADDR_GET_TILEINDEX_INPUT
2120 *
2121 * @brief
2122 * Input structure for AddrGetTileIndex
2123 ****************************************************************************************************
2124 */
2125 typedef struct _ADDR_GET_TILEINDEX_INPUT
2126 {
2127 UINT_32 size; ///< Size of this structure in bytes
2128
2129 AddrTileMode tileMode; ///< Tile mode
2130 AddrTileType tileType; ///< Tile-type: disp/non-disp/...
2131 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D
2132 } ADDR_GET_TILEINDEX_INPUT;
2133
2134 /**
2135 ****************************************************************************************************
2136 * ADDR_GET_TILEINDEX_OUTPUT
2137 *
2138 * @brief
2139 * Output structure for AddrGetTileIndex
2140 ****************************************************************************************************
2141 */
2142 typedef struct _ADDR_GET_TILEINDEX_OUTPUT
2143 {
2144 UINT_32 size; ///< Size of this structure in bytes
2145
2146 INT_32 index; ///< index in table
2147 } ADDR_GET_TILEINDEX_OUTPUT;
2148
2149 /**
2150 ****************************************************************************************************
2151 * AddrGetTileIndex
2152 *
2153 * @brief
2154 * Get the tiling mode index in table
2155 ****************************************************************************************************
2156 */
2157 ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
2158 ADDR_HANDLE hLib,
2159 const ADDR_GET_TILEINDEX_INPUT* pIn,
2160 ADDR_GET_TILEINDEX_OUTPUT* pOut);
2161
2162 /**
2163 ****************************************************************************************************
2164 * ADDR_PRT_INFO_INPUT
2165 *
2166 * @brief
2167 * Input structure for AddrComputePrtInfo
2168 ****************************************************************************************************
2169 */
2170 typedef struct _ADDR_PRT_INFO_INPUT
2171 {
2172 AddrFormat format; ///< Surface format
2173 UINT_32 baseMipWidth; ///< Base mipmap width
2174 UINT_32 baseMipHeight; ///< Base mipmap height
2175 UINT_32 baseMipDepth; ///< Base mipmap depth
2176 UINT_32 numFrags; ///< Number of fragments,
2177 } ADDR_PRT_INFO_INPUT;
2178
2179 /**
2180 ****************************************************************************************************
2181 * ADDR_PRT_INFO_OUTPUT
2182 *
2183 * @brief
2184 * Input structure for AddrComputePrtInfo
2185 ****************************************************************************************************
2186 */
2187 typedef struct _ADDR_PRT_INFO_OUTPUT
2188 {
2189 UINT_32 prtTileWidth;
2190 UINT_32 prtTileHeight;
2191 } ADDR_PRT_INFO_OUTPUT;
2192
2193 /**
2194 ****************************************************************************************************
2195 * AddrComputePrtInfo
2196 *
2197 * @brief
2198 * Compute prt surface related information
2199 ****************************************************************************************************
2200 */
2201 ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
2202 ADDR_HANDLE hLib,
2203 const ADDR_PRT_INFO_INPUT* pIn,
2204 ADDR_PRT_INFO_OUTPUT* pOut);
2205
2206 ////////////////////////////////////////////////////////////////////////////////////////////////////
2207 // DCC key functions
2208 ////////////////////////////////////////////////////////////////////////////////////////////////////
2209
2210 /**
2211 ****************************************************************************************************
2212 * _ADDR_COMPUTE_DCCINFO_INPUT
2213 *
2214 * @brief
2215 * Input structure of AddrComputeDccInfo
2216 ****************************************************************************************************
2217 */
2218 typedef struct _ADDR_COMPUTE_DCCINFO_INPUT
2219 {
2220 UINT_32 size; ///< Size of this structure in bytes
2221 UINT_32 bpp; ///< BitPP of color surface
2222 UINT_32 numSamples; ///< Sample number of color surface
2223 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound
2224 AddrTileMode tileMode; ///< Tile mode of color surface
2225 ADDR_TILEINFO tileInfo; ///< Tile info of color surface
2226 UINT_32 tileSwizzle; ///< Tile swizzle
2227 INT_32 tileIndex; ///< Tile index of color surface,
2228 ///< MUST be -1 if you don't want to use it
2229 ///< while the global useTileIndex is set to 1
2230 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2231 ///< README: When tileIndex is not -1, this must be valid
2232 } ADDR_COMPUTE_DCCINFO_INPUT;
2233
2234 /**
2235 ****************************************************************************************************
2236 * ADDR_COMPUTE_DCCINFO_OUTPUT
2237 *
2238 * @brief
2239 * Output structure of AddrComputeDccInfo
2240 ****************************************************************************************************
2241 */
2242 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
2243 {
2244 UINT_32 size; ///< Size of this structure in bytes
2245 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
2246 UINT_64 dccRamSize; ///< Size of dcc key
2247 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared
2248 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
2249 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned
2250 } ADDR_COMPUTE_DCCINFO_OUTPUT;
2251
2252 /**
2253 ****************************************************************************************************
2254 * AddrComputeDccInfo
2255 *
2256 * @brief
2257 * Compute DCC key size, base alignment
2258 * info
2259 ****************************************************************************************************
2260 */
2261 ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
2262 ADDR_HANDLE hLib,
2263 const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
2264 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);
2265
2266 /**
2267 ****************************************************************************************************
2268 * ADDR_GET_MAX_ALINGMENTS_OUTPUT
2269 *
2270 * @brief
2271 * Output structure of AddrGetMaxAlignments
2272 ****************************************************************************************************
2273 */
2274 typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
2275 {
2276 UINT_32 size; ///< Size of this structure in bytes
2277 UINT_32 baseAlign; ///< Maximum base alignment in bytes
2278 } ADDR_GET_MAX_ALINGMENTS_OUTPUT;
2279
2280 /**
2281 ****************************************************************************************************
2282 * AddrGetMaxAlignments
2283 *
2284 * @brief
2285 * Gets maximnum alignments
2286 ****************************************************************************************************
2287 */
2288 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
2289 ADDR_HANDLE hLib,
2290 ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
2291
2292 /**
2293 ****************************************************************************************************
2294 * AddrGetMaxMetaAlignments
2295 *
2296 * @brief
2297 * Gets maximnum alignments for metadata
2298 ****************************************************************************************************
2299 */
2300 ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
2301 ADDR_HANDLE hLib,
2302 ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
2303
2304 /**
2305 ****************************************************************************************************
2306 * Address library interface version 2
2307 * available from Gfx9 hardware
2308 ****************************************************************************************************
2309 * Addr2ComputeSurfaceInfo()
2310 * Addr2ComputeSurfaceAddrFromCoord()
2311 * Addr2ComputeSurfaceCoordFromAddr()
2312
2313 * Addr2ComputeHtileInfo()
2314 * Addr2ComputeHtileAddrFromCoord()
2315 * Addr2ComputeHtileCoordFromAddr()
2316 *
2317 * Addr2ComputeCmaskInfo()
2318 * Addr2ComputeCmaskAddrFromCoord()
2319 * Addr2ComputeCmaskCoordFromAddr()
2320 *
2321 * Addr2ComputeFmaskInfo()
2322 * Addr2ComputeFmaskAddrFromCoord()
2323 * Addr2ComputeFmaskCoordFromAddr()
2324 *
2325 * Addr2ComputeDccInfo()
2326 *
2327 **/
2328
2329 ////////////////////////////////////////////////////////////////////////////////////////////////////
2330 // Surface functions for Gfx9
2331 ////////////////////////////////////////////////////////////////////////////////////////////////////
2332
2333 /**
2334 ****************************************************************************************************
2335 * ADDR2_SURFACE_FLAGS
2336 *
2337 * @brief
2338 * Surface flags
2339 ****************************************************************************************************
2340 */
2341 typedef union _ADDR2_SURFACE_FLAGS
2342 {
2343 struct
2344 {
2345 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV
2346 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV
2347 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV
2348 UINT_32 fmask : 1; ///< This is an fmask surface
2349 UINT_32 overlay : 1; ///< This is an overlay surface
2350 UINT_32 display : 1; ///< This resource is displable, can be used with DRV
2351 UINT_32 prt : 1; ///< This is a partially resident texture
2352 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface
2353 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
2354 UINT_32 texture : 1; ///< This resource can be used with SRV
2355 UINT_32 unordered : 1; ///< This resource can be used with UAV
2356 UINT_32 rotated : 1; ///< This resource is rotated and displable
2357 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible
2358 UINT_32 opt4space : 1; ///< This resource should be optimized for space
2359 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment
2360 UINT_32 noMetadata : 1; ///< This resource has no metadata
2361 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata
2362 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata
2363 UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array
2364 UINT_32 reserved : 13; ///< Reserved bits
2365 };
2366
2367 UINT_32 value;
2368 } ADDR2_SURFACE_FLAGS;
2369
2370 /**
2371 ****************************************************************************************************
2372 * ADDR2_COMPUTE_SURFACE_INFO_INPUT
2373 *
2374 * @brief
2375 * Input structure for Addr2ComputeSurfaceInfo
2376 ****************************************************************************************************
2377 */
2378 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT
2379 {
2380 UINT_32 size; ///< Size of this structure in bytes
2381
2382 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2383 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9
2384 AddrResourceType resourceType; ///< Surface type
2385 AddrFormat format; ///< Surface format
2386 UINT_32 bpp; ///< bits per pixel
2387 UINT_32 width; ///< Width (of mip0), in pixels
2388 UINT_32 height; ///< Height (of mip0), in pixels
2389 UINT_32 numSlices; ///< Number surface slice/depth (of mip0),
2390 UINT_32 numMipLevels; ///< Total mipmap levels.
2391 UINT_32 numSamples; ///< Number of samples
2392 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2393 /// number of samples for normal AA; Set it to the
2394 /// number of fragments for EQAA
2395 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2396 UINT_32 sliceAlign; ///< Required slice size in bytes
2397 } ADDR2_COMPUTE_SURFACE_INFO_INPUT;
2398
2399 /**
2400 ****************************************************************************************************
2401 * ADDR2_MIP_INFO
2402 *
2403 * @brief
2404 * Structure that contains information for mip level
2405 *
2406 ****************************************************************************************************
2407 */
2408 typedef struct _ADDR2_MIP_INFO
2409 {
2410 UINT_32 pitch; ///< Pitch in elements
2411 UINT_32 height; ///< Padded height in elements
2412 UINT_32 depth; ///< Padded depth
2413 UINT_32 pixelPitch; ///< Pitch in pixels
2414 UINT_32 pixelHeight; ///< Padded height in pixels
2415 UINT_32 equationIndex; ///< Equation index in the equation table
2416 UINT_64 offset; ///< Offset in bytes from mip base, should only be used
2417 ///< to setup vam surface descriptor, can't be used
2418 ///< to setup swizzle pattern
2419 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base
2420 UINT_32 mipTailOffset; ///< mip tail offset in bytes
2421 UINT_32 mipTailCoordX; ///< mip tail coord x
2422 UINT_32 mipTailCoordY; ///< mip tail coord y
2423 UINT_32 mipTailCoordZ; ///< mip tail coord z
2424 } ADDR2_MIP_INFO;
2425
2426 /**
2427 ****************************************************************************************************
2428 * ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2429 *
2430 * @brief
2431 * Output structure for Addr2ComputeSurfInfo
2432 * @note
2433 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
2434 Pixel: Original pixel
2435 ****************************************************************************************************
2436 */
2437 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2438 {
2439 UINT_32 size; ///< Size of this structure in bytes
2440
2441 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats)
2442 UINT_32 height; ///< Padded height (of mip0) in elements
2443 UINT_32 numSlices; ///< Padded depth for 3d resource
2444 ///< or padded number of slices for 2d array resource
2445 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements
2446 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements
2447 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain)
2448 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes
2449 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes
2450 UINT_32 baseAlign; ///< Base address alignment
2451 UINT_32 bpp; ///< Bits per elements
2452 /// (e.g. blocks for BCn, 1/3 for 96bit)
2453 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels
2454 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels
2455 UINT_32 pixelPitch; ///< Pitch in original pixels
2456 UINT_32 pixelHeight; ///< Height in original pixels
2457 UINT_32 pixelBits; ///< Original bits per pixel, passed from input
2458
2459 UINT_32 blockWidth; ///< Width in element inside one block
2460 UINT_32 blockHeight; ///< Height in element inside one block
2461 UINT_32 blockSlices; ///< Slice number inside one block
2462 ///< Prt tile is one block, its width/height/slice
2463 ///< equals to blcok width/height/slice
2464
2465 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register
2466 /// Stereo info
2467 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE
2468 /// Mip info
2469 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array
2470 /// if it is not NULL, the array is assumed to
2471 /// contain numMipLevels entries
2472
2473 UINT_32 equationIndex; ///< Equation index in the equation table of mip0
2474 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block
2475 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip
2476 /// in tail, it will be set to number of mip levels
2477 } ADDR2_COMPUTE_SURFACE_INFO_OUTPUT;
2478
2479 /**
2480 ****************************************************************************************************
2481 * Addr2ComputeSurfaceInfo
2482 *
2483 * @brief
2484 * Compute surface width/height/slices/alignments and suitable tiling mode
2485 ****************************************************************************************************
2486 */
2487 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
2488 ADDR_HANDLE hLib,
2489 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
2490 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
2491
2492 /**
2493 ****************************************************************************************************
2494 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2495 *
2496 * @brief
2497 * Input structure for Addr2ComputeSurfaceAddrFromCoord
2498 ****************************************************************************************************
2499 */
2500 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2501 {
2502 UINT_32 size; ///< Size of this structure in bytes
2503
2504 UINT_32 x; ///< X coordinate
2505 UINT_32 y; ///< Y coordinate
2506 UINT_32 slice; ///< Slice index
2507 UINT_32 sample; ///< Sample index, use fragment index for EQAA
2508 UINT_32 mipId; ///< the mip ID in mip chain
2509
2510 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9
2511 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2512 AddrResourceType resourceType; ///< Surface type
2513 UINT_32 bpp; ///< Bits per pixel
2514 UINT_32 unalignedWidth; ///< Surface original width (of mip0)
2515 UINT_32 unalignedHeight; ///< Surface original height (of mip0)
2516 UINT_32 numSlices; ///< Surface original slices (of mip0)
2517 UINT_32 numMipLevels; ///< Total mipmap levels
2518 UINT_32 numSamples; ///< Number of samples
2519 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2520 /// number of samples for normal AA; Set it to the
2521 /// number of fragments for EQAA
2522
2523 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
2524 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2525 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
2526
2527 /**
2528 ****************************************************************************************************
2529 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2530 *
2531 * @brief
2532 * Output structure for Addr2ComputeSurfaceAddrFromCoord
2533 ****************************************************************************************************
2534 */
2535 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2536 {
2537 UINT_32 size; ///< Size of this structure in bytes
2538
2539 UINT_64 addr; ///< Byte address
2540 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.
2541 /// For surface bpp < 8, e.g. FMT_1.
2542 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)
2543 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
2544
2545 /**
2546 ****************************************************************************************************
2547 * Addr2ComputeSurfaceAddrFromCoord
2548 *
2549 * @brief
2550 * Compute surface address from a given coordinate.
2551 ****************************************************************************************************
2552 */
2553 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
2554 ADDR_HANDLE hLib,
2555 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
2556 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
2557
2558 /**
2559 ****************************************************************************************************
2560 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2561 *
2562 * @brief
2563 * Input structure for Addr2ComputeSurfaceCoordFromAddr
2564 ****************************************************************************************************
2565 */
2566 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2567 {
2568 UINT_32 size; ///< Size of this structure in bytes
2569
2570 UINT_64 addr; ///< Address in bytes
2571 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,
2572 /// e.g. FMT_1;
2573
2574 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9
2575 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2576 AddrResourceType resourceType; ///< Surface type
2577 UINT_32 bpp; ///< Bits per pixel
2578 UINT_32 unalignedWidth; ///< Surface original width (of mip0)
2579 UINT_32 unalignedHeight; ///< Surface original height (of mip0)
2580 UINT_32 numSlices; ///< Surface original slices (of mip0)
2581 UINT_32 numMipLevels; ///< Total mipmap levels.
2582 UINT_32 numSamples; ///< Number of samples
2583 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2584 /// number of samples for normal AA; Set it to the
2585 /// number of fragments for EQAA
2586
2587 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
2588 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2589 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
2590
2591 /**
2592 ****************************************************************************************************
2593 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2594 *
2595 * @brief
2596 * Output structure for Addr2ComputeSurfaceCoordFromAddr
2597 ****************************************************************************************************
2598 */
2599 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2600 {
2601 UINT_32 size; ///< Size of this structure in bytes
2602
2603 UINT_32 x; ///< X coordinate
2604 UINT_32 y; ///< Y coordinate
2605 UINT_32 slice; ///< Index of slices
2606 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
2607 UINT_32 mipId; ///< mipmap level id
2608 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
2609
2610 /**
2611 ****************************************************************************************************
2612 * Addr2ComputeSurfaceCoordFromAddr
2613 *
2614 * @brief
2615 * Compute coordinate from a given surface address
2616 ****************************************************************************************************
2617 */
2618 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
2619 ADDR_HANDLE hLib,
2620 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
2621 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
2622
2623 ////////////////////////////////////////////////////////////////////////////////////////////////////
2624 // HTile functions for Gfx9
2625 ////////////////////////////////////////////////////////////////////////////////////////////////////
2626
2627 /**
2628 ****************************************************************************************************
2629 * ADDR2_META_FLAGS
2630 *
2631 * @brief
2632 * Metadata flags
2633 ****************************************************************************************************
2634 */
2635 typedef union _ADDR2_META_FLAGS
2636 {
2637 struct
2638 {
2639 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned
2640 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned
2641 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this!
2642 UINT_32 reserved : 29; ///< Reserved bits
2643 };
2644
2645 UINT_32 value;
2646 } ADDR2_META_FLAGS;
2647
2648 /**
2649 ****************************************************************************************************
2650 * ADDR2_META_MIP_INFO
2651 *
2652 * @brief
2653 * Structure to store per mip metadata information
2654 ****************************************************************************************************
2655 */
2656 typedef struct _ADDR2_META_MIP_INFO
2657 {
2658 BOOL_32 inMiptail;
2659 union
2660 {
2661 struct
2662 {
2663 UINT_32 startX;
2664 UINT_32 startY;
2665 UINT_32 startZ;
2666 UINT_32 width;
2667 UINT_32 height;
2668 UINT_32 depth;
2669 };
2670
2671 struct
2672 {
2673 UINT_32 offset; ///< Metadata offset within one slice,
2674 /// the thickness of a slice is meta block depth.
2675 UINT_32 sliceSize; ///< Metadata size within one slice,
2676 /// the thickness of a slice is meta block depth.
2677 };
2678 };
2679 } ADDR2_META_MIP_INFO;
2680
2681 /**
2682 ****************************************************************************************************
2683 * ADDR2_COMPUTE_HTILE_INFO_INPUT
2684 *
2685 * @brief
2686 * Input structure of Addr2ComputeHtileInfo
2687 ****************************************************************************************************
2688 */
2689 typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
2690 {
2691 UINT_32 size; ///< Size of this structure in bytes
2692
2693 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2694 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags
2695 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2696 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2697 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2698 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)
2699 UINT_32 numMipLevels; ///< Total mipmap levels of color surface
2700 UINT_32 firstMipIdInTail; /// Id of the first mip in tail,
2701 /// if no mip is in tail, it should be set to
2702 /// number of mip levels
2703 } ADDR2_COMPUTE_HTILE_INFO_INPUT;
2704
2705 /**
2706 ****************************************************************************************************
2707 * ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2708 *
2709 * @brief
2710 * Output structure of Addr2ComputeHtileInfo
2711 ****************************************************************************************************
2712 */
2713 typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2714 {
2715 UINT_32 size; ///< Size of this structure in bytes
2716
2717 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this
2718 /// HTile buffer. This might be larger than original depth
2719 /// buffer pitch when called with an unaligned pitch.
2720 UINT_32 height; ///< Height in pixels, as above
2721 UINT_32 baseAlign; ///< Base alignment
2722 UINT_32 sliceSize; ///< Slice size, in bytes.
2723 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes
2724 UINT_32 metaBlkWidth; ///< Meta block width
2725 UINT_32 metaBlkHeight; ///< Meta block height
2726 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
2727
2728 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information
2729 } ADDR2_COMPUTE_HTILE_INFO_OUTPUT;
2730
2731 /**
2732 ****************************************************************************************************
2733 * Addr2ComputeHtileInfo
2734 *
2735 * @brief
2736 * Compute Htile pitch, height, base alignment and size in bytes
2737 ****************************************************************************************************
2738 */
2739 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
2740 ADDR_HANDLE hLib,
2741 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
2742 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut);
2743
2744 /**
2745 ****************************************************************************************************
2746 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2747 *
2748 * @brief
2749 * Input structure for Addr2ComputeHtileAddrFromCoord
2750 ****************************************************************************************************
2751 */
2752 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2753 {
2754 UINT_32 size; ///< Size of this structure in bytes
2755
2756 UINT_32 x; ///< X coordinate
2757 UINT_32 y; ///< Y coordinate
2758 UINT_32 slice; ///< Index of slices
2759 UINT_32 mipId; ///< mipmap level id
2760
2761 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2762 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags
2763 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2764 UINT_32 bpp; ///< Depth surface bits per pixel
2765 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2766 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2767 UINT_32 numSlices; ///< Depth surface original depth (of mip0)
2768 UINT_32 numMipLevels; ///< Depth surface total mipmap levels
2769 UINT_32 numSamples; ///< Depth surface number of samples
2770 UINT_32 pipeXor; ///< Pipe xor setting
2771 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
2772
2773 /**
2774 ****************************************************************************************************
2775 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2776 *
2777 * @brief
2778 * Output structure for Addr2ComputeHtileAddrFromCoord
2779 ****************************************************************************************************
2780 */
2781 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2782 {
2783 UINT_32 size; ///< Size of this structure in bytes
2784
2785 UINT_64 addr; ///< Address in bytes
2786 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
2787
2788 /**
2789 ****************************************************************************************************
2790 * Addr2ComputeHtileAddrFromCoord
2791 *
2792 * @brief
2793 * Compute Htile address according to coordinates (of depth buffer)
2794 ****************************************************************************************************
2795 */
2796 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
2797 ADDR_HANDLE hLib,
2798 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
2799 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
2800
2801 /**
2802 ****************************************************************************************************
2803 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2804 *
2805 * @brief
2806 * Input structure for Addr2ComputeHtileCoordFromAddr
2807 ****************************************************************************************************
2808 */
2809 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2810 {
2811 UINT_32 size; ///< Size of this structure in bytes
2812
2813 UINT_64 addr; ///< Address
2814
2815 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2816 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags
2817 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2818 UINT_32 bpp; ///< Depth surface bits per pixel
2819 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2820 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2821 UINT_32 numSlices; ///< Depth surface original depth (of mip0)
2822 UINT_32 numMipLevels; ///< Depth surface total mipmap levels
2823 UINT_32 numSamples; ///< Depth surface number of samples
2824 UINT_32 pipeXor; ///< Pipe xor setting
2825 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT;
2826
2827 /**
2828 ****************************************************************************************************
2829 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2830 *
2831 * @brief
2832 * Output structure for Addr2ComputeHtileCoordFromAddr
2833 ****************************************************************************************************
2834 */
2835 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2836 {
2837 UINT_32 size; ///< Size of this structure in bytes
2838
2839 UINT_32 x; ///< X coordinate
2840 UINT_32 y; ///< Y coordinate
2841 UINT_32 slice; ///< Index of slices
2842 UINT_32 mipId; ///< mipmap level id
2843 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
2844
2845 /**
2846 ****************************************************************************************************
2847 * Addr2ComputeHtileCoordFromAddr
2848 *
2849 * @brief
2850 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to
2851 * Htile address
2852 ****************************************************************************************************
2853 */
2854 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
2855 ADDR_HANDLE hLib,
2856 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
2857 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
2858
2859 ////////////////////////////////////////////////////////////////////////////////////////////////////
2860 // C-mask functions for Gfx9
2861 ////////////////////////////////////////////////////////////////////////////////////////////////////
2862
2863 /**
2864 ****************************************************************************************************
2865 * ADDR2_COMPUTE_CMASK_INFO_INPUT
2866 *
2867 * @brief
2868 * Input structure of Addr2ComputeCmaskInfo
2869 ****************************************************************************************************
2870 */
2871 typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT
2872 {
2873 UINT_32 size; ///< Size of this structure in bytes
2874
2875 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
2876 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
2877 AddrResourceType resourceType; ///< Color surface type
2878 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
2879 UINT_32 unalignedWidth; ///< Color surface original width
2880 UINT_32 unalignedHeight; ///< Color surface original height
2881 UINT_32 numSlices; ///< Number of slices of color buffer
2882 } ADDR2_COMPUTE_CMASK_INFO_INPUT;
2883
2884 /**
2885 ****************************************************************************************************
2886 * ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2887 *
2888 * @brief
2889 * Output structure of Addr2ComputeCmaskInfo
2890 ****************************************************************************************************
2891 */
2892 typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2893 {
2894 UINT_32 size; ///< Size of this structure in bytes
2895
2896 UINT_32 pitch; ///< Pitch in pixels of color buffer which
2897 /// this Cmask matches. The size might be larger than
2898 /// original color buffer pitch when called with
2899 /// an unaligned pitch.
2900 UINT_32 height; ///< Height in pixels, as above
2901 UINT_32 baseAlign; ///< Base alignment
2902 UINT_32 sliceSize; ///< Slice size, in bytes.
2903 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer
2904 UINT_32 metaBlkWidth; ///< Meta block width
2905 UINT_32 metaBlkHeight; ///< Meta block height
2906
2907 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
2908 } ADDR2_COMPUTE_CMASK_INFO_OUTPUT;
2909
2910 /**
2911 ****************************************************************************************************
2912 * Addr2ComputeCmaskInfo
2913 *
2914 * @brief
2915 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer
2916 * info
2917 ****************************************************************************************************
2918 */
2919 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
2920 ADDR_HANDLE hLib,
2921 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
2922 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut);
2923
2924 /**
2925 ****************************************************************************************************
2926 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
2927 *
2928 * @brief
2929 * Input structure for Addr2ComputeCmaskAddrFromCoord
2930 *
2931 ****************************************************************************************************
2932 */
2933 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
2934 {
2935 UINT_32 size; ///< Size of this structure in bytes
2936
2937 UINT_32 x; ///< X coordinate
2938 UINT_32 y; ///< Y coordinate
2939 UINT_32 slice; ///< Index of slices
2940
2941 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
2942 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
2943 AddrResourceType resourceType; ///< Color surface type
2944 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
2945
2946 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
2947 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
2948 UINT_32 numSlices; ///< Color surface original slices (of mip0)
2949
2950 UINT_32 numSamples; ///< Color surfae sample number
2951 UINT_32 numFrags; ///< Color surface fragment number
2952
2953 UINT_32 pipeXor; ///< pipe Xor setting
2954 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
2955
2956 /**
2957 ****************************************************************************************************
2958 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
2959 *
2960 * @brief
2961 * Output structure for Addr2ComputeCmaskAddrFromCoord
2962 ****************************************************************************************************
2963 */
2964 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
2965 {
2966 UINT_32 size; ///< Size of this structure in bytes
2967
2968 UINT_64 addr; ///< CMASK address in bytes
2969 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
2970 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
2971
2972 /**
2973 ****************************************************************************************************
2974 * Addr2ComputeCmaskAddrFromCoord
2975 *
2976 * @brief
2977 * Compute Cmask address according to coordinates (of MSAA color buffer)
2978 ****************************************************************************************************
2979 */
2980 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
2981 ADDR_HANDLE hLib,
2982 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
2983 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
2984
2985 /**
2986 ****************************************************************************************************
2987 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
2988 *
2989 * @brief
2990 * Input structure for Addr2ComputeCmaskCoordFromAddr
2991 ****************************************************************************************************
2992 */
2993 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
2994 {
2995 UINT_32 size; ///< Size of this structure in bytes
2996
2997 UINT_64 addr; ///< CMASK address in bytes
2998 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
2999
3000 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
3001 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3002 AddrResourceType resourceType; ///< Color surface type
3003 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3004
3005 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3006 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3007 UINT_32 numSlices; ///< Color surface original slices (of mip0)
3008 UINT_32 numMipLevels; ///< Color surface total mipmap levels.
3009 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT;
3010
3011 /**
3012 ****************************************************************************************************
3013 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3014 *
3015 * @brief
3016 * Output structure for Addr2ComputeCmaskCoordFromAddr
3017 ****************************************************************************************************
3018 */
3019 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3020 {
3021 UINT_32 size; ///< Size of this structure in bytes
3022
3023 UINT_32 x; ///< X coordinate
3024 UINT_32 y; ///< Y coordinate
3025 UINT_32 slice; ///< Index of slices
3026 UINT_32 mipId; ///< mipmap level id
3027 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
3028
3029 /**
3030 ****************************************************************************************************
3031 * Addr2ComputeCmaskCoordFromAddr
3032 *
3033 * @brief
3034 * Compute coordinates within color buffer (1st pixel of a micro tile) according to
3035 * Cmask address
3036 ****************************************************************************************************
3037 */
3038 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
3039 ADDR_HANDLE hLib,
3040 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
3041 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
3042
3043 ////////////////////////////////////////////////////////////////////////////////////////////////////
3044 // F-mask functions for Gfx9
3045 ////////////////////////////////////////////////////////////////////////////////////////////////////
3046
3047 /**
3048 ****************************************************************************************************
3049 * ADDR2_FMASK_FLAGS
3050 *
3051 * @brief
3052 * FMASK flags
3053 ****************************************************************************************************
3054 */
3055 typedef union _ADDR2_FMASK_FLAGS
3056 {
3057 struct
3058 {
3059 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients
3060 /// by H/W clients. S/W should always set it to FALSE.
3061 UINT_32 reserved : 31; ///< Reserved for future use.
3062 };
3063
3064 UINT_32 value;
3065 } ADDR2_FMASK_FLAGS;
3066
3067 /**
3068 ****************************************************************************************************
3069 * ADDR2_COMPUTE_FMASK_INFO_INPUT
3070 *
3071 * @brief
3072 * Input structure for Addr2ComputeFmaskInfo
3073 ****************************************************************************************************
3074 */
3075 typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT
3076 {
3077 UINT_32 size; ///< Size of this structure in bytes
3078
3079 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3080 UINT_32 unalignedWidth; ///< Color surface original width
3081 UINT_32 unalignedHeight; ///< Color surface original height
3082 UINT_32 numSlices; ///< Number of slices/depth
3083 UINT_32 numSamples; ///< Number of samples
3084 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3085 /// number of samples for normal AA; Set it to the
3086 /// number of fragments for EQAA
3087 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3088 } ADDR2_COMPUTE_FMASK_INFO_INPUT;
3089
3090 /**
3091 ****************************************************************************************************
3092 * ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3093 *
3094 * @brief
3095 * Output structure for Addr2ComputeFmaskInfo
3096 ****************************************************************************************************
3097 */
3098 typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3099 {
3100 UINT_32 size; ///< Size of this structure in bytes
3101
3102 UINT_32 pitch; ///< Pitch of fmask in pixels
3103 UINT_32 height; ///< Height of fmask in pixels
3104 UINT_32 baseAlign; ///< Base alignment
3105 UINT_32 numSlices; ///< Slices of fmask
3106 UINT_32 fmaskBytes; ///< Size of fmask in bytes
3107 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes
3108 UINT_32 numSamples; ///< Number of samples
3109 UINT_32 sliceSize; ///< Size of slice in bytes
3110 } ADDR2_COMPUTE_FMASK_INFO_OUTPUT;
3111
3112 /**
3113 ****************************************************************************************************
3114 * Addr2ComputeFmaskInfo
3115 *
3116 * @brief
3117 * Compute Fmask pitch/height/slices/alignments and size in bytes
3118 ****************************************************************************************************
3119 */
3120 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
3121 ADDR_HANDLE hLib,
3122 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
3123 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
3124
3125 /**
3126 ****************************************************************************************************
3127 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3128 *
3129 * @brief
3130 * Input structure for Addr2ComputeFmaskAddrFromCoord
3131 ****************************************************************************************************
3132 */
3133 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3134 {
3135 UINT_32 size; ///< Size of this structure in bytes
3136
3137 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3138 UINT_32 x; ///< X coordinate
3139 UINT_32 y; ///< Y coordinate
3140 UINT_32 slice; ///< Slice index
3141 UINT_32 sample; ///< Sample index (fragment index for EQAA)
3142 UINT_32 plane; ///< Plane number
3143
3144 UINT_32 unalignedWidth; ///< Color surface original width
3145 UINT_32 unalignedHeight; ///< Color surface original height
3146 UINT_32 numSamples; ///< Number of samples
3147 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3148 /// number of samples for normal AA; Set it to the
3149 /// number of fragments for EQAA
3150 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
3151
3152 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3153 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
3154
3155 /**
3156 ****************************************************************************************************
3157 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3158 *
3159 * @brief
3160 * Output structure for Addr2ComputeFmaskAddrFromCoord
3161 ****************************************************************************************************
3162 */
3163 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3164 {
3165 UINT_32 size; ///< Size of this structure in bytes
3166
3167 UINT_64 addr; ///< Fmask address
3168 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.
3169 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
3170
3171 /**
3172 ****************************************************************************************************
3173 * Addr2ComputeFmaskAddrFromCoord
3174 *
3175 * @brief
3176 * Compute Fmask address according to coordinates (x,y,slice,sample,plane)
3177 ****************************************************************************************************
3178 */
3179 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
3180 ADDR_HANDLE hLib,
3181 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
3182 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
3183
3184 /**
3185 ****************************************************************************************************
3186 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3187 *
3188 * @brief
3189 * Input structure for Addr2ComputeFmaskCoordFromAddr
3190 ****************************************************************************************************
3191 */
3192 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3193 {
3194 UINT_32 size; ///< Size of this structure in bytes
3195
3196 UINT_64 addr; ///< Address
3197 UINT_32 bitPosition; ///< Bit position within addr, 0-7.
3198 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3199
3200 UINT_32 unalignedWidth; ///< Color surface original width
3201 UINT_32 unalignedHeight; ///< Color surface original height
3202 UINT_32 numSamples; ///< Number of samples
3203 UINT_32 numFrags; ///< Number of fragments
3204
3205 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
3206
3207 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3208 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT;
3209
3210 /**
3211 ****************************************************************************************************
3212 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3213 *
3214 * @brief
3215 * Output structure for Addr2ComputeFmaskCoordFromAddr
3216 ****************************************************************************************************
3217 */
3218 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3219 {
3220 UINT_32 size; ///< Size of this structure in bytes
3221
3222 UINT_32 x; ///< X coordinate
3223 UINT_32 y; ///< Y coordinate
3224 UINT_32 slice; ///< Slice index
3225 UINT_32 sample; ///< Sample index (fragment index for EQAA)
3226 UINT_32 plane; ///< Plane number
3227 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
3228
3229 /**
3230 ****************************************************************************************************
3231 * Addr2ComputeFmaskCoordFromAddr
3232 *
3233 * @brief
3234 * Compute FMASK coordinate from an given address
3235 ****************************************************************************************************
3236 */
3237 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
3238 ADDR_HANDLE hLib,
3239 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
3240 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
3241
3242 ////////////////////////////////////////////////////////////////////////////////////////////////////
3243 // DCC key functions for Gfx9
3244 ////////////////////////////////////////////////////////////////////////////////////////////////////
3245
3246 /**
3247 ****************************************************************************************************
3248 * _ADDR2_COMPUTE_DCCINFO_INPUT
3249 *
3250 * @brief
3251 * Input structure of Addr2ComputeDccInfo
3252 ****************************************************************************************************
3253 */
3254 typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
3255 {
3256 UINT_32 size; ///< Size of this structure in bytes
3257
3258 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags
3259 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3260 AddrResourceType resourceType; ///< Color surface type
3261 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
3262 UINT_32 bpp; ///< bits per pixel
3263 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3264 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3265 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0)
3266 UINT_32 numFrags; ///< Fragment number of color surface
3267 UINT_32 numMipLevels; ///< Total mipmap levels of color surface
3268 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels
3269 ///< useful in meta linear case
3270 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
3271 /// it should be number of mip levels
3272 } ADDR2_COMPUTE_DCCINFO_INPUT;
3273
3274 /**
3275 ****************************************************************************************************
3276 * ADDR2_COMPUTE_DCCINFO_OUTPUT
3277 *
3278 * @brief
3279 * Output structure of Addr2ComputeDccInfo
3280 ****************************************************************************************************
3281 */
3282 typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
3283 {
3284 UINT_32 size; ///< Size of this structure in bytes
3285
3286 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
3287 UINT_32 dccRamSize; ///< Size of dcc key
3288
3289 UINT_32 pitch; ///< DCC surface mip chain pitch
3290 UINT_32 height; ///< DCC surface mip chain height
3291 UINT_32 depth; ///< DCC surface mip chain depth
3292
3293 UINT_32 compressBlkWidth; ///< DCC compress block width
3294 UINT_32 compressBlkHeight; ///< DCC compress block height
3295 UINT_32 compressBlkDepth; ///< DCC compress block depth
3296
3297 UINT_32 metaBlkWidth; ///< DCC meta block width
3298 UINT_32 metaBlkHeight; ///< DCC meta block height
3299 UINT_32 metaBlkDepth; ///< DCC meta block depth
3300
3301 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
3302
3303 union
3304 {
3305 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
3306 UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's
3307 /// the slize size of a mip chain, the thickness of a
3308 /// a slice is meta block depth
3309 };
3310
3311 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information
3312 } ADDR2_COMPUTE_DCCINFO_OUTPUT;
3313
3314 /**
3315 ****************************************************************************************************
3316 * Addr2ComputeDccInfo
3317 *
3318 * @brief
3319 * Compute DCC key size, base alignment
3320 * info
3321 ****************************************************************************************************
3322 */
3323 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
3324 ADDR_HANDLE hLib,
3325 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
3326 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);
3327
3328 /**
3329 ****************************************************************************************************
3330 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3331 *
3332 * @brief
3333 * Input structure for Addr2ComputeDccAddrFromCoord
3334 *
3335 ****************************************************************************************************
3336 */
3337 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3338 {
3339 UINT_32 size; ///< Size of this structure in bytes
3340
3341 UINT_32 x; ///< X coordinate
3342 UINT_32 y; ///< Y coordinate
3343 UINT_32 slice; ///< Index of slices
3344 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
3345 UINT_32 mipId; ///< mipmap level id
3346
3347 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags
3348 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3349 AddrResourceType resourceType; ///< Color surface type
3350 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
3351 UINT_32 bpp; ///< Color surface bits per pixel
3352 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3353 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3354 UINT_32 numSlices; ///< Color surface original slices (of mip0)
3355 UINT_32 numMipLevels; ///< Color surface mipmap levels
3356 UINT_32 numFrags; ///< Color surface fragment number
3357
3358 UINT_32 pipeXor; ///< pipe Xor setting
3359 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;
3360
3361 /**
3362 ****************************************************************************************************
3363 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3364 *
3365 * @brief
3366 * Output structure for Addr2ComputeDccAddrFromCoord
3367 ****************************************************************************************************
3368 */
3369 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3370 {
3371 UINT_32 size; ///< Size of this structure in bytes
3372
3373 UINT_64 addr; ///< DCC address in bytes
3374 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT;
3375
3376 /**
3377 ****************************************************************************************************
3378 * Addr2ComputeDccAddrFromCoord
3379 *
3380 * @brief
3381 * Compute DCC address according to coordinates (of MSAA color buffer)
3382 ****************************************************************************************************
3383 */
3384 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(
3385 ADDR_HANDLE hLib,
3386 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
3387 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
3388
3389 ////////////////////////////////////////////////////////////////////////////////////////////////////
3390 // Misc functions for Gfx9
3391 ////////////////////////////////////////////////////////////////////////////////////////////////////
3392
3393 /**
3394 ****************************************************************************************************
3395 * ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3396 *
3397 * @brief
3398 * Input structure of Addr2ComputePipebankXor
3399 ****************************************************************************************************
3400 */
3401 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3402 {
3403 UINT_32 size; ///< Size of this structure in bytes
3404 UINT_32 surfIndex; ///< Input surface index
3405 ADDR2_SURFACE_FLAGS flags; ///< Surface flag
3406 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3407 AddrResourceType resourceType; ///< Surface resource type
3408 AddrFormat format; ///< Surface format
3409 UINT_32 numSamples; ///< Number of samples
3410 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3411 /// number of samples for normal AA; Set it to the
3412 /// number of fragments for EQAA
3413 } ADDR2_COMPUTE_PIPEBANKXOR_INPUT;
3414
3415 /**
3416 ****************************************************************************************************
3417 * ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3418 *
3419 * @brief
3420 * Output structure of Addr2ComputePipebankXor
3421 ****************************************************************************************************
3422 */
3423 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3424 {
3425 UINT_32 size; ///< Size of this structure in bytes
3426 UINT_32 pipeBankXor; ///< Pipe bank xor
3427 } ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT;
3428
3429 /**
3430 ****************************************************************************************************
3431 * Addr2ComputePipeBankXor
3432 *
3433 * @brief
3434 * Calculate a valid bank pipe xor value for client to use.
3435 ****************************************************************************************************
3436 */
3437 ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor(
3438 ADDR_HANDLE hLib,
3439 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
3440 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
3441
3442 /**
3443 ****************************************************************************************************
3444 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3445 *
3446 * @brief
3447 * Input structure of Addr2ComputeSlicePipeBankXor
3448 ****************************************************************************************************
3449 */
3450 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3451 {
3452 UINT_32 size; ///< Size of this structure in bytes
3453 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3454 AddrResourceType resourceType; ///< Surface resource type
3455 UINT_32 basePipeBankXor; ///< Base pipe bank xor
3456 UINT_32 slice; ///< Slice id
3457 UINT_32 numSamples; ///< Number of samples
3458 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT;
3459
3460 /**
3461 ****************************************************************************************************
3462 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3463 *
3464 * @brief
3465 * Output structure of Addr2ComputeSlicePipeBankXor
3466 ****************************************************************************************************
3467 */
3468 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3469 {
3470 UINT_32 size; ///< Size of this structure in bytes
3471 UINT_32 pipeBankXor; ///< Pipe bank xor
3472 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT;
3473
3474 /**
3475 ****************************************************************************************************
3476 * Addr2ComputeSlicePipeBankXor
3477 *
3478 * @brief
3479 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id.
3480 ****************************************************************************************************
3481 */
3482 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(
3483 ADDR_HANDLE hLib,
3484 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
3485 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
3486
3487 /**
3488 ****************************************************************************************************
3489 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3490 *
3491 * @brief
3492 * Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3493 ****************************************************************************************************
3494 */
3495 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3496 {
3497 UINT_32 size; ///< Size of this structure in bytes
3498 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3499 AddrResourceType resourceType; ///< Surface resource type
3500 UINT_32 pipeBankXor; ///< Per resource xor
3501 UINT_32 slice; ///< Slice id
3502 UINT_64 sliceSize; ///< Slice size of a mip chain
3503 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO
3504 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO
3505 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT;
3506
3507 /**
3508 ****************************************************************************************************
3509 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3510 *
3511 * @brief
3512 * Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3513 ****************************************************************************************************
3514 */
3515 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3516 {
3517 UINT_32 size; ///< Size of this structure in bytes
3518 UINT_64 offset; ///< offset
3519 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT;
3520
3521 /**
3522 ****************************************************************************************************
3523 * Addr2ComputeSubResourceOffsetForSwizzlePattern
3524 *
3525 * @brief
3526 * Calculate sub resource offset to support swizzle pattern.
3527 ****************************************************************************************************
3528 */
3529 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
3530 ADDR_HANDLE hLib,
3531 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
3532 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
3533
3534 /**
3535 ****************************************************************************************************
3536 * ADDR2_BLOCK_SET
3537 *
3538 * @brief
3539 * Bit field that defines block type
3540 ****************************************************************************************************
3541 */
3542 typedef union _ADDR2_BLOCK_SET
3543 {
3544 struct
3545 {
3546 UINT_32 micro : 1; // 256B block for 2D resource
3547 UINT_32 macro4KB : 1; // 4KB for 2D/3D resource
3548 UINT_32 macro64KB : 1; // 64KB for 2D/3D resource
3549 UINT_32 var : 1; // VAR block
3550 UINT_32 linear : 1; // Linear block
3551 UINT_32 reserved : 27;
3552 };
3553
3554 UINT_32 value;
3555 } ADDR2_BLOCK_SET;
3556
3557 /**
3558 ****************************************************************************************************
3559 * ADDR2_SWTYPE_SET
3560 *
3561 * @brief
3562 * Bit field that defines swizzle type
3563 ****************************************************************************************************
3564 */
3565 typedef union _ADDR2_SWTYPE_SET
3566 {
3567 struct
3568 {
3569 UINT_32 sw_Z : 1; // SW_*_Z_*
3570 UINT_32 sw_S : 1; // SW_*_S_*
3571 UINT_32 sw_D : 1; // SW_*_D_*
3572 UINT_32 sw_R : 1; // SW_*_R_*
3573 UINT_32 reserved : 28;
3574 };
3575
3576 UINT_32 value;
3577 } ADDR2_SWTYPE_SET;
3578
3579 /**
3580 ****************************************************************************************************
3581 * ADDR2_SWMODE_SET
3582 *
3583 * @brief
3584 * Bit field that defines swizzle type
3585 ****************************************************************************************************
3586 */
3587 typedef union _ADDR2_SWMODE_SET
3588 {
3589 struct
3590 {
3591 UINT_32 swLinear : 1;
3592 UINT_32 sw256B_S : 1;
3593 UINT_32 sw256B_D : 1;
3594 UINT_32 sw256B_R : 1;
3595 UINT_32 sw4KB_Z : 1;
3596 UINT_32 sw4KB_S : 1;
3597 UINT_32 sw4KB_D : 1;
3598 UINT_32 sw4KB_R : 1;
3599 UINT_32 sw64KB_Z : 1;
3600 UINT_32 sw64KB_S : 1;
3601 UINT_32 sw64KB_D : 1;
3602 UINT_32 sw64KB_R : 1;
3603 UINT_32 swVar_Z : 1;
3604 UINT_32 swVar_S : 1;
3605 UINT_32 swVar_D : 1;
3606 UINT_32 swVar_R : 1;
3607 UINT_32 sw64KB_Z_T : 1;
3608 UINT_32 sw64KB_S_T : 1;
3609 UINT_32 sw64KB_D_T : 1;
3610 UINT_32 sw64KB_R_T : 1;
3611 UINT_32 sw4KB_Z_X : 1;
3612 UINT_32 sw4KB_S_X : 1;
3613 UINT_32 sw4KB_D_X : 1;
3614 UINT_32 sw4KB_R_X : 1;
3615 UINT_32 sw64KB_Z_X : 1;
3616 UINT_32 sw64KB_S_X : 1;
3617 UINT_32 sw64KB_D_X : 1;
3618 UINT_32 sw64KB_R_X : 1;
3619 UINT_32 swVar_Z_X : 1;
3620 UINT_32 swVar_S_X : 1;
3621 UINT_32 swVar_D_X : 1;
3622 UINT_32 swVar_R_X : 1;
3623 };
3624
3625 UINT_32 value;
3626 } ADDR2_SWMODE_SET;
3627
3628 /**
3629 ****************************************************************************************************
3630 * ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3631 *
3632 * @brief
3633 * Input structure of Addr2GetPreferredSurfaceSetting
3634 ****************************************************************************************************
3635 */
3636 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3637 {
3638 UINT_32 size; ///< Size of this structure in bytes
3639
3640 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
3641 AddrResourceType resourceType; ///< Surface type
3642 AddrFormat format; ///< Surface format
3643 AddrResrouceLocation resourceLoction; ///< Surface heap choice
3644 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting
3645 ///< such as linear for DXTn, tiled for YUV
3646 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted
3647 BOOL_32 noXor; ///< Do not use xor mode for this resource
3648 UINT_32 bpp; ///< bits per pixel
3649 UINT_32 width; ///< Width (of mip0), in pixels
3650 UINT_32 height; ///< Height (of mip0), in pixels
3651 UINT_32 numSlices; ///< Number surface slice/depth (of mip0),
3652 UINT_32 numMipLevels; ///< Total mipmap levels.
3653 UINT_32 numSamples; ///< Number of samples
3654 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3655 /// number of samples for normal AA; Set it to the
3656 /// number of fragments for EQAA
3657 UINT_32 maxAlign; ///< maximum base/size alignment requested by client
3658 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will
3659 /// be padded to multiple of this value (in bytes)
3660 } ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;
3661
3662 /**
3663 ****************************************************************************************************
3664 * ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3665 *
3666 * @brief
3667 * Output structure of Addr2GetPreferredSurfaceSetting
3668 ****************************************************************************************************
3669 */
3670 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3671 {
3672 UINT_32 size; ///< Size of this structure in bytes
3673
3674 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used
3675 AddrResourceType resourceType; ///< Suggested resource type to program HW
3676 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination
3677 BOOL_32 canXor; ///< If client can use xor on a valid macro block
3678 /// type
3679 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination
3680 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
3681 ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination
3682 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
3683
3684 /**
3685 ****************************************************************************************************
3686 * Addr2GetPreferredSurfaceSetting
3687 *
3688 * @brief
3689 * Suggest a preferred setting for client driver to program HW register
3690 ****************************************************************************************************
3691 */
3692 ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(
3693 ADDR_HANDLE hLib,
3694 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
3695 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut);
3696
3697 /**
3698 ****************************************************************************************************
3699 * Addr2IsValidDisplaySwizzleMode
3700 *
3701 * @brief
3702 * Return whether the swizzle mode is supported by DCE / DCN.
3703 ****************************************************************************************************
3704 */
3705 ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
3706 ADDR_HANDLE hLib,
3707 AddrSwizzleMode swizzleMode,
3708 UINT_32 bpp,
3709 bool *result);
3710
3711 #if defined(__cplusplus)
3712 }
3713 #endif
3714
3715 #endif // __ADDR_INTERFACE_H__