src/amd/addrlib/inc/chip/gfx9/gfx9_gb_reg.h

   1 #if !defined (__GFX9_GB_REG_H__)
   2 #define __GFX9_GB_REG_H__
   3
   4 /*
   5  * Copyright © 2017 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29
  30 //
  31 // Make sure the necessary endian defines are there.
  32 //
  33 #if defined(LITTLEENDIAN_CPU)
  34 #elif defined(BIGENDIAN_CPU)
  35 #else
  36 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
  37 #endif
  38
  39 union GB_ADDR_CONFIG {
  40     struct {
  41 #if        defined(LITTLEENDIAN_CPU)
  42         unsigned int                       NUM_PIPES : 3;
  43         unsigned int            PIPE_INTERLEAVE_SIZE : 3;
  44         unsigned int            MAX_COMPRESSED_FRAGS : 2;
  45         unsigned int            BANK_INTERLEAVE_SIZE : 3;
  46         unsigned int                                 : 1;
  47         unsigned int                       NUM_BANKS : 3;
  48         unsigned int                                 : 1;
  49         unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
  50         unsigned int              NUM_SHADER_ENGINES : 2;
  51         unsigned int                        NUM_GPUS : 3;
  52         unsigned int             MULTI_GPU_TILE_SIZE : 2;
  53         unsigned int                   NUM_RB_PER_SE : 2;
  54         unsigned int                        ROW_SIZE : 2;
  55         unsigned int                 NUM_LOWER_PIPES : 1;
  56         unsigned int                       SE_ENABLE : 1;
  57 #elif        defined(BIGENDIAN_CPU)
  58         unsigned int                       SE_ENABLE : 1;
  59         unsigned int                 NUM_LOWER_PIPES : 1;
  60         unsigned int                        ROW_SIZE : 2;
  61         unsigned int                   NUM_RB_PER_SE : 2;
  62         unsigned int             MULTI_GPU_TILE_SIZE : 2;
  63         unsigned int                        NUM_GPUS : 3;
  64         unsigned int              NUM_SHADER_ENGINES : 2;
  65         unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
  66         unsigned int                                 : 1;
  67         unsigned int                       NUM_BANKS : 3;
  68         unsigned int                                 : 1;
  69         unsigned int            BANK_INTERLEAVE_SIZE : 3;
  70         unsigned int            MAX_COMPRESSED_FRAGS : 2;
  71         unsigned int            PIPE_INTERLEAVE_SIZE : 3;
  72         unsigned int                       NUM_PIPES : 3;
  73 #endif
  74     } bitfields, bits;
  75     unsigned int    u32All;
  76     signed int    i32All;
  77     float    f32All;
  78 };
  79
  80 #endif
  81