src/amd/addrlib/src/chip/gfx9/gfx9_gb_reg.h

   1 /*
   2  * Copyright © 2007-2019 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #if !defined (__GFX9_GB_REG_H__)
  28 #define __GFX9_GB_REG_H__
  29
  30 /*
  31 *    gfx9_gb_reg.h
  32 *
  33 *    Register Spec Release:  1.0
  34 *
  35 */
  36
  37 //
  38 // Make sure the necessary endian defines are there.
  39 //
  40 #include "util/u_endian.h"
  41
  42 #if UTIL_ARCH_LITTLE_ENDIAN
  43 #define LITTLEENDIAN_CPU
  44 #elif UTIL_ARCH_BIG_ENDIAN
  45 #define BIGENDIAN_CPU
  46 #endif
  47
  48 union GB_ADDR_CONFIG {
  49     struct {
  50 #if        defined(LITTLEENDIAN_CPU)
  51         unsigned int                       NUM_PIPES : 3;
  52         unsigned int            PIPE_INTERLEAVE_SIZE : 3;
  53         unsigned int            MAX_COMPRESSED_FRAGS : 2;
  54         unsigned int            BANK_INTERLEAVE_SIZE : 3;
  55         unsigned int                                 : 1;
  56         unsigned int                       NUM_BANKS : 3;
  57         unsigned int                                 : 1;
  58         unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
  59         unsigned int              NUM_SHADER_ENGINES : 2;
  60         unsigned int                        NUM_GPUS : 3;
  61         unsigned int             MULTI_GPU_TILE_SIZE : 2;
  62         unsigned int                   NUM_RB_PER_SE : 2;
  63         unsigned int                        ROW_SIZE : 2;
  64         unsigned int                 NUM_LOWER_PIPES : 1;
  65         unsigned int                       SE_ENABLE : 1;
  66 #elif        defined(BIGENDIAN_CPU)
  67         unsigned int                       SE_ENABLE : 1;
  68         unsigned int                 NUM_LOWER_PIPES : 1;
  69         unsigned int                        ROW_SIZE : 2;
  70         unsigned int                   NUM_RB_PER_SE : 2;
  71         unsigned int             MULTI_GPU_TILE_SIZE : 2;
  72         unsigned int                        NUM_GPUS : 3;
  73         unsigned int              NUM_SHADER_ENGINES : 2;
  74         unsigned int         SHADER_ENGINE_TILE_SIZE : 3;
  75         unsigned int                                 : 1;
  76         unsigned int                       NUM_BANKS : 3;
  77         unsigned int                                 : 1;
  78         unsigned int            BANK_INTERLEAVE_SIZE : 3;
  79         unsigned int            MAX_COMPRESSED_FRAGS : 2;
  80         unsigned int            PIPE_INTERLEAVE_SIZE : 3;
  81         unsigned int                       NUM_PIPES : 3;
  82 #endif
  83     } bitfields, bits;
  84     unsigned int    u32All;
  85     signed int    i32All;
  86     float    f32All;
  87 };
  88
  89 #endif
  90