1 #if !defined (__SI_GB_REG_H__)
2 #define __SI_GB_REG_H__
5 * Copyright © 2007-2019 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * The above copyright notice and this permission notice (including the
26 * next paragraph) shall be included in all copies or substantial portions
30 #include "util/u_endian.h"
32 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
33 #define LITTLEENDIAN_CPU
34 #elif defined(PIPE_ARCH_BIG_ENDIAN)
39 // Make sure the necessary endian defines are there.
41 #if defined(LITTLEENDIAN_CPU)
42 #elif defined(BIGENDIAN_CPU)
44 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
48 * GB_ADDR_CONFIG struct
51 #if defined(LITTLEENDIAN_CPU)
53 typedef struct _GB_ADDR_CONFIG_T
{
54 unsigned int num_pipes
: 3;
56 unsigned int pipe_interleave_size
: 3;
58 unsigned int bank_interleave_size
: 3;
60 unsigned int num_shader_engines
: 2;
62 unsigned int shader_engine_tile_size
: 3;
64 unsigned int num_gpus
: 3;
66 unsigned int multi_gpu_tile_size
: 2;
68 unsigned int row_size
: 2;
69 unsigned int num_lower_pipes
: 1;
73 #elif defined(BIGENDIAN_CPU)
75 typedef struct _GB_ADDR_CONFIG_T
{
77 unsigned int num_lower_pipes
: 1;
78 unsigned int row_size
: 2;
80 unsigned int multi_gpu_tile_size
: 2;
82 unsigned int num_gpus
: 3;
84 unsigned int shader_engine_tile_size
: 3;
86 unsigned int num_shader_engines
: 2;
88 unsigned int bank_interleave_size
: 3;
90 unsigned int pipe_interleave_size
: 3;
92 unsigned int num_pipes
: 3;
98 unsigned int val
: 32;
102 #if defined(LITTLEENDIAN_CPU)
104 typedef struct _GB_TILE_MODE_T
{
105 unsigned int micro_tile_mode
: 2;
106 unsigned int array_mode
: 4;
107 unsigned int pipe_config
: 5;
108 unsigned int tile_split
: 3;
109 unsigned int bank_width
: 2;
110 unsigned int bank_height
: 2;
111 unsigned int macro_tile_aspect
: 2;
112 unsigned int num_banks
: 2;
113 unsigned int micro_tile_mode_new
: 3;
114 unsigned int sample_split
: 2;
118 typedef struct _GB_MACROTILE_MODE_T
{
119 unsigned int bank_width
: 2;
120 unsigned int bank_height
: 2;
121 unsigned int macro_tile_aspect
: 2;
122 unsigned int num_banks
: 2;
124 } GB_MACROTILE_MODE_T
;
126 #elif defined(BIGENDIAN_CPU)
128 typedef struct _GB_TILE_MODE_T
{
130 unsigned int sample_split
: 2;
131 unsigned int micro_tile_mode_new
: 3;
132 unsigned int num_banks
: 2;
133 unsigned int macro_tile_aspect
: 2;
134 unsigned int bank_height
: 2;
135 unsigned int bank_width
: 2;
136 unsigned int tile_split
: 3;
137 unsigned int pipe_config
: 5;
138 unsigned int array_mode
: 4;
139 unsigned int micro_tile_mode
: 2;
142 typedef struct _GB_MACROTILE_MODE_T
{
144 unsigned int num_banks
: 2;
145 unsigned int macro_tile_aspect
: 2;
146 unsigned int bank_height
: 2;
147 unsigned int bank_width
: 2;
148 } GB_MACROTILE_MODE_T
;
153 unsigned int val
: 32;
158 unsigned int val
: 32;
159 GB_MACROTILE_MODE_T f
;