2 * Copyright © 2007-2019 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #if !defined (__SI_GB_REG_H__)
28 #define __SI_GB_REG_H__
30 /*****************************************************************************************************************
34 * Register Spec Release: Chip Spec 0.28
36 *****************************************************************************************************************/
39 // Make sure the necessary endian defines are there.
41 #include "util/u_endian.h"
43 #if UTIL_ARCH_LITTLE_ENDIAN
44 #define LITTLEENDIAN_CPU
45 #elif UTIL_ARCH_BIG_ENDIAN
50 * GB_ADDR_CONFIG struct
53 #if defined(LITTLEENDIAN_CPU)
55 typedef struct _GB_ADDR_CONFIG_T
{
56 unsigned int num_pipes
: 3;
58 unsigned int pipe_interleave_size
: 3;
60 unsigned int bank_interleave_size
: 3;
62 unsigned int num_shader_engines
: 2;
64 unsigned int shader_engine_tile_size
: 3;
66 unsigned int num_gpus
: 3;
68 unsigned int multi_gpu_tile_size
: 2;
70 unsigned int row_size
: 2;
71 unsigned int num_lower_pipes
: 1;
75 #elif defined(BIGENDIAN_CPU)
77 typedef struct _GB_ADDR_CONFIG_T
{
79 unsigned int num_lower_pipes
: 1;
80 unsigned int row_size
: 2;
82 unsigned int multi_gpu_tile_size
: 2;
84 unsigned int num_gpus
: 3;
86 unsigned int shader_engine_tile_size
: 3;
88 unsigned int num_shader_engines
: 2;
90 unsigned int bank_interleave_size
: 3;
92 unsigned int pipe_interleave_size
: 3;
94 unsigned int num_pipes
: 3;
100 unsigned int val
: 32;
104 #if defined(LITTLEENDIAN_CPU)
106 typedef struct _GB_TILE_MODE_T
{
107 unsigned int micro_tile_mode
: 2;
108 unsigned int array_mode
: 4;
109 unsigned int pipe_config
: 5;
110 unsigned int tile_split
: 3;
111 unsigned int bank_width
: 2;
112 unsigned int bank_height
: 2;
113 unsigned int macro_tile_aspect
: 2;
114 unsigned int num_banks
: 2;
115 unsigned int micro_tile_mode_new
: 3;
116 unsigned int sample_split
: 2;
120 typedef struct _GB_MACROTILE_MODE_T
{
121 unsigned int bank_width
: 2;
122 unsigned int bank_height
: 2;
123 unsigned int macro_tile_aspect
: 2;
124 unsigned int num_banks
: 2;
126 } GB_MACROTILE_MODE_T
;
128 #elif defined(BIGENDIAN_CPU)
130 typedef struct _GB_TILE_MODE_T
{
132 unsigned int sample_split
: 2;
133 unsigned int micro_tile_mode_new
: 3;
134 unsigned int num_banks
: 2;
135 unsigned int macro_tile_aspect
: 2;
136 unsigned int bank_height
: 2;
137 unsigned int bank_width
: 2;
138 unsigned int tile_split
: 3;
139 unsigned int pipe_config
: 5;
140 unsigned int array_mode
: 4;
141 unsigned int micro_tile_mode
: 2;
144 typedef struct _GB_MACROTILE_MODE_T
{
146 unsigned int num_banks
: 2;
147 unsigned int macro_tile_aspect
: 2;
148 unsigned int bank_height
: 2;
149 unsigned int bank_width
: 2;
150 } GB_MACROTILE_MODE_T
;
155 unsigned int val
: 32;
160 unsigned int val
: 32;
161 GB_MACROTILE_MODE_T f
;