src/amd/addrlib/src/core/addrlib2.h

   1 /*
   2  * Copyright © 2007-2019 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 /**
  28 ************************************************************************************************************************
  29 * @file  addrlib2.h
  30 * @brief Contains the Addr::V2::Lib class definition.
  31 ************************************************************************************************************************
  32 */
  33
  34 #ifndef __ADDR2_LIB2_H__
  35 #define __ADDR2_LIB2_H__
  36
  37 #include "addrlib.h"
  38
  39 namespace Addr
  40 {
  41 namespace V2
  42 {
  43
  44 /**
  45 ************************************************************************************************************************
  46 * @brief Flags for SwizzleModeTable
  47 ************************************************************************************************************************
  48 */
  49 struct SwizzleModeFlags
  50 {
  51     // Swizzle mode
  52     UINT_32 isLinear        : 1;    // Linear
  53
  54     // Block size
  55     UINT_32 is256b          : 1;    // Block size is 256B
  56     UINT_32 is4kb           : 1;    // Block size is 4KB
  57     UINT_32 is64kb          : 1;    // Block size is 64KB
  58     UINT_32 isVar           : 1;    // Block size is variable
  59
  60     UINT_32 isZ             : 1;    // Z order swizzle mode
  61     UINT_32 isStd           : 1;    // Standard swizzle mode
  62     UINT_32 isDisp          : 1;    // Display swizzle mode
  63     UINT_32 isRot           : 1;    // Rotate swizzle mode
  64
  65     // XOR mode
  66     UINT_32 isXor           : 1;    // XOR after swizzle if set
  67
  68     UINT_32 isT             : 1;    // T mode
  69
  70     UINT_32 isRtOpt         : 1;    // mode opt for render target
  71 };
  72
  73 struct Dim2d
  74 {
  75     UINT_32 w;
  76     UINT_32 h;
  77 };
  78
  79 struct Dim3d
  80 {
  81     UINT_32 w;
  82     UINT_32 h;
  83     UINT_32 d;
  84 };
  85
  86 // Macro define resource block type
  87 enum AddrBlockType
  88 {
  89     AddrBlockMicro     = 0, // Resource uses 256B block
  90     AddrBlock4KB       = 1, // Resource uses 4KB block
  91     AddrBlock64KB      = 2, // Resource uses 64KB block
  92     AddrBlockVar       = 3, // Resource uses var block, only valid for GFX9
  93     AddrBlockLinear    = 4, // Resource uses linear swizzle mode
  94
  95     AddrBlockMaxTiledType = AddrBlock64KB + 1,
  96 };
  97
  98 enum AddrBlockSet
  99 {
 100     AddrBlockSetMicro     = 1 << AddrBlockMicro,
 101     AddrBlockSetMacro4KB  = 1 << AddrBlock4KB,
 102     AddrBlockSetMacro64KB = 1 << AddrBlock64KB,
 103     AddrBlockSetVar       = 1 << AddrBlockVar,
 104     AddrBlockSetLinear    = 1 << AddrBlockLinear,
 105
 106     AddrBlockSetMacro   = AddrBlockSetMacro4KB | AddrBlockSetMacro64KB,
 107 };
 108
 109 enum AddrSwSet
 110 {
 111     AddrSwSetZ = 1 << ADDR_SW_Z,
 112     AddrSwSetS = 1 << ADDR_SW_S,
 113     AddrSwSetD = 1 << ADDR_SW_D,
 114     AddrSwSetR = 1 << ADDR_SW_R,
 115
 116     AddrSwSetAll         = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR,
 117 };
 118
 119 /**
 120 ************************************************************************************************************************
 121 * @brief This class contains asic independent address lib functionalities
 122 ************************************************************************************************************************
 123 */
 124 class Lib : public Addr::Lib
 125 {
 126 public:
 127     virtual ~Lib();
 128
 129     static Lib* GetLib(
 130         ADDR_HANDLE hLib);
 131
 132     //
 133     // Interface stubs
 134     //
 135
 136     // For data surface
 137     ADDR_E_RETURNCODE ComputeSurfaceInfo(
 138         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
 139         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
 140
 141     ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
 142         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
 143         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const;
 144
 145     ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
 146         const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
 147         ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut) const;
 148
 149     // For HTile
 150     ADDR_E_RETURNCODE ComputeHtileInfo(
 151         const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
 152         ADDR2_COMPUTE_HTILE_INFO_OUTPUT*      pOut) const;
 153
 154     ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
 155         const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
 156         ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*      pOut);
 157
 158     ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
 159         const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
 160         ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*      pOut);
 161
 162     // For CMask
 163     ADDR_E_RETURNCODE ComputeCmaskInfo(
 164         const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
 165         ADDR2_COMPUTE_CMASK_INFO_OUTPUT*      pOut) const;
 166
 167     ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
 168         const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
 169         ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*      pOut);
 170
 171     ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
 172         const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
 173         ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*      pOut) const;
 174
 175     // For FMask
 176     ADDR_E_RETURNCODE ComputeFmaskInfo(
 177         const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
 178         ADDR2_COMPUTE_FMASK_INFO_OUTPUT*      pOut);
 179
 180     ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
 181         const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
 182         ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*      pOut) const;
 183
 184     ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
 185         const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
 186         ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*      pOut) const;
 187
 188     // For DCC key
 189     ADDR_E_RETURNCODE ComputeDccInfo(
 190         const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
 191         ADDR2_COMPUTE_DCCINFO_OUTPUT*      pOut) const;
 192
 193     ADDR_E_RETURNCODE ComputeDccAddrFromCoord(
 194         const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
 195         ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*      pOut);
 196
 197     // Misc
 198     ADDR_E_RETURNCODE ComputePipeBankXor(
 199         const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
 200         ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT*      pOut);
 201
 202     ADDR_E_RETURNCODE ComputeSlicePipeBankXor(
 203         const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
 204         ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT*      pOut);
 205
 206     ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern(
 207         const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
 208         ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT*      pOut);
 209
 210     ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting(
 211         const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
 212         ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT*      pOut) const;
 213
 214     virtual BOOL_32 IsValidDisplaySwizzleMode(
 215         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
 216     {
 217         ADDR_NOT_IMPLEMENTED();
 218         return ADDR_NOTIMPLEMENTED;
 219     }
 220
 221 protected:
 222     Lib();  // Constructor is protected
 223     Lib(const Client* pClient);
 224
 225     static const UINT_32 MaxNumOfBpp = 5;
 226     static const UINT_32 MaxNumOfAA  = 4;
 227
 228     static const Dim2d Block256_2d[MaxNumOfBpp];
 229     static const Dim3d Block1K_3d[MaxNumOfBpp];
 230
 231     static const UINT_32 PrtAlignment = 64 * 1024;
 232     static const UINT_32 MaxMacroBits = 20;
 233
 234     static const UINT_32 MaxMipLevels = 16;
 235
 236     // Checking block size
 237     BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const
 238     {
 239         return m_swizzleModeTable[swizzleMode].is256b;
 240     }
 241
 242     BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const
 243     {
 244         return m_swizzleModeTable[swizzleMode].is4kb;
 245     }
 246
 247     BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const
 248     {
 249         return m_swizzleModeTable[swizzleMode].is64kb;
 250     }
 251
 252     BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const
 253     {
 254         return m_swizzleModeTable[swizzleMode].isVar;
 255     }
 256
 257     // Checking swizzle mode
 258     BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const
 259     {
 260         return m_swizzleModeTable[swizzleMode].isLinear;
 261     }
 262
 263     BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const
 264     {
 265         return m_swizzleModeTable[swizzleMode].isRtOpt;
 266     }
 267
 268     BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const
 269     {
 270         return m_swizzleModeTable[swizzleMode].isZ;
 271     }
 272
 273     BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const
 274     {
 275         return m_swizzleModeTable[swizzleMode].isStd;
 276     }
 277
 278     BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const
 279     {
 280         return m_swizzleModeTable[swizzleMode].isDisp;
 281     }
 282
 283     BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const
 284     {
 285         return m_swizzleModeTable[swizzleMode].isRot;
 286     }
 287
 288     BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
 289     {
 290         return HwlIsStandardSwizzle(resourceType, swizzleMode);
 291     }
 292
 293     BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
 294     {
 295         return HwlIsDisplaySwizzle(resourceType, swizzleMode);
 296     }
 297
 298     BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const
 299     {
 300         return m_swizzleModeTable[swizzleMode].isXor;
 301     }
 302
 303     BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const
 304     {
 305         return m_swizzleModeTable[swizzleMode].isT;
 306     }
 307
 308     BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const
 309     {
 310         return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE));
 311     }
 312
 313     // Checking resource type
 314     static BOOL_32 IsTex1d(AddrResourceType resourceType)
 315     {
 316         return (resourceType == ADDR_RSRC_TEX_1D);
 317     }
 318
 319     static BOOL_32 IsTex2d(AddrResourceType resourceType)
 320     {
 321         return (resourceType == ADDR_RSRC_TEX_2D);
 322     }
 323
 324     static BOOL_32 IsTex3d(AddrResourceType resourceType)
 325     {
 326         return (resourceType == ADDR_RSRC_TEX_3D);
 327     }
 328
 329     BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
 330     {
 331         return HwlIsThick(resourceType, swizzleMode);
 332     }
 333
 334     BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
 335     {
 336         return HwlIsThin(resourceType, swizzleMode);
 337     }
 338
 339     UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const
 340     {
 341         UINT_32 blockSizeLog2 = 0;
 342
 343         if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode))
 344         {
 345             blockSizeLog2 = 8;
 346         }
 347         else if (IsBlock4kb(swizzleMode))
 348         {
 349             blockSizeLog2 = 12;
 350         }
 351         else if (IsBlock64kb(swizzleMode))
 352         {
 353             blockSizeLog2 = 16;
 354         }
 355         else if (IsBlockVariable(swizzleMode))
 356         {
 357             blockSizeLog2 = m_blockVarSizeLog2;
 358         }
 359         else
 360         {
 361             ADDR_ASSERT_ALWAYS();
 362         }
 363
 364         return blockSizeLog2;
 365     }
 366
 367     UINT_32 GetBlockSize(AddrSwizzleMode swizzleMode) const
 368     {
 369         return (1 << GetBlockSizeLog2(swizzleMode));
 370     }
 371
 372     static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag)
 373     {
 374         sample = (sample == 0) ? 1 : sample;
 375         frag   = (frag   == 0) ? sample : frag;
 376
 377         UINT_32 fmaskBpp = QLog2(frag);
 378
 379         if (sample > frag)
 380         {
 381             fmaskBpp++;
 382         }
 383
 384         if (fmaskBpp == 3)
 385         {
 386             fmaskBpp = 4;
 387         }
 388
 389         fmaskBpp = Max(8u, fmaskBpp * sample);
 390
 391         return fmaskBpp;
 392     }
 393
 394     virtual BOOL_32 HwlIsStandardSwizzle(
 395         AddrResourceType resourceType,
 396         AddrSwizzleMode  swizzleMode) const
 397     {
 398         ADDR_NOT_IMPLEMENTED();
 399         return FALSE;
 400     }
 401
 402     virtual BOOL_32 HwlIsDisplaySwizzle(
 403         AddrResourceType resourceType,
 404         AddrSwizzleMode  swizzleMode) const
 405     {
 406         ADDR_NOT_IMPLEMENTED();
 407         return FALSE;
 408     }
 409
 410     virtual BOOL_32 HwlIsThin(
 411         AddrResourceType resourceType,
 412         AddrSwizzleMode  swizzleMode) const
 413     {
 414         ADDR_NOT_IMPLEMENTED();
 415         return FALSE;
 416     }
 417
 418     virtual BOOL_32 HwlIsThick(
 419         AddrResourceType resourceType,
 420         AddrSwizzleMode  swizzleMode) const
 421     {
 422         ADDR_NOT_IMPLEMENTED();
 423         return FALSE;
 424     }
 425
 426     virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
 427         const ADDR2_COMPUTE_HTILE_INFO_INPUT*    pIn,
 428         ADDR2_COMPUTE_HTILE_INFO_OUTPUT*         pOut) const
 429     {
 430         ADDR_NOT_IMPLEMENTED();
 431         return ADDR_NOTSUPPORTED;
 432     }
 433
 434     virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
 435         const ADDR2_COMPUTE_CMASK_INFO_INPUT*    pIn,
 436         ADDR2_COMPUTE_CMASK_INFO_OUTPUT*         pOut) const
 437     {
 438         ADDR_NOT_IMPLEMENTED();
 439         return ADDR_NOTSUPPORTED;
 440     }
 441
 442     virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
 443         const ADDR2_COMPUTE_DCCINFO_INPUT*    pIn,
 444         ADDR2_COMPUTE_DCCINFO_OUTPUT*         pOut) const
 445     {
 446         ADDR_NOT_IMPLEMENTED();
 447         return ADDR_NOTSUPPORTED;
 448     }
 449
 450     virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
 451         const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
 452         ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*      pOut)
 453     {
 454         ADDR_NOT_IMPLEMENTED();
 455         return ADDR_NOTSUPPORTED;
 456     }
 457
 458     virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
 459         const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
 460         ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*      pOut)
 461     {
 462         ADDR_NOT_IMPLEMENTED();
 463         return ADDR_NOTSUPPORTED;
 464     }
 465
 466     virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
 467         const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
 468         ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*      pOut)
 469     {
 470         ADDR_NOT_IMPLEMENTED();
 471         return ADDR_NOTSUPPORTED;
 472     }
 473
 474     virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
 475         const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
 476         ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*      pOut)
 477     {
 478         ADDR_NOT_IMPLEMENTED();
 479         return ADDR_NOTSUPPORTED;
 480     }
 481
 482     virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation(
 483         AddrResourceType rsrcType,
 484         AddrSwizzleMode swMode,
 485         UINT_32 elementBytesLog2,
 486         ADDR_EQUATION* pEquation) const
 487     {
 488         ADDR_NOT_IMPLEMENTED();
 489         return ADDR_NOTSUPPORTED;
 490     }
 491
 492     virtual ADDR_E_RETURNCODE HwlComputeThinEquation(
 493         AddrResourceType rsrcType,
 494         AddrSwizzleMode swMode,
 495         UINT_32 elementBytesLog2,
 496         ADDR_EQUATION* pEquation) const
 497     {
 498         ADDR_NOT_IMPLEMENTED();
 499         return ADDR_NOTSUPPORTED;
 500     }
 501
 502     virtual ADDR_E_RETURNCODE HwlComputeThickEquation(
 503         AddrResourceType rsrcType,
 504         AddrSwizzleMode swMode,
 505         UINT_32 elementBytesLog2,
 506         ADDR_EQUATION* pEquation) const
 507     {
 508         ADDR_NOT_IMPLEMENTED();
 509         return ADDR_NOTSUPPORTED;
 510     }
 511
 512     virtual UINT_32 HwlGetEquationIndex(
 513         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
 514         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const
 515     {
 516         ADDR_NOT_IMPLEMENTED();
 517         return ADDR_INVALID_EQUATION_INDEX;
 518     }
 519
 520     UINT_32 GetEquationIndex(
 521         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
 522         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const
 523     {
 524         return HwlGetEquationIndex(pIn, pOut);
 525     }
 526
 527     virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
 528         const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
 529         ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT*      pOut) const
 530     {
 531         ADDR_NOT_IMPLEMENTED();
 532         return ADDR_NOTSUPPORTED;
 533     }
 534
 535     virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
 536         const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
 537         ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT*      pOut) const
 538     {
 539         ADDR_NOT_IMPLEMENTED();
 540         return ADDR_NOTSUPPORTED;
 541     }
 542
 543     virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
 544         const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
 545         ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT*      pOut) const
 546     {
 547         ADDR_NOT_IMPLEMENTED();
 548         return ADDR_NOTSUPPORTED;
 549     }
 550
 551     virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
 552         const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
 553         ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT*      pOut) const
 554     {
 555         ADDR_NOT_IMPLEMENTED();
 556         return ADDR_NOTSUPPORTED;
 557     }
 558
 559     virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
 560         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
 561     {
 562         ADDR_NOT_IMPLEMENTED();
 563         return ADDR_NOTSUPPORTED;
 564     }
 565
 566     virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
 567          const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
 568          ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const
 569     {
 570         ADDR_NOT_IMPLEMENTED();
 571         return ADDR_NOTIMPLEMENTED;
 572     }
 573
 574     virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
 575          const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
 576          ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const
 577     {
 578         ADDR_NOT_IMPLEMENTED();
 579         return ADDR_NOTIMPLEMENTED;
 580     }
 581
 582     virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
 583         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
 584         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const
 585     {
 586         ADDR_NOT_IMPLEMENTED();
 587         return ADDR_NOTIMPLEMENTED;
 588     }
 589
 590     ADDR_E_RETURNCODE ComputeBlock256Equation(
 591         AddrResourceType rsrcType,
 592         AddrSwizzleMode swMode,
 593         UINT_32 elementBytesLog2,
 594         ADDR_EQUATION* pEquation) const;
 595
 596     ADDR_E_RETURNCODE ComputeThinEquation(
 597         AddrResourceType rsrcType,
 598         AddrSwizzleMode swMode,
 599         UINT_32 elementBytesLog2,
 600         ADDR_EQUATION* pEquation) const;
 601
 602     ADDR_E_RETURNCODE ComputeThickEquation(
 603         AddrResourceType rsrcType,
 604         AddrSwizzleMode swMode,
 605         UINT_32 elementBytesLog2,
 606         ADDR_EQUATION* pEquation) const;
 607
 608     ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck(
 609         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
 610
 611     ADDR_E_RETURNCODE ComputeSurfaceInfoLinear(
 612         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
 613         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
 614
 615     ADDR_E_RETURNCODE ComputeSurfaceInfoTiled(
 616         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
 617         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
 618
 619     ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear(
 620         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
 621         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const;
 622
 623     ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled(
 624         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
 625         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const;
 626
 627     ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrLinear(
 628         const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
 629         ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut) const;
 630
 631     ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrTiled(
 632         const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
 633         ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*      pOut) const;
 634
 635     UINT_32 ComputeSurface2DMicroBlockOffset(
 636         const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const;
 637
 638     UINT_32 ComputeSurface3DMicroBlockOffset(
 639         const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const;
 640
 641     // Misc
 642     ADDR_E_RETURNCODE ComputeBlockDimensionForSurf(
 643         UINT_32*         pWidth,
 644         UINT_32*         pHeight,
 645         UINT_32*         pDepth,
 646         UINT_32          bpp,
 647         UINT_32          numSamples,
 648         AddrResourceType resourceType,
 649         AddrSwizzleMode  swizzleMode) const;
 650
 651     ADDR_E_RETURNCODE ComputeBlockDimension(
 652         UINT_32*          pWidth,
 653         UINT_32*          pHeight,
 654         UINT_32*          pDepth,
 655         UINT_32           bpp,
 656         AddrResourceType  resourceType,
 657         AddrSwizzleMode   swizzleMode) const;
 658
 659     static UINT_64 ComputePadSize(
 660         const Dim3d*      pBlkDim,
 661         UINT_32           width,
 662         UINT_32           height,
 663         UINT_32           numSlices,
 664         Dim3d*            pPadDim)
 665     {
 666         pPadDim->w = PowTwoAlign(width ,pBlkDim->w);
 667         pPadDim->h = PowTwoAlign(height ,pBlkDim->h);
 668         pPadDim->d = PowTwoAlign(numSlices, pBlkDim->d);
 669         return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d;
 670     }
 671
 672     static ADDR_E_RETURNCODE ExtractPipeBankXor(
 673         UINT_32  pipeBankXor,
 674         UINT_32  bankBits,
 675         UINT_32  pipeBits,
 676         UINT_32* pBankX,
 677         UINT_32* pPipeX);
 678
 679     static BOOL_32 Valid3DMipSliceIdConstraint(
 680         UINT_32 numSlices,
 681         UINT_32 mipId,
 682         UINT_32 slice)
 683     {
 684         return (Max((numSlices >> mipId), 1u) > slice);
 685     }
 686
 687     Dim3d GetMipTailDim(
 688         AddrResourceType  resourceType,
 689         AddrSwizzleMode   swizzleMode,
 690         UINT_32           blockWidth,
 691         UINT_32           blockHeight,
 692         UINT_32           blockDepth) const;
 693
 694     static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType)
 695     {
 696         return ((resourceType == ADDR_RSRC_LOC_LOCAL) ||
 697                 (resourceType == ADDR_RSRC_LOC_INVIS));
 698     }
 699
 700     static BOOL_32 IsInvisibleHeap(AddrResrouceLocation resourceType)
 701     {
 702         return (resourceType == ADDR_RSRC_LOC_INVIS);
 703     }
 704
 705     static BOOL_32 IsNonlocalHeap(AddrResrouceLocation resourceType)
 706     {
 707         return ((resourceType == ADDR_RSRC_LOC_USWC) ||
 708                 (resourceType == ADDR_RSRC_LOC_CACHED));
 709     }
 710
 711     UINT_32 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const
 712     {
 713         UINT_32 numPipeLog2 = pipeAligned ? Min(m_pipesLog2 + m_seLog2, 5u) : 0;
 714
 715         if (IsXor(swizzleMode))
 716         {
 717             UINT_32 maxPipeLog2 = GetBlockSizeLog2(swizzleMode) - m_pipeInterleaveLog2;
 718
 719             numPipeLog2 = Min(numPipeLog2, maxPipeLog2);
 720         }
 721
 722         return numPipeLog2;
 723     }
 724
 725     UINT_32 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const
 726     {
 727         return (1 << GetPipeLog2ForMetaAddressing(pipeAligned, swizzleMode));
 728     }
 729
 730     VOID VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
 731     {
 732 #if DEBUG
 733         if (pIn->numMipLevels > 1)
 734         {
 735             UINT_32 actualMipLevels = 1;
 736             switch (pIn->resourceType)
 737             {
 738                 case ADDR_RSRC_TEX_3D:
 739                     // Fall through to share 2D case
 740                     actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->numSlices) + 1);
 741                 case ADDR_RSRC_TEX_2D:
 742                     // Fall through to share 1D case
 743                     actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->height) + 1);
 744                 case ADDR_RSRC_TEX_1D:
 745                     // Base 1D case
 746                     actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->width) + 1);
 747                     break;
 748                 default:
 749                     ADDR_ASSERT_ALWAYS();
 750                     break;
 751             }
 752             // Client pass wrong number of MipLevels to addrlib and result will be bad.
 753             // Not sure if we should fail this calling instead of putting an assertion here.
 754             ADDR_ASSERT(actualMipLevels >= pIn->numMipLevels);
 755         }
 756 #endif
 757     }
 758
 759     ADDR_E_RETURNCODE ApplyCustomerPipeBankXor(
 760         AddrSwizzleMode swizzleMode,
 761         UINT_32         pipeBankXor,
 762         UINT_32         bankBits,
 763         UINT_32         pipeBits,
 764         UINT_32*        pBlockOffset) const
 765     {
 766         ADDR_E_RETURNCODE returnCode = ADDR_OK;
 767
 768         if (IsXor(swizzleMode))
 769         {
 770             // Apply driver set bankPipeXor
 771             UINT_32 bankX = 0;
 772             UINT_32 pipeX = 0;
 773             returnCode = ExtractPipeBankXor(pipeBankXor, bankBits, pipeBits, &bankX, &pipeX);
 774             *pBlockOffset ^= (pipeX << m_pipeInterleaveLog2);
 775             *pBlockOffset ^= (bankX << (m_pipeInterleaveLog2 + pipeBits));
 776         }
 777
 778         return returnCode;
 779     }
 780
 781     UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const;
 782
 783     ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
 784         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
 785         UINT_32                                 elementBytes,
 786         UINT_32                                 pitchAlignInElement,
 787         UINT_32*                                pPitch,
 788         UINT_32*                                pHeight) const;
 789
 790     VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
 791
 792     UINT_32 m_se;                       ///< Number of shader engine
 793     UINT_32 m_rbPerSe;                  ///< Number of render backend per shader engine
 794     UINT_32 m_maxCompFrag;              ///< Number of max compressed fragment
 795
 796     UINT_32 m_banksLog2;                ///< Number of bank Log2
 797     UINT_32 m_pipesLog2;                ///< Number of pipe per shader engine Log2
 798     UINT_32 m_seLog2;                   ///< Number of shader engine Log2
 799     UINT_32 m_rbPerSeLog2;              ///< Number of render backend per shader engine Log2
 800     UINT_32 m_maxCompFragLog2;          ///< Number of max compressed fragment Log2
 801
 802     UINT_32 m_pipeInterleaveLog2;       ///< Log2 of pipe interleave bytes
 803
 804     UINT_32 m_blockVarSizeLog2;         ///< Log2 of block var size
 805
 806     SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE];  ///< Swizzle mode table
 807
 808 private:
 809     // Disallow the copy constructor
 810     Lib(const Lib& a);
 811
 812     // Disallow the assignment operator
 813     Lib& operator=(const Lib& a);
 814 };
 815
 816 } // V2
 817 } // Addr
 818
 819 #endif
 820