src/amd/common/ac_binary.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "ac_gpu_info.h"
  25 #include "ac_binary.h"
  26
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29
  30 #include <gelf.h>
  31 #include <libelf.h>
  32 #include <stdio.h>
  33
  34 #include <sid.h>
  35
  36 #define SPILLED_SGPRS                                     0x4
  37 #define SPILLED_VGPRS                                     0x8
  38
  39 /* Parse configuration data in .AMDGPU.config section format. */
  40 void ac_parse_shader_binary_config(const char *data, size_t nbytes,
  41                                    unsigned wave_size,
  42                                    bool really_needs_scratch,
  43                                    const struct radeon_info *info,
  44                                    struct ac_shader_config *conf)
  45 {
  46         uint32_t scratch_size = 0;
  47
  48         for (size_t i = 0; i < nbytes; i += 8) {
  49                 unsigned reg = util_le32_to_cpu(*(uint32_t*)(data + i));
  50                 unsigned value = util_le32_to_cpu(*(uint32_t*)(data + i + 4));
  51                 switch (reg) {
  52                 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
  53                 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
  54                 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
  55                 case R_00B848_COMPUTE_PGM_RSRC1:
  56                 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
  57                         if (wave_size == 32)
  58                                 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
  59                         else
  60                                 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
  61
  62                         conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
  63                         /* TODO: LLVM doesn't set FLOAT_MODE for non-compute shaders */
  64                         conf->float_mode =  G_00B028_FLOAT_MODE(value);
  65                         conf->rsrc1 = value;
  66                         break;
  67                 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
  68                         conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
  69                         /* TODO: LLVM doesn't set SHARED_VGPR_CNT for all shader types */
  70                         conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
  71                         conf->rsrc2 = value;
  72                         break;
  73                 case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
  74                         conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
  75                         conf->rsrc2 = value;
  76                         break;
  77                 case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
  78                         conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
  79                         conf->rsrc2 = value;
  80                         break;
  81                 case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
  82                         conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
  83                         conf->rsrc2 = value;
  84                         break;
  85                 case R_00B84C_COMPUTE_PGM_RSRC2:
  86                         conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
  87                         conf->rsrc2 = value;
  88                         break;
  89                 case R_00B8A0_COMPUTE_PGM_RSRC3:
  90                         conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
  91                         conf->rsrc3 = value;
  92                         break;
  93                 case R_0286CC_SPI_PS_INPUT_ENA:
  94                         conf->spi_ps_input_ena = value;
  95                         break;
  96                 case R_0286D0_SPI_PS_INPUT_ADDR:
  97                         conf->spi_ps_input_addr = value;
  98                         break;
  99                 case R_0286E8_SPI_TMPRING_SIZE:
 100                 case R_00B860_COMPUTE_TMPRING_SIZE:
 101                         /* WAVESIZE is in units of 256 dwords. */
 102                         scratch_size = value;
 103                         break;
 104                 case SPILLED_SGPRS:
 105                         conf->spilled_sgprs = value;
 106                         break;
 107                 case SPILLED_VGPRS:
 108                         conf->spilled_vgprs = value;
 109                         break;
 110                 default:
 111                         {
 112                                 static bool printed;
 113
 114                                 if (!printed) {
 115                                         fprintf(stderr, "Warning: LLVM emitted unknown "
 116                                                 "config register: 0x%x\n", reg);
 117                                         printed = true;
 118                                 }
 119                         }
 120                         break;
 121                 }
 122         }
 123
 124         if (!conf->spi_ps_input_addr)
 125                 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
 126
 127         if (really_needs_scratch) {
 128                 /* sgprs spills aren't spilling */
 129                 conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(scratch_size) * 256 * 4;
 130         }
 131
 132         /* GFX 10.3 internally:
 133          * - aligns VGPRS to 16 for Wave32 and 8 for Wave64
 134          * - aligns LDS to 1024
 135          *
 136          * For shader-db stats, set num_vgprs that the hw actually uses.
 137          */
 138         if (info->chip_class >= GFX10_3) {
 139                 conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8);
 140         }
 141
 142         /* Enable 64-bit and 16-bit denormals, because there is no performance
 143          * cost.
 144          *
 145          * Don't enable denormals for 32-bit floats, because:
 146          * - denormals disable output modifiers
 147          * - denormals break v_mad_f32
 148          * - GFX6 & GFX7 would be very slow
 149          */
 150         conf->float_mode &= ~V_00B028_FP_ALL_DENORMS;
 151         conf->float_mode |= V_00B028_FP_64_DENORMS;
 152 }