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amd/common: use generated register header
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "sid.h"
28
29 #include "util/u_math.h"
30
31 #include <stdio.h>
32
33 #include <xf86drm.h>
34 #include <amdgpu_drm.h>
35
36 #include <amdgpu.h>
37
38 #define CIK_TILE_MODE_COLOR_2D 14
39
40 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
41 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
55
56 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
57 {
58 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
59
60 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
61 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
62 return 2;
63 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
67 return 4;
68 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
75 return 8;
76 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
78 return 16;
79 default:
80 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
81 assert(!"this should never occur");
82 return 2;
83 }
84 }
85
86 static bool has_syncobj(int fd)
87 {
88 uint64_t value;
89 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
90 return false;
91 return value ? true : false;
92 }
93
94 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
95 struct radeon_info *info,
96 struct amdgpu_gpu_info *amdinfo)
97 {
98 struct drm_amdgpu_info_device device_info = {};
99 struct amdgpu_buffer_size_alignments alignment_info = {};
100 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
101 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
102 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
103 struct amdgpu_gds_resource_info gds = {};
104 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
105 int r, i, j;
106 drmDevicePtr devinfo;
107
108 /* Get PCI info. */
109 r = drmGetDevice2(fd, 0, &devinfo);
110 if (r) {
111 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
112 return false;
113 }
114 info->pci_domain = devinfo->businfo.pci->domain;
115 info->pci_bus = devinfo->businfo.pci->bus;
116 info->pci_dev = devinfo->businfo.pci->dev;
117 info->pci_func = devinfo->businfo.pci->func;
118 drmFreeDevice(&devinfo);
119
120 /* Query hardware and driver information. */
121 r = amdgpu_query_gpu_info(dev, amdinfo);
122 if (r) {
123 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
124 return false;
125 }
126
127 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
128 &device_info);
129 if (r) {
130 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
131 return false;
132 }
133
134 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
135 if (r) {
136 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
137 return false;
138 }
139
140 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
141 if (r) {
142 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
143 return false;
144 }
145
146 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
147 if (r) {
148 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
149 return false;
150 }
151
152 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
153 if (r) {
154 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
155 return false;
156 }
157
158 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
159 if (r) {
160 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
161 return false;
162 }
163
164 if (info->drm_major == 3 && info->drm_minor >= 17) {
165 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
166 if (r) {
167 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
168 return false;
169 }
170 }
171
172 if (info->drm_major == 3 && info->drm_minor >= 17) {
173 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
174 if (r) {
175 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
176 return false;
177 }
178 }
179
180 if (info->drm_major == 3 && info->drm_minor >= 17) {
181 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
182 if (r) {
183 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
184 return false;
185 }
186 }
187
188 if (info->drm_major == 3 && info->drm_minor >= 27) {
189 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
190 if (r) {
191 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
192 return false;
193 }
194 }
195
196 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
197 &info->me_fw_version,
198 &info->me_fw_feature);
199 if (r) {
200 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
201 return false;
202 }
203
204 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
205 &info->pfp_fw_version,
206 &info->pfp_fw_feature);
207 if (r) {
208 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
209 return false;
210 }
211
212 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
213 &info->ce_fw_version,
214 &info->ce_fw_feature);
215 if (r) {
216 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
217 return false;
218 }
219
220 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
221 &uvd_version, &uvd_feature);
222 if (r) {
223 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
224 return false;
225 }
226
227 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
228 if (r) {
229 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
230 return false;
231 }
232
233 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
234 &vce_version, &vce_feature);
235 if (r) {
236 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
237 return false;
238 }
239
240 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
241 if (r) {
242 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
243 return false;
244 }
245
246 r = amdgpu_query_gds_info(dev, &gds);
247 if (r) {
248 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
249 return false;
250 }
251
252 if (info->drm_minor >= 9) {
253 struct drm_amdgpu_memory_info meminfo = {};
254
255 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
256 if (r) {
257 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
258 return false;
259 }
260
261 /* Note: usable_heap_size values can be random and can't be relied on. */
262 info->gart_size = meminfo.gtt.total_heap_size;
263 info->vram_size = meminfo.vram.total_heap_size;
264 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
265 } else {
266 /* This is a deprecated interface, which reports usable sizes
267 * (total minus pinned), but the pinned size computation is
268 * buggy, so the values returned from these functions can be
269 * random.
270 */
271 struct amdgpu_heap_info vram, vram_vis, gtt;
272
273 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
274 if (r) {
275 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
276 return false;
277 }
278
279 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
280 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
281 &vram_vis);
282 if (r) {
283 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
284 return false;
285 }
286
287 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
288 if (r) {
289 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
290 return false;
291 }
292
293 info->gart_size = gtt.heap_size;
294 info->vram_size = vram.heap_size;
295 info->vram_vis_size = vram_vis.heap_size;
296 }
297
298 /* Set chip identification. */
299 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
300 info->vce_harvest_config = amdinfo->vce_harvest_config;
301
302 switch (info->pci_id) {
303 #define CHIPSET(pci_id, cfamily) \
304 case pci_id: \
305 info->family = CHIP_##cfamily; \
306 info->name = #cfamily; \
307 break;
308 #include "pci_ids/radeonsi_pci_ids.h"
309 #undef CHIPSET
310
311 default:
312 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
313 return false;
314 }
315
316 /* Raven2 uses the same PCI IDs as Raven1, but different revision IDs. */
317 if (info->family == CHIP_RAVEN && amdinfo->chip_rev >= 0x8) {
318 info->family = CHIP_RAVEN2;
319 info->name = "RAVEN2";
320 }
321
322 if (info->family >= CHIP_VEGA10)
323 info->chip_class = GFX9;
324 else if (info->family >= CHIP_TONGA)
325 info->chip_class = GFX8;
326 else if (info->family >= CHIP_BONAIRE)
327 info->chip_class = GFX7;
328 else if (info->family >= CHIP_TAHITI)
329 info->chip_class = GFX6;
330 else {
331 fprintf(stderr, "amdgpu: Unknown family.\n");
332 return false;
333 }
334
335 info->marketing_name = amdgpu_get_marketing_name(dev);
336 info->is_pro_graphics = info->marketing_name &&
337 (!strcmp(info->marketing_name, "Pro") ||
338 !strcmp(info->marketing_name, "PRO") ||
339 !strcmp(info->marketing_name, "Frontier"));
340
341 /* Set which chips have dedicated VRAM. */
342 info->has_dedicated_vram =
343 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
344
345 /* The kernel can split large buffers in VRAM but not in GTT, so large
346 * allocations can fail or cause buffer movement failures in the kernel.
347 */
348 if (info->has_dedicated_vram)
349 info->max_alloc_size = info->vram_size * 0.8;
350 else
351 info->max_alloc_size = info->gart_size * 0.7;
352
353 /* Set hardware information. */
354 info->gds_size = gds.gds_total_size;
355 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
356 /* convert the shader clock from KHz to MHz */
357 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
358 info->num_tcc_blocks = device_info.num_tcc_blocks;
359 info->max_se = amdinfo->num_shader_engines;
360 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
361 info->has_hw_decode =
362 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
363 (vcn_jpeg.available_rings != 0);
364 info->uvd_fw_version =
365 uvd.available_rings ? uvd_version : 0;
366 info->vce_fw_version =
367 vce.available_rings ? vce_version : 0;
368 info->uvd_enc_supported =
369 uvd_enc.available_rings ? true : false;
370 info->has_userptr = true;
371 info->has_syncobj = has_syncobj(fd);
372 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
373 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
374 info->has_ctx_priority = info->drm_minor >= 22;
375 info->has_local_buffers = info->drm_minor >= 20;
376 info->kernel_flushes_hdp_before_ib = true;
377 info->htile_cmask_support_1d_tiling = true;
378 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
379 info->has_bo_metadata = true;
380 info->has_gpu_reset_status_query = true;
381 info->has_eqaa_surface_allocator = true;
382 info->has_format_bc1_through_bc7 = true;
383 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
384 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
385 info->drm_minor >= 2;
386 info->has_indirect_compute_dispatch = true;
387 /* GFX6 doesn't support unaligned loads. */
388 info->has_unaligned_shader_loads = info->chip_class != GFX6;
389 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
390 * these faults are mitigated in software.
391 * Disable sparse mappings on GFX9 due to hangs.
392 */
393 info->has_sparse_vm_mappings =
394 info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
395 info->drm_minor >= 13;
396 info->has_2d_tiling = true;
397 info->has_read_registers_query = true;
398 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
399
400 info->num_render_backends = amdinfo->rb_pipes;
401 /* The value returned by the kernel driver was wrong. */
402 if (info->family == CHIP_KAVERI)
403 info->num_render_backends = 2;
404
405 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
406 if (!info->clock_crystal_freq) {
407 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
408 info->clock_crystal_freq = 1;
409 }
410 info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
411 info->gb_addr_config = amdinfo->gb_addr_cfg;
412 if (info->chip_class == GFX9) {
413 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
414 info->pipe_interleave_bytes =
415 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
416 } else {
417 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
418 info->pipe_interleave_bytes =
419 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
420 }
421 info->r600_has_virtual_memory = true;
422
423 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
424 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
425
426 info->num_sdma_rings = util_bitcount(dma.available_rings);
427 info->num_compute_rings = util_bitcount(compute.available_rings);
428
429 /* Get the number of good compute units. */
430 info->num_good_compute_units = 0;
431 for (i = 0; i < info->max_se; i++)
432 for (j = 0; j < info->max_sh_per_se; j++)
433 info->num_good_compute_units +=
434 util_bitcount(amdinfo->cu_bitmap[i][j]);
435 info->num_good_cu_per_sh = info->num_good_compute_units /
436 (info->max_se * info->max_sh_per_se);
437
438 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
439 sizeof(amdinfo->gb_tile_mode));
440 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
441
442 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
443 sizeof(amdinfo->gb_macro_tile_mode));
444
445 info->pte_fragment_size = alignment_info.size_local;
446 info->gart_page_size = alignment_info.size_remote;
447
448 if (info->chip_class == GFX6)
449 info->gfx_ib_pad_with_type2 = TRUE;
450
451 unsigned ib_align = 0;
452 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
453 ib_align = MAX2(ib_align, compute.ib_start_alignment);
454 ib_align = MAX2(ib_align, dma.ib_start_alignment);
455 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
456 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
457 ib_align = MAX2(ib_align, vce.ib_start_alignment);
458 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
459 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
460 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
461 assert(ib_align);
462 info->ib_start_alignment = ib_align;
463
464 if (info->drm_minor >= 31 &&
465 (info->family == CHIP_RAVEN ||
466 info->family == CHIP_RAVEN2)) {
467 if (info->num_render_backends == 1)
468 info->use_display_dcc_unaligned = true;
469 else
470 info->use_display_dcc_with_retile_blit = true;
471 }
472
473 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
474 info->drm_minor >= 29 &&
475 HAVE_LLVM >= 0x0800;
476 return true;
477 }
478
479 void ac_compute_driver_uuid(char *uuid, size_t size)
480 {
481 char amd_uuid[] = "AMD-MESA-DRV";
482
483 assert(size >= sizeof(amd_uuid));
484
485 memset(uuid, 0, size);
486 strncpy(uuid, amd_uuid, size);
487 }
488
489 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
490 {
491 uint32_t *uint_uuid = (uint32_t*)uuid;
492
493 assert(size >= sizeof(uint32_t)*4);
494
495 /**
496 * Use the device info directly instead of using a sha1. GL/VK UUIDs
497 * are 16 byte vs 20 byte for sha1, and the truncation that would be
498 * required would get rid of part of the little entropy we have.
499 * */
500 memset(uuid, 0, size);
501 uint_uuid[0] = info->pci_domain;
502 uint_uuid[1] = info->pci_bus;
503 uint_uuid[2] = info->pci_dev;
504 uint_uuid[3] = info->pci_func;
505 }
506
507 void ac_print_gpu_info(struct radeon_info *info)
508 {
509 printf("Device info:\n");
510 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
511 info->pci_domain, info->pci_bus,
512 info->pci_dev, info->pci_func);
513 printf(" pci_id = 0x%x\n", info->pci_id);
514 printf(" family = %i\n", info->family);
515 printf(" chip_class = %i\n", info->chip_class);
516 printf(" num_compute_rings = %u\n", info->num_compute_rings);
517 printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
518 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
519 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
520
521 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
522 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
523
524 printf("Memory info:\n");
525 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
526 printf(" gart_page_size = %u\n", info->gart_page_size);
527 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
528 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
529 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
530 printf(" gds_size = %u kB\n", info->gds_size / 1024);
531 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
532 printf(" max_alloc_size = %i MB\n",
533 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
534 printf(" min_alloc_size = %u\n", info->min_alloc_size);
535 printf(" address32_hi = %u\n", info->address32_hi);
536 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
537
538 printf("CP info:\n");
539 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
540 printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
541 printf(" me_fw_version = %i\n", info->me_fw_version);
542 printf(" me_fw_feature = %i\n", info->me_fw_feature);
543 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
544 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
545 printf(" ce_fw_version = %i\n", info->ce_fw_version);
546 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
547
548 printf("Multimedia info:\n");
549 printf(" has_hw_decode = %u\n", info->has_hw_decode);
550 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
551 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
552 printf(" vce_fw_version = %u\n", info->vce_fw_version);
553 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
554
555 printf("Kernel & winsys capabilities:\n");
556 printf(" drm = %i.%i.%i\n", info->drm_major,
557 info->drm_minor, info->drm_patchlevel);
558 printf(" has_userptr = %i\n", info->has_userptr);
559 printf(" has_syncobj = %u\n", info->has_syncobj);
560 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
561 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
562 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
563 printf(" has_local_buffers = %u\n", info->has_local_buffers);
564 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
565 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
566 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
567 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
568 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
569 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
570 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
571 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
572 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
573 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
574 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
575 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
576 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
577 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
578 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
579
580 printf("Shader core info:\n");
581 printf(" max_shader_clock = %i\n", info->max_shader_clock);
582 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
583 printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
584 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
585 printf(" max_se = %i\n", info->max_se);
586 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
587
588 printf("Render backend info:\n");
589 printf(" num_render_backends = %i\n", info->num_render_backends);
590 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
591 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
592 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
593 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
594
595 printf("GB_ADDR_CONFIG:\n");
596 if (info->chip_class >= GFX9) {
597 printf(" num_pipes = %u\n",
598 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
599 printf(" pipe_interleave_size = %u\n",
600 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
601 printf(" max_compressed_frags = %u\n",
602 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
603 printf(" bank_interleave_size = %u\n",
604 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
605 printf(" num_banks = %u\n",
606 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
607 printf(" shader_engine_tile_size = %u\n",
608 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
609 printf(" num_shader_engines = %u\n",
610 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
611 printf(" num_gpus = %u (raw)\n",
612 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
613 printf(" multi_gpu_tile_size = %u (raw)\n",
614 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
615 printf(" num_rb_per_se = %u\n",
616 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
617 printf(" row_size = %u\n",
618 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
619 printf(" num_lower_pipes = %u (raw)\n",
620 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
621 printf(" se_enable = %u (raw)\n",
622 G_0098F8_SE_ENABLE(info->gb_addr_config));
623 } else {
624 printf(" num_pipes = %u\n",
625 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
626 printf(" pipe_interleave_size = %u\n",
627 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
628 printf(" bank_interleave_size = %u\n",
629 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
630 printf(" num_shader_engines = %u\n",
631 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
632 printf(" shader_engine_tile_size = %u\n",
633 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
634 printf(" num_gpus = %u (raw)\n",
635 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
636 printf(" multi_gpu_tile_size = %u (raw)\n",
637 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
638 printf(" row_size = %u\n",
639 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
640 printf(" num_lower_pipes = %u (raw)\n",
641 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
642 }
643 }
644
645 int
646 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
647 {
648 if (chip_class >= GFX9)
649 return -1;
650
651 switch (family) {
652 case CHIP_OLAND:
653 case CHIP_HAINAN:
654 case CHIP_KAVERI:
655 case CHIP_KABINI:
656 case CHIP_ICELAND:
657 case CHIP_CARRIZO:
658 case CHIP_STONEY:
659 return 16;
660 case CHIP_TAHITI:
661 case CHIP_PITCAIRN:
662 case CHIP_VERDE:
663 case CHIP_BONAIRE:
664 case CHIP_HAWAII:
665 case CHIP_TONGA:
666 case CHIP_FIJI:
667 case CHIP_POLARIS10:
668 case CHIP_POLARIS11:
669 case CHIP_POLARIS12:
670 case CHIP_VEGAM:
671 return 32;
672 default:
673 unreachable("Unknown GPU");
674 }
675 }
676
677 void
678 ac_get_raster_config(struct radeon_info *info,
679 uint32_t *raster_config_p,
680 uint32_t *raster_config_1_p,
681 uint32_t *se_tile_repeat_p)
682 {
683 unsigned raster_config, raster_config_1, se_tile_repeat;
684
685 switch (info->family) {
686 /* 1 SE / 1 RB */
687 case CHIP_HAINAN:
688 case CHIP_KABINI:
689 case CHIP_STONEY:
690 raster_config = 0x00000000;
691 raster_config_1 = 0x00000000;
692 break;
693 /* 1 SE / 4 RBs */
694 case CHIP_VERDE:
695 raster_config = 0x0000124a;
696 raster_config_1 = 0x00000000;
697 break;
698 /* 1 SE / 2 RBs (Oland is special) */
699 case CHIP_OLAND:
700 raster_config = 0x00000082;
701 raster_config_1 = 0x00000000;
702 break;
703 /* 1 SE / 2 RBs */
704 case CHIP_KAVERI:
705 case CHIP_ICELAND:
706 case CHIP_CARRIZO:
707 raster_config = 0x00000002;
708 raster_config_1 = 0x00000000;
709 break;
710 /* 2 SEs / 4 RBs */
711 case CHIP_BONAIRE:
712 case CHIP_POLARIS11:
713 case CHIP_POLARIS12:
714 raster_config = 0x16000012;
715 raster_config_1 = 0x00000000;
716 break;
717 /* 2 SEs / 8 RBs */
718 case CHIP_TAHITI:
719 case CHIP_PITCAIRN:
720 raster_config = 0x2a00126a;
721 raster_config_1 = 0x00000000;
722 break;
723 /* 4 SEs / 8 RBs */
724 case CHIP_TONGA:
725 case CHIP_POLARIS10:
726 raster_config = 0x16000012;
727 raster_config_1 = 0x0000002a;
728 break;
729 /* 4 SEs / 16 RBs */
730 case CHIP_HAWAII:
731 case CHIP_FIJI:
732 case CHIP_VEGAM:
733 raster_config = 0x3a00161a;
734 raster_config_1 = 0x0000002e;
735 break;
736 default:
737 fprintf(stderr,
738 "ac: Unknown GPU, using 0 for raster_config\n");
739 raster_config = 0x00000000;
740 raster_config_1 = 0x00000000;
741 break;
742 }
743
744 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
745 * This decreases performance by up to 50% when the RB is the bottleneck.
746 */
747 if (info->family == CHIP_KAVERI && info->drm_major == 2)
748 raster_config = 0x00000000;
749
750 /* Fiji: Old kernels have incorrect tiling config. This decreases
751 * RB performance by 25%. (it disables 1 RB in the second packer)
752 */
753 if (info->family == CHIP_FIJI &&
754 info->cik_macrotile_mode_array[0] == 0x000000e8) {
755 raster_config = 0x16000012;
756 raster_config_1 = 0x0000002a;
757 }
758
759 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
760 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
761
762 /* I don't know how to calculate this, though this is probably a good guess. */
763 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
764
765 *raster_config_p = raster_config;
766 *raster_config_1_p = raster_config_1;
767 if (se_tile_repeat_p)
768 *se_tile_repeat_p = se_tile_repeat;
769 }
770
771 void
772 ac_get_harvested_configs(struct radeon_info *info,
773 unsigned raster_config,
774 unsigned *cik_raster_config_1_p,
775 unsigned *raster_config_se)
776 {
777 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
778 unsigned num_se = MAX2(info->max_se, 1);
779 unsigned rb_mask = info->enabled_rb_mask;
780 unsigned num_rb = MIN2(info->num_render_backends, 16);
781 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
782 unsigned rb_per_se = num_rb / num_se;
783 unsigned se_mask[4];
784 unsigned se;
785
786 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
787 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
788 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
789 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
790
791 assert(num_se == 1 || num_se == 2 || num_se == 4);
792 assert(sh_per_se == 1 || sh_per_se == 2);
793 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
794
795
796 if (info->chip_class >= GFX7) {
797 unsigned raster_config_1 = *cik_raster_config_1_p;
798 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
799 (!se_mask[2] && !se_mask[3]))) {
800 raster_config_1 &= C_028354_SE_PAIR_MAP;
801
802 if (!se_mask[0] && !se_mask[1]) {
803 raster_config_1 |=
804 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
805 } else {
806 raster_config_1 |=
807 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
808 }
809 *cik_raster_config_1_p = raster_config_1;
810 }
811 }
812
813 for (se = 0; se < num_se; se++) {
814 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
815 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
816 int idx = (se / 2) * 2;
817
818 raster_config_se[se] = raster_config;
819 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
820 raster_config_se[se] &= C_028350_SE_MAP;
821
822 if (!se_mask[idx]) {
823 raster_config_se[se] |=
824 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
825 } else {
826 raster_config_se[se] |=
827 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
828 }
829 }
830
831 pkr0_mask &= rb_mask;
832 pkr1_mask &= rb_mask;
833 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
834 raster_config_se[se] &= C_028350_PKR_MAP;
835
836 if (!pkr0_mask) {
837 raster_config_se[se] |=
838 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
839 } else {
840 raster_config_se[se] |=
841 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
842 }
843 }
844
845 if (rb_per_se >= 2) {
846 unsigned rb0_mask = 1 << (se * rb_per_se);
847 unsigned rb1_mask = rb0_mask << 1;
848
849 rb0_mask &= rb_mask;
850 rb1_mask &= rb_mask;
851 if (!rb0_mask || !rb1_mask) {
852 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
853
854 if (!rb0_mask) {
855 raster_config_se[se] |=
856 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
857 } else {
858 raster_config_se[se] |=
859 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
860 }
861 }
862
863 if (rb_per_se > 2) {
864 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
865 rb1_mask = rb0_mask << 1;
866 rb0_mask &= rb_mask;
867 rb1_mask &= rb_mask;
868 if (!rb0_mask || !rb1_mask) {
869 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
870
871 if (!rb0_mask) {
872 raster_config_se[se] |=
873 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
874 } else {
875 raster_config_se[se] |=
876 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
877 }
878 }
879 }
880 }
881 }
882 }