ac/gpu_info: set num_tiles_pipes on gfx10+ too
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "addrlib/src/amdgpu_asic_addr.h"
28 #include "sid.h"
29
30 #include "util/macros.h"
31 #include "util/u_math.h"
32
33 #include <stdio.h>
34
35 #include <xf86drm.h>
36 #include "drm-uapi/amdgpu_drm.h"
37
38 #include <amdgpu.h>
39
40 #define CIK_TILE_MODE_COLOR_2D 14
41
42 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57
58 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
59 {
60 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
61
62 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
63 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
64 return 2;
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
68 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
69 return 4;
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
77 return 8;
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
80 return 16;
81 default:
82 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
83 assert(!"this should never occur");
84 return 2;
85 }
86 }
87
88 static bool has_syncobj(int fd)
89 {
90 uint64_t value;
91 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
92 return false;
93 return value ? true : false;
94 }
95
96 static bool has_timeline_syncobj(int fd)
97 {
98 uint64_t value;
99 if (drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &value))
100 return false;
101 return value ? true : false;
102 }
103
104 static uint64_t fix_vram_size(uint64_t size)
105 {
106 /* The VRAM size is underreported, so we need to fix it, because
107 * it's used to compute the number of memory modules for harvesting.
108 */
109 return align64(size, 256*1024*1024);
110 }
111
112 static uint32_t
113 get_l2_cache_size(enum radeon_family family)
114 {
115 switch (family) {
116 case CHIP_KABINI:
117 case CHIP_STONEY:
118 return 128 * 1024;
119 case CHIP_OLAND:
120 case CHIP_HAINAN:
121 case CHIP_ICELAND:
122 return 256 * 1024;
123 case CHIP_PITCAIRN:
124 case CHIP_VERDE:
125 case CHIP_BONAIRE:
126 case CHIP_KAVERI:
127 case CHIP_POLARIS12:
128 case CHIP_CARRIZO:
129 return 512 * 1024;
130 case CHIP_TAHITI:
131 case CHIP_TONGA:
132 return 768 * 1024;
133 break;
134 case CHIP_HAWAII:
135 case CHIP_POLARIS11:
136 return 1024 * 1024;
137 case CHIP_FIJI:
138 case CHIP_POLARIS10:
139 return 2048 * 1024;
140 break;
141 default:
142 return 4096 * 1024;
143 }
144 }
145
146 bool ac_query_gpu_info(int fd, void *dev_p,
147 struct radeon_info *info,
148 struct amdgpu_gpu_info *amdinfo)
149 {
150 struct drm_amdgpu_info_device device_info = {};
151 struct amdgpu_buffer_size_alignments alignment_info = {};
152 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
153 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
154 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
155 struct amdgpu_gds_resource_info gds = {};
156 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
157 int r, i, j;
158 amdgpu_device_handle dev = dev_p;
159 drmDevicePtr devinfo;
160
161 /* Get PCI info. */
162 r = drmGetDevice2(fd, 0, &devinfo);
163 if (r) {
164 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
165 return false;
166 }
167 info->pci_domain = devinfo->businfo.pci->domain;
168 info->pci_bus = devinfo->businfo.pci->bus;
169 info->pci_dev = devinfo->businfo.pci->dev;
170 info->pci_func = devinfo->businfo.pci->func;
171 drmFreeDevice(&devinfo);
172
173 assert(info->drm_major == 3);
174 info->is_amdgpu = true;
175
176 /* Query hardware and driver information. */
177 r = amdgpu_query_gpu_info(dev, amdinfo);
178 if (r) {
179 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
180 return false;
181 }
182
183 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
184 &device_info);
185 if (r) {
186 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
187 return false;
188 }
189
190 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
191 if (r) {
192 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
193 return false;
194 }
195
196 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
197 if (r) {
198 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
199 return false;
200 }
201
202 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
203 if (r) {
204 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
205 return false;
206 }
207
208 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
209 if (r) {
210 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
211 return false;
212 }
213
214 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
215 if (r) {
216 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
217 return false;
218 }
219
220 if (info->drm_minor >= 17) {
221 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
222 if (r) {
223 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
224 return false;
225 }
226 }
227
228 if (info->drm_minor >= 17) {
229 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
230 if (r) {
231 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
232 return false;
233 }
234 }
235
236 if (info->drm_minor >= 17) {
237 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
238 if (r) {
239 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
240 return false;
241 }
242 }
243
244 if (info->drm_minor >= 27) {
245 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
246 if (r) {
247 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
248 return false;
249 }
250 }
251
252 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
253 &info->me_fw_version,
254 &info->me_fw_feature);
255 if (r) {
256 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
257 return false;
258 }
259
260 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
261 &info->pfp_fw_version,
262 &info->pfp_fw_feature);
263 if (r) {
264 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
265 return false;
266 }
267
268 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
269 &info->ce_fw_version,
270 &info->ce_fw_feature);
271 if (r) {
272 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
273 return false;
274 }
275
276 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
277 &uvd_version, &uvd_feature);
278 if (r) {
279 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
280 return false;
281 }
282
283 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
284 if (r) {
285 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
286 return false;
287 }
288
289 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
290 &vce_version, &vce_feature);
291 if (r) {
292 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
293 return false;
294 }
295
296 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
297 if (r) {
298 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
299 return false;
300 }
301
302 r = amdgpu_query_gds_info(dev, &gds);
303 if (r) {
304 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
305 return false;
306 }
307
308 if (info->drm_minor >= 9) {
309 struct drm_amdgpu_memory_info meminfo = {};
310
311 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
312 if (r) {
313 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
314 return false;
315 }
316
317 /* Note: usable_heap_size values can be random and can't be relied on. */
318 info->gart_size = meminfo.gtt.total_heap_size;
319 info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
320 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
321 } else {
322 /* This is a deprecated interface, which reports usable sizes
323 * (total minus pinned), but the pinned size computation is
324 * buggy, so the values returned from these functions can be
325 * random.
326 */
327 struct amdgpu_heap_info vram, vram_vis, gtt;
328
329 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
330 if (r) {
331 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
332 return false;
333 }
334
335 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
336 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
337 &vram_vis);
338 if (r) {
339 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
340 return false;
341 }
342
343 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
344 if (r) {
345 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
346 return false;
347 }
348
349 info->gart_size = gtt.heap_size;
350 info->vram_size = fix_vram_size(vram.heap_size);
351 info->vram_vis_size = vram_vis.heap_size;
352 }
353
354 /* Set chip identification. */
355 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
356 info->pci_rev_id = amdinfo->pci_rev_id;
357 info->vce_harvest_config = amdinfo->vce_harvest_config;
358
359 #define identify_chip2(asic, chipname) \
360 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
361 info->family = CHIP_##chipname; \
362 info->name = #chipname; \
363 }
364 #define identify_chip(chipname) identify_chip2(chipname, chipname)
365
366 switch (amdinfo->family_id) {
367 case FAMILY_SI:
368 identify_chip(TAHITI);
369 identify_chip(PITCAIRN);
370 identify_chip2(CAPEVERDE, VERDE);
371 identify_chip(OLAND);
372 identify_chip(HAINAN);
373 break;
374 case FAMILY_CI:
375 identify_chip(BONAIRE);
376 identify_chip(HAWAII);
377 break;
378 case FAMILY_KV:
379 identify_chip2(SPECTRE, KAVERI);
380 identify_chip2(SPOOKY, KAVERI);
381 identify_chip2(KALINDI, KABINI);
382 identify_chip2(GODAVARI, KABINI);
383 break;
384 case FAMILY_VI:
385 identify_chip(ICELAND);
386 identify_chip(TONGA);
387 identify_chip(FIJI);
388 identify_chip(POLARIS10);
389 identify_chip(POLARIS11);
390 identify_chip(POLARIS12);
391 identify_chip(VEGAM);
392 break;
393 case FAMILY_CZ:
394 identify_chip(CARRIZO);
395 identify_chip(STONEY);
396 break;
397 case FAMILY_AI:
398 identify_chip(VEGA10);
399 identify_chip(VEGA12);
400 identify_chip(VEGA20);
401 identify_chip(ARCTURUS);
402 break;
403 case FAMILY_RV:
404 identify_chip(RAVEN);
405 identify_chip(RAVEN2);
406 identify_chip(RENOIR);
407 break;
408 case FAMILY_NV:
409 identify_chip(NAVI10);
410 identify_chip(NAVI12);
411 identify_chip(NAVI14);
412 identify_chip(SIENNA_CICHLID);
413 identify_chip(NAVY_FLOUNDER);
414 break;
415 }
416
417 if (!info->name) {
418 fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
419 amdinfo->family_id, amdinfo->chip_external_rev);
420 return false;
421 }
422
423 if (info->family >= CHIP_SIENNA_CICHLID)
424 info->chip_class = GFX10_3;
425 else if (info->family >= CHIP_NAVI10)
426 info->chip_class = GFX10;
427 else if (info->family >= CHIP_VEGA10)
428 info->chip_class = GFX9;
429 else if (info->family >= CHIP_TONGA)
430 info->chip_class = GFX8;
431 else if (info->family >= CHIP_BONAIRE)
432 info->chip_class = GFX7;
433 else if (info->family >= CHIP_TAHITI)
434 info->chip_class = GFX6;
435 else {
436 fprintf(stderr, "amdgpu: Unknown family.\n");
437 return false;
438 }
439
440 info->family_id = amdinfo->family_id;
441 info->chip_external_rev = amdinfo->chip_external_rev;
442 info->marketing_name = amdgpu_get_marketing_name(dev);
443 info->is_pro_graphics = info->marketing_name &&
444 (!strcmp(info->marketing_name, "Pro") ||
445 !strcmp(info->marketing_name, "PRO") ||
446 !strcmp(info->marketing_name, "Frontier"));
447
448 /* Set which chips have dedicated VRAM. */
449 info->has_dedicated_vram =
450 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
451
452 /* The kernel can split large buffers in VRAM but not in GTT, so large
453 * allocations can fail or cause buffer movement failures in the kernel.
454 */
455 if (info->has_dedicated_vram)
456 info->max_alloc_size = info->vram_size * 0.8;
457 else
458 info->max_alloc_size = info->gart_size * 0.7;
459
460 info->vram_type = amdinfo->vram_type;
461 info->vram_bit_width = amdinfo->vram_bit_width;
462 info->ce_ram_size = amdinfo->ce_ram_size;
463
464 info->l2_cache_size = get_l2_cache_size(info->family);
465 info->l1_cache_size = 16384;
466
467 /* Set which chips have uncached device memory. */
468 info->has_l2_uncached = info->chip_class >= GFX9;
469
470 /* Set hardware information. */
471 info->gds_size = gds.gds_total_size;
472 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
473 /* convert the shader/memory clocks from KHz to MHz */
474 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
475 info->max_memory_clock = amdinfo->max_memory_clk / 1000;
476 info->num_tcc_blocks = device_info.num_tcc_blocks;
477 info->max_se = amdinfo->num_shader_engines;
478 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
479 info->has_hw_decode =
480 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
481 (vcn_jpeg.available_rings != 0);
482 info->uvd_fw_version =
483 uvd.available_rings ? uvd_version : 0;
484 info->vce_fw_version =
485 vce.available_rings ? vce_version : 0;
486 info->uvd_enc_supported =
487 uvd_enc.available_rings ? true : false;
488 info->has_userptr = true;
489 info->has_syncobj = has_syncobj(fd);
490 info->has_timeline_syncobj = has_timeline_syncobj(fd);
491 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
492 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
493 info->has_ctx_priority = info->drm_minor >= 22;
494 info->has_local_buffers = info->drm_minor >= 20;
495 info->kernel_flushes_hdp_before_ib = true;
496 info->htile_cmask_support_1d_tiling = true;
497 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
498 info->has_bo_metadata = true;
499 info->has_gpu_reset_status_query = true;
500 info->has_eqaa_surface_allocator = true;
501 info->has_format_bc1_through_bc7 = true;
502 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
503 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
504 info->drm_minor >= 2;
505 info->has_indirect_compute_dispatch = true;
506 /* GFX6 doesn't support unaligned loads. */
507 info->has_unaligned_shader_loads = info->chip_class != GFX6;
508 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
509 * these faults are mitigated in software.
510 */
511 info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13;
512 info->has_2d_tiling = true;
513 info->has_read_registers_query = true;
514 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
515 info->mid_command_buffer_preemption_enabled =
516 amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
517
518 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
519 info->num_render_backends = amdinfo->rb_pipes;
520 /* The value returned by the kernel driver was wrong. */
521 if (info->family == CHIP_KAVERI)
522 info->num_render_backends = 2;
523
524 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
525 if (!info->clock_crystal_freq) {
526 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
527 info->clock_crystal_freq = 1;
528 }
529 if (info->chip_class >= GFX10) {
530 info->tcc_cache_line_size = 128;
531
532 if (info->drm_minor >= 35) {
533 info->tcc_harvested = device_info.tcc_disabled_mask != 0;
534 } else {
535 /* This is a hack, but it's all we can do without a kernel upgrade. */
536 info->tcc_harvested =
537 (info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
538 }
539 } else {
540 info->tcc_cache_line_size = 64;
541 }
542 info->gb_addr_config = amdinfo->gb_addr_cfg;
543 if (info->chip_class >= GFX9) {
544 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
545 info->pipe_interleave_bytes =
546 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
547 } else {
548 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
549 info->pipe_interleave_bytes =
550 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
551 }
552 info->r600_has_virtual_memory = true;
553
554 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
555 * 16KB makes some SIMDs unoccupied).
556 *
557 * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used.
558 */
559 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
560 info->lds_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4;
561
562 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
563 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
564
565 info->has_graphics = gfx.available_rings > 0;
566 info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
567 info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
568 info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
569 info->num_rings[RING_UVD] = util_bitcount(uvd.available_rings);
570 info->num_rings[RING_VCE] = util_bitcount(vce.available_rings);
571 info->num_rings[RING_UVD_ENC] = util_bitcount(uvd_enc.available_rings);
572 info->num_rings[RING_VCN_DEC] = util_bitcount(vcn_dec.available_rings);
573 info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
574 info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
575
576 /* This is "align_mask" copied from the kernel, maximums of all IP versions. */
577 info->ib_pad_dw_mask[RING_GFX] = 0xff;
578 info->ib_pad_dw_mask[RING_COMPUTE] = 0xff;
579 info->ib_pad_dw_mask[RING_DMA] = 0xf;
580 info->ib_pad_dw_mask[RING_UVD] = 0xf;
581 info->ib_pad_dw_mask[RING_VCE] = 0x3f;
582 info->ib_pad_dw_mask[RING_UVD_ENC] = 0x3f;
583 info->ib_pad_dw_mask[RING_VCN_DEC] = 0xf;
584 info->ib_pad_dw_mask[RING_VCN_ENC] = 0x3f;
585 info->ib_pad_dw_mask[RING_VCN_JPEG] = 0xf;
586
587 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
588 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
589 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
590 */
591 info->has_clear_state = info->chip_class >= GFX7;
592
593 info->has_distributed_tess = info->chip_class >= GFX10 ||
594 (info->chip_class >= GFX8 && info->max_se >= 2);
595
596 info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
597 info->family == CHIP_RENOIR ||
598 info->chip_class >= GFX10;
599
600 info->has_rbplus = info->family == CHIP_STONEY ||
601 info->chip_class >= GFX9;
602
603 /* Some chips have RB+ registers, but don't support RB+. Those must
604 * always disable it.
605 */
606 info->rbplus_allowed = info->has_rbplus &&
607 (info->family == CHIP_STONEY ||
608 info->family == CHIP_VEGA12 ||
609 info->family == CHIP_RAVEN ||
610 info->family == CHIP_RAVEN2 ||
611 info->family == CHIP_RENOIR ||
612 info->chip_class >= GFX10_3);
613
614 info->has_out_of_order_rast = info->chip_class >= GFX8 &&
615 info->chip_class <= GFX9 &&
616 info->max_se >= 2;
617
618 /* Whether chips support double rate packed math instructions. */
619 info->has_packed_math_16bit = info->chip_class >= GFX9;
620
621 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
622 info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
623 (info->chip_class >= GFX8 &&
624 info->me_fw_feature >= 41);
625
626 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
627
628 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 ||
629 info->family == CHIP_RAVEN;
630
631 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
632 info->chip_class <= GFX9;
633
634 info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 &&
635 info->family <= CHIP_POLARIS12) ||
636 info->family == CHIP_VEGA10 ||
637 info->family == CHIP_RAVEN;
638
639 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 ||
640 info->family == CHIP_RAVEN;
641
642 /* Get the number of good compute units. */
643 info->num_good_compute_units = 0;
644 for (i = 0; i < info->max_se; i++) {
645 for (j = 0; j < info->max_sh_per_se; j++) {
646 /*
647 * The cu bitmap in amd gpu info structure is
648 * 4x4 size array, and it's usually suitable for Vega
649 * ASICs which has 4*2 SE/SH layout.
650 * But for Arcturus, SE/SH layout is changed to 8*1.
651 * To mostly reduce the impact, we make it compatible
652 * with current bitmap array as below:
653 * SE4,SH0 --> cu_bitmap[0][1]
654 * SE5,SH0 --> cu_bitmap[1][1]
655 * SE6,SH0 --> cu_bitmap[2][1]
656 * SE7,SH0 --> cu_bitmap[3][1]
657 */
658 info->cu_mask[i%4][j+i/4] = amdinfo->cu_bitmap[i%4][j+i/4];
659 info->num_good_compute_units +=
660 util_bitcount(info->cu_mask[i][j]);
661 }
662 }
663
664 /* On GFX10, only whole WGPs (in units of 2 CUs) can be disabled,
665 * and max - min <= 2.
666 */
667 unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1;
668 info->max_good_cu_per_sa = DIV_ROUND_UP(info->num_good_compute_units,
669 (info->max_se * info->max_sh_per_se * cu_group)) * cu_group;
670 info->min_good_cu_per_sa = (info->num_good_compute_units /
671 (info->max_se * info->max_sh_per_se * cu_group)) * cu_group;
672
673 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
674 sizeof(amdinfo->gb_tile_mode));
675 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
676
677 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
678 sizeof(amdinfo->gb_macro_tile_mode));
679
680 info->pte_fragment_size = alignment_info.size_local;
681 info->gart_page_size = alignment_info.size_remote;
682
683 if (info->chip_class == GFX6)
684 info->gfx_ib_pad_with_type2 = true;
685
686 unsigned ib_align = 0;
687 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
688 ib_align = MAX2(ib_align, gfx.ib_size_alignment);
689 ib_align = MAX2(ib_align, compute.ib_start_alignment);
690 ib_align = MAX2(ib_align, compute.ib_size_alignment);
691 ib_align = MAX2(ib_align, dma.ib_start_alignment);
692 ib_align = MAX2(ib_align, dma.ib_size_alignment);
693 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
694 ib_align = MAX2(ib_align, uvd.ib_size_alignment);
695 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
696 ib_align = MAX2(ib_align, uvd_enc.ib_size_alignment);
697 ib_align = MAX2(ib_align, vce.ib_start_alignment);
698 ib_align = MAX2(ib_align, vce.ib_size_alignment);
699 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
700 ib_align = MAX2(ib_align, vcn_dec.ib_size_alignment);
701 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
702 ib_align = MAX2(ib_align, vcn_enc.ib_size_alignment);
703 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
704 ib_align = MAX2(ib_align, vcn_jpeg.ib_size_alignment);
705 /* GFX10 and maybe GFX9 need this alignment for cache coherency. */
706 if (info->chip_class >= GFX9)
707 ib_align = MAX2(ib_align, info->tcc_cache_line_size);
708 /* The kernel pads gfx and compute IBs to 256 dwords since:
709 * 66f3b2d527154bd258a57c8815004b5964aa1cf5
710 * Do the same.
711 */
712 ib_align = MAX2(ib_align, 1024);
713 info->ib_alignment = ib_align;
714
715 if ((info->drm_minor >= 31 &&
716 (info->family == CHIP_RAVEN ||
717 info->family == CHIP_RAVEN2 ||
718 info->family == CHIP_RENOIR)) ||
719 (info->drm_minor >= 34 &&
720 (info->family == CHIP_NAVI12 ||
721 info->family == CHIP_NAVI14)) ||
722 info->chip_class >= GFX10_3) {
723 if (info->num_render_backends == 1)
724 info->use_display_dcc_unaligned = true;
725 else
726 info->use_display_dcc_with_retile_blit = true;
727 }
728
729 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
730 info->drm_minor >= 29;
731
732 if (info->chip_class >= GFX9) {
733 unsigned pc_lines = 0;
734
735 switch (info->family) {
736 case CHIP_VEGA10:
737 case CHIP_VEGA12:
738 case CHIP_VEGA20:
739 pc_lines = 2048;
740 break;
741 case CHIP_RAVEN:
742 case CHIP_RAVEN2:
743 case CHIP_RENOIR:
744 case CHIP_NAVI10:
745 case CHIP_NAVI12:
746 case CHIP_SIENNA_CICHLID:
747 case CHIP_NAVY_FLOUNDER:
748 pc_lines = 1024;
749 break;
750 case CHIP_NAVI14:
751 pc_lines = 512;
752 break;
753 case CHIP_ARCTURUS:
754 break;
755 default:
756 assert(0);
757 }
758
759 info->pc_lines = pc_lines;
760
761 if (info->chip_class >= GFX10) {
762 info->pbb_max_alloc_count = pc_lines / 3;
763 } else {
764 info->pbb_max_alloc_count =
765 MIN2(128, pc_lines / (4 * info->max_se));
766 }
767 }
768
769 /* The number of SDPs is the same as the number of TCCs for now. */
770 if (info->chip_class >= GFX10)
771 info->num_sdp_interfaces = device_info.num_tcc_blocks;
772
773 if (info->chip_class >= GFX10_3)
774 info->max_wave64_per_simd = 16;
775 else if (info->chip_class == GFX10)
776 info->max_wave64_per_simd = 20;
777 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
778 info->max_wave64_per_simd = 8;
779 else
780 info->max_wave64_per_simd = 10;
781
782 if (info->chip_class >= GFX10) {
783 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd;
784 info->min_sgpr_alloc = 128;
785 info->sgpr_alloc_granularity = 128;
786 /* Don't use late alloc on small chips. */
787 info->use_late_alloc = info->num_render_backends > 4;
788 } else if (info->chip_class >= GFX8) {
789 info->num_physical_sgprs_per_simd = 800;
790 info->min_sgpr_alloc = 16;
791 info->sgpr_alloc_granularity = 16;
792 info->use_late_alloc = true;
793 } else {
794 info->num_physical_sgprs_per_simd = 512;
795 info->min_sgpr_alloc = 8;
796 info->sgpr_alloc_granularity = 8;
797 /* Potential hang on Kabini: */
798 info->use_late_alloc = info->family != CHIP_KABINI;
799 }
800
801 info->max_sgpr_alloc = info->family == CHIP_TONGA ||
802 info->family == CHIP_ICELAND ? 96 : 104;
803
804 info->min_wave64_vgpr_alloc = 4;
805 info->max_vgpr_alloc = 256;
806 info->wave64_vgpr_alloc_granularity = 4;
807
808 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
809 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
810
811 return true;
812 }
813
814 void ac_compute_driver_uuid(char *uuid, size_t size)
815 {
816 char amd_uuid[] = "AMD-MESA-DRV";
817
818 assert(size >= sizeof(amd_uuid));
819
820 memset(uuid, 0, size);
821 strncpy(uuid, amd_uuid, size);
822 }
823
824 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
825 {
826 uint32_t *uint_uuid = (uint32_t*)uuid;
827
828 assert(size >= sizeof(uint32_t)*4);
829
830 /**
831 * Use the device info directly instead of using a sha1. GL/VK UUIDs
832 * are 16 byte vs 20 byte for sha1, and the truncation that would be
833 * required would get rid of part of the little entropy we have.
834 * */
835 memset(uuid, 0, size);
836 uint_uuid[0] = info->pci_domain;
837 uint_uuid[1] = info->pci_bus;
838 uint_uuid[2] = info->pci_dev;
839 uint_uuid[3] = info->pci_func;
840 }
841
842 void ac_print_gpu_info(struct radeon_info *info)
843 {
844 printf("Device info:\n");
845 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
846 info->pci_domain, info->pci_bus,
847 info->pci_dev, info->pci_func);
848
849 printf(" name = %s\n", info->name);
850 printf(" marketing_name = %s\n", info->marketing_name);
851 printf(" is_pro_graphics = %u\n", info->is_pro_graphics);
852 printf(" pci_id = 0x%x\n", info->pci_id);
853 printf(" pci_rev_id = 0x%x\n", info->pci_rev_id);
854 printf(" family = %i\n", info->family);
855 printf(" chip_class = %i\n", info->chip_class);
856 printf(" family_id = %i\n", info->family_id);
857 printf(" chip_external_rev = %i\n", info->chip_external_rev);
858 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
859
860 printf("Features:\n");
861 printf(" has_graphics = %i\n", info->has_graphics);
862 printf(" num_rings[RING_GFX] = %i\n", info->num_rings[RING_GFX]);
863 printf(" num_rings[RING_DMA] = %i\n", info->num_rings[RING_DMA]);
864 printf(" num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
865 printf(" num_rings[RING_UVD] = %i\n", info->num_rings[RING_UVD]);
866 printf(" num_rings[RING_VCE] = %i\n", info->num_rings[RING_VCE]);
867 printf(" num_rings[RING_UVD_ENC] = %i\n", info->num_rings[RING_UVD_ENC]);
868 printf(" num_rings[RING_VCN_DEC] = %i\n", info->num_rings[RING_VCN_DEC]);
869 printf(" num_rings[RING_VCN_ENC] = %i\n", info->num_rings[RING_VCN_ENC]);
870 printf(" num_rings[RING_VCN_JPEG] = %i\n", info->num_rings[RING_VCN_JPEG]);
871 printf(" has_clear_state = %u\n", info->has_clear_state);
872 printf(" has_distributed_tess = %u\n", info->has_distributed_tess);
873 printf(" has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
874 printf(" has_rbplus = %u\n", info->has_rbplus);
875 printf(" rbplus_allowed = %u\n", info->rbplus_allowed);
876 printf(" has_load_ctx_reg_pkt = %u\n", info->has_load_ctx_reg_pkt);
877 printf(" has_out_of_order_rast = %u\n", info->has_out_of_order_rast);
878 printf(" cpdma_prefetch_writes_memory = %u\n", info->cpdma_prefetch_writes_memory);
879 printf(" has_gfx9_scissor_bug = %i\n", info->has_gfx9_scissor_bug);
880 printf(" has_tc_compat_zrange_bug = %i\n", info->has_tc_compat_zrange_bug);
881 printf(" has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug);
882 printf(" has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
883
884 printf("Display features:\n");
885 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
886 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
887
888 printf("Memory info:\n");
889 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
890 printf(" gart_page_size = %u\n", info->gart_page_size);
891 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
892 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
893 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
894 printf(" vram_type = %i\n", info->vram_type);
895 printf(" vram_bit_width = %i\n", info->vram_bit_width);
896 printf(" gds_size = %u kB\n", info->gds_size / 1024);
897 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
898 printf(" max_alloc_size = %i MB\n",
899 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
900 printf(" min_alloc_size = %u\n", info->min_alloc_size);
901 printf(" address32_hi = %u\n", info->address32_hi);
902 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
903 printf(" num_sdp_interfaces = %u\n", info->num_sdp_interfaces);
904 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
905 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
906 printf(" tcc_harvested = %u\n", info->tcc_harvested);
907 printf(" pc_lines = %u\n", info->pc_lines);
908 printf(" lds_size_per_workgroup = %u\n", info->lds_size_per_workgroup);
909 printf(" lds_granularity = %i\n", info->lds_granularity);
910 printf(" max_memory_clock = %i\n", info->max_memory_clock);
911 printf(" ce_ram_size = %i\n", info->ce_ram_size);
912 printf(" l1_cache_size = %i\n", info->l1_cache_size);
913 printf(" l2_cache_size = %i\n", info->l2_cache_size);
914
915 printf("CP info:\n");
916 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
917 printf(" ib_alignment = %u\n", info->ib_alignment);
918 printf(" me_fw_version = %i\n", info->me_fw_version);
919 printf(" me_fw_feature = %i\n", info->me_fw_feature);
920 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
921 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
922 printf(" ce_fw_version = %i\n", info->ce_fw_version);
923 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
924
925 printf("Multimedia info:\n");
926 printf(" has_hw_decode = %u\n", info->has_hw_decode);
927 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
928 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
929 printf(" vce_fw_version = %u\n", info->vce_fw_version);
930 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
931
932 printf("Kernel & winsys capabilities:\n");
933 printf(" drm = %i.%i.%i\n", info->drm_major,
934 info->drm_minor, info->drm_patchlevel);
935 printf(" has_userptr = %i\n", info->has_userptr);
936 printf(" has_syncobj = %u\n", info->has_syncobj);
937 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
938 printf(" has_timeline_syncobj = %u\n", info->has_timeline_syncobj);
939 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
940 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
941 printf(" has_local_buffers = %u\n", info->has_local_buffers);
942 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
943 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
944 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
945 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
946 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
947 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
948 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
949 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
950 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
951 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
952 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
953 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
954 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
955 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
956 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
957 printf(" mid_command_buffer_preemption_enabled = %u\n", info->mid_command_buffer_preemption_enabled);
958
959 printf("Shader core info:\n");
960 printf(" max_shader_clock = %i\n", info->max_shader_clock);
961 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
962 printf(" max_good_cu_per_sa = %i\n", info->max_good_cu_per_sa);
963 printf(" min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa);
964 printf(" max_se = %i\n", info->max_se);
965 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
966 printf(" max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
967 printf(" num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd);
968 printf(" num_physical_wave64_vgprs_per_simd = %i\n", info->num_physical_wave64_vgprs_per_simd);
969 printf(" num_simd_per_compute_unit = %i\n", info->num_simd_per_compute_unit);
970 printf(" min_sgpr_alloc = %i\n", info->min_sgpr_alloc);
971 printf(" max_sgpr_alloc = %i\n", info->max_sgpr_alloc);
972 printf(" sgpr_alloc_granularity = %i\n", info->sgpr_alloc_granularity);
973 printf(" min_wave64_vgpr_alloc = %i\n", info->min_wave64_vgpr_alloc);
974 printf(" max_vgpr_alloc = %i\n", info->max_vgpr_alloc);
975 printf(" wave64_vgpr_alloc_granularity = %i\n", info->wave64_vgpr_alloc_granularity);
976
977 printf("Render backend info:\n");
978 printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
979 printf(" num_render_backends = %i\n", info->num_render_backends);
980 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
981 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
982 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
983 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
984 printf(" pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count);
985
986 printf("GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config);
987 if (info->chip_class >= GFX10) {
988 printf(" num_pipes = %u\n",
989 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
990 printf(" pipe_interleave_size = %u\n",
991 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
992 printf(" max_compressed_frags = %u\n",
993 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
994 } else if (info->chip_class == GFX9) {
995 printf(" num_pipes = %u\n",
996 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
997 printf(" pipe_interleave_size = %u\n",
998 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
999 printf(" max_compressed_frags = %u\n",
1000 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
1001 printf(" bank_interleave_size = %u\n",
1002 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1003 printf(" num_banks = %u\n",
1004 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
1005 printf(" shader_engine_tile_size = %u\n",
1006 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1007 printf(" num_shader_engines = %u\n",
1008 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
1009 printf(" num_gpus = %u (raw)\n",
1010 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
1011 printf(" multi_gpu_tile_size = %u (raw)\n",
1012 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1013 printf(" num_rb_per_se = %u\n",
1014 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
1015 printf(" row_size = %u\n",
1016 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1017 printf(" num_lower_pipes = %u (raw)\n",
1018 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1019 printf(" se_enable = %u (raw)\n",
1020 G_0098F8_SE_ENABLE(info->gb_addr_config));
1021 } else {
1022 printf(" num_pipes = %u\n",
1023 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1024 printf(" pipe_interleave_size = %u\n",
1025 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
1026 printf(" bank_interleave_size = %u\n",
1027 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1028 printf(" num_shader_engines = %u\n",
1029 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
1030 printf(" shader_engine_tile_size = %u\n",
1031 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1032 printf(" num_gpus = %u (raw)\n",
1033 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
1034 printf(" multi_gpu_tile_size = %u (raw)\n",
1035 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1036 printf(" row_size = %u\n",
1037 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1038 printf(" num_lower_pipes = %u (raw)\n",
1039 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1040 }
1041 }
1042
1043 int
1044 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
1045 {
1046 if (chip_class >= GFX9)
1047 return -1;
1048
1049 switch (family) {
1050 case CHIP_OLAND:
1051 case CHIP_HAINAN:
1052 case CHIP_KAVERI:
1053 case CHIP_KABINI:
1054 case CHIP_ICELAND:
1055 case CHIP_CARRIZO:
1056 case CHIP_STONEY:
1057 return 16;
1058 case CHIP_TAHITI:
1059 case CHIP_PITCAIRN:
1060 case CHIP_VERDE:
1061 case CHIP_BONAIRE:
1062 case CHIP_HAWAII:
1063 case CHIP_TONGA:
1064 case CHIP_FIJI:
1065 case CHIP_POLARIS10:
1066 case CHIP_POLARIS11:
1067 case CHIP_POLARIS12:
1068 case CHIP_VEGAM:
1069 return 32;
1070 default:
1071 unreachable("Unknown GPU");
1072 }
1073 }
1074
1075 void
1076 ac_get_raster_config(struct radeon_info *info,
1077 uint32_t *raster_config_p,
1078 uint32_t *raster_config_1_p,
1079 uint32_t *se_tile_repeat_p)
1080 {
1081 unsigned raster_config, raster_config_1, se_tile_repeat;
1082
1083 switch (info->family) {
1084 /* 1 SE / 1 RB */
1085 case CHIP_HAINAN:
1086 case CHIP_KABINI:
1087 case CHIP_STONEY:
1088 raster_config = 0x00000000;
1089 raster_config_1 = 0x00000000;
1090 break;
1091 /* 1 SE / 4 RBs */
1092 case CHIP_VERDE:
1093 raster_config = 0x0000124a;
1094 raster_config_1 = 0x00000000;
1095 break;
1096 /* 1 SE / 2 RBs (Oland is special) */
1097 case CHIP_OLAND:
1098 raster_config = 0x00000082;
1099 raster_config_1 = 0x00000000;
1100 break;
1101 /* 1 SE / 2 RBs */
1102 case CHIP_KAVERI:
1103 case CHIP_ICELAND:
1104 case CHIP_CARRIZO:
1105 raster_config = 0x00000002;
1106 raster_config_1 = 0x00000000;
1107 break;
1108 /* 2 SEs / 4 RBs */
1109 case CHIP_BONAIRE:
1110 case CHIP_POLARIS11:
1111 case CHIP_POLARIS12:
1112 raster_config = 0x16000012;
1113 raster_config_1 = 0x00000000;
1114 break;
1115 /* 2 SEs / 8 RBs */
1116 case CHIP_TAHITI:
1117 case CHIP_PITCAIRN:
1118 raster_config = 0x2a00126a;
1119 raster_config_1 = 0x00000000;
1120 break;
1121 /* 4 SEs / 8 RBs */
1122 case CHIP_TONGA:
1123 case CHIP_POLARIS10:
1124 raster_config = 0x16000012;
1125 raster_config_1 = 0x0000002a;
1126 break;
1127 /* 4 SEs / 16 RBs */
1128 case CHIP_HAWAII:
1129 case CHIP_FIJI:
1130 case CHIP_VEGAM:
1131 raster_config = 0x3a00161a;
1132 raster_config_1 = 0x0000002e;
1133 break;
1134 default:
1135 fprintf(stderr,
1136 "ac: Unknown GPU, using 0 for raster_config\n");
1137 raster_config = 0x00000000;
1138 raster_config_1 = 0x00000000;
1139 break;
1140 }
1141
1142 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
1143 * This decreases performance by up to 50% when the RB is the bottleneck.
1144 */
1145 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
1146 raster_config = 0x00000000;
1147
1148 /* Fiji: Old kernels have incorrect tiling config. This decreases
1149 * RB performance by 25%. (it disables 1 RB in the second packer)
1150 */
1151 if (info->family == CHIP_FIJI &&
1152 info->cik_macrotile_mode_array[0] == 0x000000e8) {
1153 raster_config = 0x16000012;
1154 raster_config_1 = 0x0000002a;
1155 }
1156
1157 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
1158 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
1159
1160 /* I don't know how to calculate this, though this is probably a good guess. */
1161 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
1162
1163 *raster_config_p = raster_config;
1164 *raster_config_1_p = raster_config_1;
1165 if (se_tile_repeat_p)
1166 *se_tile_repeat_p = se_tile_repeat;
1167 }
1168
1169 void
1170 ac_get_harvested_configs(struct radeon_info *info,
1171 unsigned raster_config,
1172 unsigned *cik_raster_config_1_p,
1173 unsigned *raster_config_se)
1174 {
1175 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
1176 unsigned num_se = MAX2(info->max_se, 1);
1177 unsigned rb_mask = info->enabled_rb_mask;
1178 unsigned num_rb = MIN2(info->num_render_backends, 16);
1179 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
1180 unsigned rb_per_se = num_rb / num_se;
1181 unsigned se_mask[4];
1182 unsigned se;
1183
1184 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1185 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1186 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1187 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1188
1189 assert(num_se == 1 || num_se == 2 || num_se == 4);
1190 assert(sh_per_se == 1 || sh_per_se == 2);
1191 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
1192
1193
1194 if (info->chip_class >= GFX7) {
1195 unsigned raster_config_1 = *cik_raster_config_1_p;
1196 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1197 (!se_mask[2] && !se_mask[3]))) {
1198 raster_config_1 &= C_028354_SE_PAIR_MAP;
1199
1200 if (!se_mask[0] && !se_mask[1]) {
1201 raster_config_1 |=
1202 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
1203 } else {
1204 raster_config_1 |=
1205 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
1206 }
1207 *cik_raster_config_1_p = raster_config_1;
1208 }
1209 }
1210
1211 for (se = 0; se < num_se; se++) {
1212 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1213 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1214 int idx = (se / 2) * 2;
1215
1216 raster_config_se[se] = raster_config;
1217 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1218 raster_config_se[se] &= C_028350_SE_MAP;
1219
1220 if (!se_mask[idx]) {
1221 raster_config_se[se] |=
1222 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
1223 } else {
1224 raster_config_se[se] |=
1225 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
1226 }
1227 }
1228
1229 pkr0_mask &= rb_mask;
1230 pkr1_mask &= rb_mask;
1231 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1232 raster_config_se[se] &= C_028350_PKR_MAP;
1233
1234 if (!pkr0_mask) {
1235 raster_config_se[se] |=
1236 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
1237 } else {
1238 raster_config_se[se] |=
1239 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
1240 }
1241 }
1242
1243 if (rb_per_se >= 2) {
1244 unsigned rb0_mask = 1 << (se * rb_per_se);
1245 unsigned rb1_mask = rb0_mask << 1;
1246
1247 rb0_mask &= rb_mask;
1248 rb1_mask &= rb_mask;
1249 if (!rb0_mask || !rb1_mask) {
1250 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
1251
1252 if (!rb0_mask) {
1253 raster_config_se[se] |=
1254 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
1255 } else {
1256 raster_config_se[se] |=
1257 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
1258 }
1259 }
1260
1261 if (rb_per_se > 2) {
1262 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1263 rb1_mask = rb0_mask << 1;
1264 rb0_mask &= rb_mask;
1265 rb1_mask &= rb_mask;
1266 if (!rb0_mask || !rb1_mask) {
1267 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
1268
1269 if (!rb0_mask) {
1270 raster_config_se[se] |=
1271 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
1272 } else {
1273 raster_config_se[se] |=
1274 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
1275 }
1276 }
1277 }
1278 }
1279 }
1280 }
1281
1282 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
1283 unsigned waves_per_threadgroup,
1284 unsigned max_waves_per_sh,
1285 unsigned threadgroups_per_cu)
1286 {
1287 unsigned compute_resource_limits =
1288 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
1289
1290 if (info->chip_class >= GFX7) {
1291 unsigned num_cu_per_se = info->num_good_compute_units /
1292 info->max_se;
1293
1294 /* Force even distribution on all SIMDs in CU if the workgroup
1295 * size is 64. This has shown some good improvements if # of CUs
1296 * per SE is not a multiple of 4.
1297 */
1298 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
1299 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
1300
1301 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
1302 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
1303 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
1304 } else {
1305 /* GFX6 */
1306 if (max_waves_per_sh) {
1307 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
1308 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
1309 }
1310 }
1311 return compute_resource_limits;
1312 }