src/amd/common/ac_gpu_info.c

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #include "ac_gpu_info.h"
  27 #include "sid.h"
  28 #include "gfx9d.h"
  29
  30 #include "util/u_math.h"
  31
  32 #include <stdio.h>
  33
  34 #include <xf86drm.h>
  35 #include <amdgpu_drm.h>
  36
  37 #define CIK_TILE_MODE_COLOR_2D                  14
  38
  39 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  40 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  41 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  42 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  43 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  44 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  45 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  46 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  54
  55 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  56 {
  57    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  58
  59    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  60    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  61        return 2;
  62    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  63    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  64    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  65    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  66        return 4;
  67    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  68    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  69    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  71    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  72    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  74        return 8;
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  76    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  77        return 16;
  78    default:
  79        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  80        assert(!"this should never occur");
  81        return 2;
  82    }
  83 }
  84
  85 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
  86                        struct radeon_info *info,
  87                        struct amdgpu_gpu_info *amdinfo)
  88 {
  89         struct amdgpu_buffer_size_alignments alignment_info = {};
  90         struct amdgpu_heap_info vram, vram_vis, gtt;
  91         struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
  92         uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
  93         uint32_t unused_feature;
  94         int r, i, j;
  95         drmDevicePtr devinfo;
  96
  97         /* Get PCI info. */
  98         r = drmGetDevice2(fd, 0, &devinfo);
  99         if (r) {
 100                 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
 101                 return false;
 102         }
 103         info->pci_domain = devinfo->businfo.pci->domain;
 104         info->pci_bus = devinfo->businfo.pci->bus;
 105         info->pci_dev = devinfo->businfo.pci->dev;
 106         info->pci_func = devinfo->businfo.pci->func;
 107         drmFreeDevice(&devinfo);
 108
 109         /* Query hardware and driver information. */
 110         r = amdgpu_query_gpu_info(dev, amdinfo);
 111         if (r) {
 112                 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 113                 return false;
 114         }
 115
 116         r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
 117         if (r) {
 118                 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 119                 return false;
 120         }
 121
 122         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 123         if (r) {
 124                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 125                 return false;
 126         }
 127
 128         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
 129                                 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 130                                 &vram_vis);
 131         if (r) {
 132                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
 133                 return false;
 134         }
 135
 136         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 137         if (r) {
 138                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 139                 return false;
 140         }
 141
 142         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
 143         if (r) {
 144                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 145                 return false;
 146         }
 147
 148         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 149         if (r) {
 150                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 151                 return false;
 152         }
 153
 154         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 155                                         &info->me_fw_version, &unused_feature);
 156         if (r) {
 157                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
 158                 return false;
 159         }
 160
 161         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
 162                                         &info->pfp_fw_version, &unused_feature);
 163         if (r) {
 164                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
 165                 return false;
 166         }
 167
 168         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
 169                                         &info->ce_fw_version, &unused_feature);
 170         if (r) {
 171                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
 172                 return false;
 173         }
 174
 175         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
 176                                         &uvd_version, &uvd_feature);
 177         if (r) {
 178                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
 179                 return false;
 180         }
 181
 182         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
 183         if (r) {
 184                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 185                 return false;
 186         }
 187
 188         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
 189                                         &vce_version, &vce_feature);
 190         if (r) {
 191                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 192                 return false;
 193         }
 194
 195         /* Set chip identification. */
 196         info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
 197         info->vce_harvest_config = amdinfo->vce_harvest_config;
 198
 199         switch (info->pci_id) {
 200 #define CHIPSET(pci_id, name, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
 201 #include "pci_ids/radeonsi_pci_ids.h"
 202 #undef CHIPSET
 203
 204         default:
 205                 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 206                 return false;
 207         }
 208
 209         if (info->family >= CHIP_VEGA10)
 210                 info->chip_class = GFX9;
 211         else if (info->family >= CHIP_TONGA)
 212                 info->chip_class = VI;
 213         else if (info->family >= CHIP_BONAIRE)
 214                 info->chip_class = CIK;
 215         else if (info->family >= CHIP_TAHITI)
 216                 info->chip_class = SI;
 217         else {
 218                 fprintf(stderr, "amdgpu: Unknown family.\n");
 219                 return false;
 220         }
 221
 222         /* Set which chips have dedicated VRAM. */
 223         info->has_dedicated_vram =
 224                 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 225
 226         /* Set hardware information. */
 227         info->gart_size = gtt.heap_size;
 228         info->vram_size = vram.heap_size;
 229         info->vram_vis_size = vram_vis.heap_size;
 230         /* The kernel can split large buffers in VRAM but not in GTT, so large
 231          * allocations can fail or cause buffer movement failures in the kernel.
 232          */
 233         info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7);
 234         /* convert the shader clock from KHz to MHz */
 235         info->max_shader_clock = amdinfo->max_engine_clk / 1000;
 236         info->max_se = amdinfo->num_shader_engines;
 237         info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
 238         info->has_uvd = uvd.available_rings != 0;
 239         info->uvd_fw_version =
 240                 uvd.available_rings ? uvd_version : 0;
 241         info->vce_fw_version =
 242                 vce.available_rings ? vce_version : 0;
 243         info->has_userptr = true;
 244         info->num_render_backends = amdinfo->rb_pipes;
 245         info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 246         info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 247         if (info->chip_class == GFX9) {
 248                 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
 249                 info->pipe_interleave_bytes =
 250                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
 251         } else {
 252                 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
 253                 info->pipe_interleave_bytes =
 254                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
 255         }
 256         info->has_virtual_memory = true;
 257         info->has_sdma = dma.available_rings != 0;
 258
 259         /* Get the number of good compute units. */
 260         info->num_good_compute_units = 0;
 261         for (i = 0; i < info->max_se; i++)
 262                 for (j = 0; j < info->max_sh_per_se; j++)
 263                         info->num_good_compute_units +=
 264                                 util_bitcount(amdinfo->cu_bitmap[i][j]);
 265
 266         memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
 267                 sizeof(amdinfo->gb_tile_mode));
 268         info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
 269
 270         memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
 271                 sizeof(amdinfo->gb_macro_tile_mode));
 272
 273         info->gart_page_size = alignment_info.size_remote;
 274
 275         if (info->chip_class == SI)
 276                 info->gfx_ib_pad_with_type2 = TRUE;
 277
 278         return true;
 279 }
 280