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[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "addrlib/src/amdgpu_asic_addr.h"
28 #include "sid.h"
29
30 #include "util/macros.h"
31 #include "util/u_math.h"
32
33 #include <stdio.h>
34
35 #include <xf86drm.h>
36 #include "drm-uapi/amdgpu_drm.h"
37
38 #include <amdgpu.h>
39
40 #define CIK_TILE_MODE_COLOR_2D 14
41
42 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57
58 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
59 {
60 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
61
62 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
63 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
64 return 2;
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
68 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
69 return 4;
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
77 return 8;
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
80 return 16;
81 default:
82 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
83 assert(!"this should never occur");
84 return 2;
85 }
86 }
87
88 static bool has_syncobj(int fd)
89 {
90 uint64_t value;
91 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
92 return false;
93 return value ? true : false;
94 }
95
96 static uint64_t fix_vram_size(uint64_t size)
97 {
98 /* The VRAM size is underreported, so we need to fix it, because
99 * it's used to compute the number of memory modules for harvesting.
100 */
101 return align64(size, 256*1024*1024);
102 }
103
104 static uint32_t
105 get_l2_cache_size(enum radeon_family family)
106 {
107 switch (family) {
108 case CHIP_KABINI:
109 case CHIP_STONEY:
110 return 128 * 1024;
111 case CHIP_OLAND:
112 case CHIP_HAINAN:
113 case CHIP_ICELAND:
114 return 256 * 1024;
115 case CHIP_PITCAIRN:
116 case CHIP_VERDE:
117 case CHIP_BONAIRE:
118 case CHIP_KAVERI:
119 case CHIP_POLARIS12:
120 case CHIP_CARRIZO:
121 return 512 * 1024;
122 case CHIP_TAHITI:
123 case CHIP_TONGA:
124 return 768 * 1024;
125 break;
126 case CHIP_HAWAII:
127 case CHIP_POLARIS11:
128 return 1024 * 1024;
129 case CHIP_FIJI:
130 case CHIP_POLARIS10:
131 return 2048 * 1024;
132 break;
133 default:
134 return 4096 * 1024;
135 }
136 }
137
138 bool ac_query_gpu_info(int fd, void *dev_p,
139 struct radeon_info *info,
140 struct amdgpu_gpu_info *amdinfo)
141 {
142 struct drm_amdgpu_info_device device_info = {};
143 struct amdgpu_buffer_size_alignments alignment_info = {};
144 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
145 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
146 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
147 struct amdgpu_gds_resource_info gds = {};
148 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
149 int r, i, j;
150 amdgpu_device_handle dev = dev_p;
151 drmDevicePtr devinfo;
152
153 /* Get PCI info. */
154 r = drmGetDevice2(fd, 0, &devinfo);
155 if (r) {
156 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
157 return false;
158 }
159 info->pci_domain = devinfo->businfo.pci->domain;
160 info->pci_bus = devinfo->businfo.pci->bus;
161 info->pci_dev = devinfo->businfo.pci->dev;
162 info->pci_func = devinfo->businfo.pci->func;
163 drmFreeDevice(&devinfo);
164
165 assert(info->drm_major == 3);
166 info->is_amdgpu = true;
167
168 /* Query hardware and driver information. */
169 r = amdgpu_query_gpu_info(dev, amdinfo);
170 if (r) {
171 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
172 return false;
173 }
174
175 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
176 &device_info);
177 if (r) {
178 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
179 return false;
180 }
181
182 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
183 if (r) {
184 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
185 return false;
186 }
187
188 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
189 if (r) {
190 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
191 return false;
192 }
193
194 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
195 if (r) {
196 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
197 return false;
198 }
199
200 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
201 if (r) {
202 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
203 return false;
204 }
205
206 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
207 if (r) {
208 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
209 return false;
210 }
211
212 if (info->drm_minor >= 17) {
213 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
214 if (r) {
215 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
216 return false;
217 }
218 }
219
220 if (info->drm_minor >= 17) {
221 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
222 if (r) {
223 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
224 return false;
225 }
226 }
227
228 if (info->drm_minor >= 17) {
229 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
230 if (r) {
231 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
232 return false;
233 }
234 }
235
236 if (info->drm_minor >= 27) {
237 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
238 if (r) {
239 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
240 return false;
241 }
242 }
243
244 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
245 &info->me_fw_version,
246 &info->me_fw_feature);
247 if (r) {
248 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
249 return false;
250 }
251
252 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
253 &info->pfp_fw_version,
254 &info->pfp_fw_feature);
255 if (r) {
256 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
257 return false;
258 }
259
260 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
261 &info->ce_fw_version,
262 &info->ce_fw_feature);
263 if (r) {
264 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
265 return false;
266 }
267
268 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
269 &uvd_version, &uvd_feature);
270 if (r) {
271 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
272 return false;
273 }
274
275 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
276 if (r) {
277 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
278 return false;
279 }
280
281 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
282 &vce_version, &vce_feature);
283 if (r) {
284 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
285 return false;
286 }
287
288 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
289 if (r) {
290 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
291 return false;
292 }
293
294 r = amdgpu_query_gds_info(dev, &gds);
295 if (r) {
296 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
297 return false;
298 }
299
300 if (info->drm_minor >= 9) {
301 struct drm_amdgpu_memory_info meminfo = {};
302
303 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
304 if (r) {
305 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
306 return false;
307 }
308
309 /* Note: usable_heap_size values can be random and can't be relied on. */
310 info->gart_size = meminfo.gtt.total_heap_size;
311 info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
312 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
313 } else {
314 /* This is a deprecated interface, which reports usable sizes
315 * (total minus pinned), but the pinned size computation is
316 * buggy, so the values returned from these functions can be
317 * random.
318 */
319 struct amdgpu_heap_info vram, vram_vis, gtt;
320
321 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
322 if (r) {
323 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
324 return false;
325 }
326
327 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
328 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
329 &vram_vis);
330 if (r) {
331 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
332 return false;
333 }
334
335 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
336 if (r) {
337 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
338 return false;
339 }
340
341 info->gart_size = gtt.heap_size;
342 info->vram_size = fix_vram_size(vram.heap_size);
343 info->vram_vis_size = vram_vis.heap_size;
344 }
345
346 /* Set chip identification. */
347 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
348 info->pci_rev_id = amdinfo->pci_rev_id;
349 info->vce_harvest_config = amdinfo->vce_harvest_config;
350
351 #define identify_chip2(asic, chipname) \
352 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
353 info->family = CHIP_##chipname; \
354 info->name = #chipname; \
355 }
356 #define identify_chip(chipname) identify_chip2(chipname, chipname)
357
358 switch (amdinfo->family_id) {
359 case FAMILY_SI:
360 identify_chip(TAHITI);
361 identify_chip(PITCAIRN);
362 identify_chip2(CAPEVERDE, VERDE);
363 identify_chip(OLAND);
364 identify_chip(HAINAN);
365 break;
366 case FAMILY_CI:
367 identify_chip(BONAIRE);
368 identify_chip(HAWAII);
369 break;
370 case FAMILY_KV:
371 identify_chip2(SPECTRE, KAVERI);
372 identify_chip2(SPOOKY, KAVERI);
373 identify_chip2(KALINDI, KABINI);
374 identify_chip2(GODAVARI, KABINI);
375 break;
376 case FAMILY_VI:
377 identify_chip(ICELAND);
378 identify_chip(TONGA);
379 identify_chip(FIJI);
380 identify_chip(POLARIS10);
381 identify_chip(POLARIS11);
382 identify_chip(POLARIS12);
383 identify_chip(VEGAM);
384 break;
385 case FAMILY_CZ:
386 identify_chip(CARRIZO);
387 identify_chip(STONEY);
388 break;
389 case FAMILY_AI:
390 identify_chip(VEGA10);
391 identify_chip(VEGA12);
392 identify_chip(VEGA20);
393 identify_chip(ARCTURUS);
394 break;
395 case FAMILY_RV:
396 identify_chip(RAVEN);
397 identify_chip(RAVEN2);
398 identify_chip(RENOIR);
399 break;
400 case FAMILY_NV:
401 identify_chip(NAVI10);
402 identify_chip(NAVI12);
403 identify_chip(NAVI14);
404 identify_chip(SIENNA);
405 break;
406 }
407
408 if (!info->name) {
409 fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
410 amdinfo->family_id, amdinfo->chip_external_rev);
411 return false;
412 }
413
414 if (info->family >= CHIP_SIENNA)
415 info->chip_class = GFX10_3;
416 else if (info->family >= CHIP_NAVI10)
417 info->chip_class = GFX10;
418 else if (info->family >= CHIP_VEGA10)
419 info->chip_class = GFX9;
420 else if (info->family >= CHIP_TONGA)
421 info->chip_class = GFX8;
422 else if (info->family >= CHIP_BONAIRE)
423 info->chip_class = GFX7;
424 else if (info->family >= CHIP_TAHITI)
425 info->chip_class = GFX6;
426 else {
427 fprintf(stderr, "amdgpu: Unknown family.\n");
428 return false;
429 }
430
431 info->family_id = amdinfo->family_id;
432 info->chip_external_rev = amdinfo->chip_external_rev;
433 info->marketing_name = amdgpu_get_marketing_name(dev);
434 info->is_pro_graphics = info->marketing_name &&
435 (!strcmp(info->marketing_name, "Pro") ||
436 !strcmp(info->marketing_name, "PRO") ||
437 !strcmp(info->marketing_name, "Frontier"));
438
439 /* Set which chips have dedicated VRAM. */
440 info->has_dedicated_vram =
441 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
442
443 /* The kernel can split large buffers in VRAM but not in GTT, so large
444 * allocations can fail or cause buffer movement failures in the kernel.
445 */
446 if (info->has_dedicated_vram)
447 info->max_alloc_size = info->vram_size * 0.8;
448 else
449 info->max_alloc_size = info->gart_size * 0.7;
450
451 info->vram_type = amdinfo->vram_type;
452 info->vram_bit_width = amdinfo->vram_bit_width;
453 info->ce_ram_size = amdinfo->ce_ram_size;
454
455 info->l2_cache_size = get_l2_cache_size(info->family);
456 info->l1_cache_size = 16384;
457
458 /* Set which chips have uncached device memory. */
459 info->has_l2_uncached = info->chip_class >= GFX9;
460
461 /* Set hardware information. */
462 info->gds_size = gds.gds_total_size;
463 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
464 /* convert the shader/memory clocks from KHz to MHz */
465 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
466 info->max_memory_clock = amdinfo->max_memory_clk / 1000;
467 info->num_tcc_blocks = device_info.num_tcc_blocks;
468 info->max_se = amdinfo->num_shader_engines;
469 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
470 info->has_hw_decode =
471 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
472 (vcn_jpeg.available_rings != 0);
473 info->uvd_fw_version =
474 uvd.available_rings ? uvd_version : 0;
475 info->vce_fw_version =
476 vce.available_rings ? vce_version : 0;
477 info->uvd_enc_supported =
478 uvd_enc.available_rings ? true : false;
479 info->has_userptr = true;
480 info->has_syncobj = has_syncobj(fd);
481 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
482 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
483 info->has_ctx_priority = info->drm_minor >= 22;
484 info->has_local_buffers = info->drm_minor >= 20;
485 info->kernel_flushes_hdp_before_ib = true;
486 info->htile_cmask_support_1d_tiling = true;
487 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
488 info->has_bo_metadata = true;
489 info->has_gpu_reset_status_query = true;
490 info->has_eqaa_surface_allocator = true;
491 info->has_format_bc1_through_bc7 = true;
492 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
493 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
494 info->drm_minor >= 2;
495 info->has_indirect_compute_dispatch = true;
496 /* GFX6 doesn't support unaligned loads. */
497 info->has_unaligned_shader_loads = info->chip_class != GFX6;
498 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
499 * these faults are mitigated in software.
500 */
501 info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13;
502 info->has_2d_tiling = true;
503 info->has_read_registers_query = true;
504 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
505
506 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
507 info->num_render_backends = amdinfo->rb_pipes;
508 /* The value returned by the kernel driver was wrong. */
509 if (info->family == CHIP_KAVERI)
510 info->num_render_backends = 2;
511
512 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
513 if (!info->clock_crystal_freq) {
514 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
515 info->clock_crystal_freq = 1;
516 }
517 if (info->chip_class >= GFX10) {
518 info->tcc_cache_line_size = 128;
519
520 if (info->drm_minor >= 35) {
521 info->tcc_harvested = device_info.tcc_disabled_mask != 0;
522 } else {
523 /* This is a hack, but it's all we can do without a kernel upgrade. */
524 info->tcc_harvested =
525 (info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
526 }
527 } else {
528 info->tcc_cache_line_size = 64;
529 }
530 info->gb_addr_config = amdinfo->gb_addr_cfg;
531 if (info->chip_class == GFX9) {
532 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
533 info->pipe_interleave_bytes =
534 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
535 } else {
536 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
537 info->pipe_interleave_bytes =
538 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
539 }
540 info->r600_has_virtual_memory = true;
541
542 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
543 * 16KB makes some SIMDs unoccupied).
544 *
545 * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used.
546 */
547 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
548 info->lds_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4;
549
550 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
551 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
552
553 info->has_graphics = gfx.available_rings > 0;
554 info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
555 info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
556 info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
557 info->num_rings[RING_UVD] = util_bitcount(uvd.available_rings);
558 info->num_rings[RING_VCE] = util_bitcount(vce.available_rings);
559 info->num_rings[RING_UVD_ENC] = util_bitcount(uvd_enc.available_rings);
560 info->num_rings[RING_VCN_DEC] = util_bitcount(vcn_dec.available_rings);
561 info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
562 info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
563
564 /* This is "align_mask" copied from the kernel, maximums of all IP versions. */
565 info->ib_pad_dw_mask[RING_GFX] = 0xff;
566 info->ib_pad_dw_mask[RING_COMPUTE] = 0xff;
567 info->ib_pad_dw_mask[RING_DMA] = 0xf;
568 info->ib_pad_dw_mask[RING_UVD] = 0xf;
569 info->ib_pad_dw_mask[RING_VCE] = 0x3f;
570 info->ib_pad_dw_mask[RING_UVD_ENC] = 0x3f;
571 info->ib_pad_dw_mask[RING_VCN_DEC] = 0xf;
572 info->ib_pad_dw_mask[RING_VCN_ENC] = 0x3f;
573 info->ib_pad_dw_mask[RING_VCN_JPEG] = 0xf;
574
575 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
576 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
577 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
578 */
579 info->has_clear_state = info->chip_class >= GFX7;
580
581 info->has_distributed_tess = info->chip_class >= GFX10 ||
582 (info->chip_class >= GFX8 && info->max_se >= 2);
583
584 info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
585 info->family == CHIP_RENOIR ||
586 info->chip_class >= GFX10;
587
588 info->has_rbplus = info->family == CHIP_STONEY ||
589 info->chip_class >= GFX9;
590
591 /* Some chips have RB+ registers, but don't support RB+. Those must
592 * always disable it.
593 */
594 info->rbplus_allowed = info->has_rbplus &&
595 (info->family == CHIP_STONEY ||
596 info->family == CHIP_VEGA12 ||
597 info->family == CHIP_RAVEN ||
598 info->family == CHIP_RAVEN2 ||
599 info->family == CHIP_RENOIR ||
600 info->chip_class >= GFX10_3);
601
602 info->has_out_of_order_rast = info->chip_class >= GFX8 &&
603 info->chip_class <= GFX9 &&
604 info->max_se >= 2;
605
606 /* Whether chips support double rate packed math instructions. */
607 info->has_packed_math_16bit = info->chip_class >= GFX9;
608
609 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
610 info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
611 (info->chip_class >= GFX8 &&
612 info->me_fw_feature >= 41);
613
614 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
615
616 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 ||
617 info->family == CHIP_RAVEN;
618
619 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
620 info->chip_class <= GFX9;
621
622 info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 &&
623 info->family <= CHIP_POLARIS12) ||
624 info->family == CHIP_VEGA10 ||
625 info->family == CHIP_RAVEN;
626
627 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 ||
628 info->family == CHIP_RAVEN;
629
630 /* Get the number of good compute units. */
631 info->num_good_compute_units = 0;
632 for (i = 0; i < info->max_se; i++) {
633 for (j = 0; j < info->max_sh_per_se; j++) {
634 /*
635 * The cu bitmap in amd gpu info structure is
636 * 4x4 size array, and it's usually suitable for Vega
637 * ASICs which has 4*2 SE/SH layout.
638 * But for Arcturus, SE/SH layout is changed to 8*1.
639 * To mostly reduce the impact, we make it compatible
640 * with current bitmap array as below:
641 * SE4,SH0 --> cu_bitmap[0][1]
642 * SE5,SH0 --> cu_bitmap[1][1]
643 * SE6,SH0 --> cu_bitmap[2][1]
644 * SE7,SH0 --> cu_bitmap[3][1]
645 */
646 info->cu_mask[i%4][j+i/4] = amdinfo->cu_bitmap[i%4][j+i/4];
647 info->num_good_compute_units +=
648 util_bitcount(info->cu_mask[i][j]);
649 }
650 }
651
652 /* On GFX10, only whole WGPs (in units of 2 CUs) can be disabled,
653 * and max - min <= 2.
654 */
655 unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1;
656 info->max_good_cu_per_sa = DIV_ROUND_UP(info->num_good_compute_units,
657 (info->max_se * info->max_sh_per_se * cu_group)) * cu_group;
658 info->min_good_cu_per_sa = (info->num_good_compute_units /
659 (info->max_se * info->max_sh_per_se * cu_group)) * cu_group;
660
661 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
662 sizeof(amdinfo->gb_tile_mode));
663 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
664
665 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
666 sizeof(amdinfo->gb_macro_tile_mode));
667
668 info->pte_fragment_size = alignment_info.size_local;
669 info->gart_page_size = alignment_info.size_remote;
670
671 if (info->chip_class == GFX6)
672 info->gfx_ib_pad_with_type2 = true;
673
674 unsigned ib_align = 0;
675 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
676 ib_align = MAX2(ib_align, gfx.ib_size_alignment);
677 ib_align = MAX2(ib_align, compute.ib_start_alignment);
678 ib_align = MAX2(ib_align, compute.ib_size_alignment);
679 ib_align = MAX2(ib_align, dma.ib_start_alignment);
680 ib_align = MAX2(ib_align, dma.ib_size_alignment);
681 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
682 ib_align = MAX2(ib_align, uvd.ib_size_alignment);
683 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
684 ib_align = MAX2(ib_align, uvd_enc.ib_size_alignment);
685 ib_align = MAX2(ib_align, vce.ib_start_alignment);
686 ib_align = MAX2(ib_align, vce.ib_size_alignment);
687 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
688 ib_align = MAX2(ib_align, vcn_dec.ib_size_alignment);
689 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
690 ib_align = MAX2(ib_align, vcn_enc.ib_size_alignment);
691 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
692 ib_align = MAX2(ib_align, vcn_jpeg.ib_size_alignment);
693 /* GFX10 and maybe GFX9 need this alignment for cache coherency. */
694 if (info->chip_class >= GFX9)
695 ib_align = MAX2(ib_align, info->tcc_cache_line_size);
696 /* The kernel pads gfx and compute IBs to 256 dwords since:
697 * 66f3b2d527154bd258a57c8815004b5964aa1cf5
698 * Do the same.
699 */
700 ib_align = MAX2(ib_align, 1024);
701 info->ib_alignment = ib_align;
702
703 if ((info->drm_minor >= 31 &&
704 (info->family == CHIP_RAVEN ||
705 info->family == CHIP_RAVEN2 ||
706 info->family == CHIP_RENOIR)) ||
707 (info->drm_minor >= 34 &&
708 (info->family == CHIP_NAVI12 ||
709 info->family == CHIP_NAVI14))) {
710 if (info->num_render_backends == 1)
711 info->use_display_dcc_unaligned = true;
712 else
713 info->use_display_dcc_with_retile_blit = true;
714 }
715
716 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
717 info->drm_minor >= 29;
718
719 if (info->chip_class >= GFX9) {
720 unsigned pc_lines = 0;
721
722 switch (info->family) {
723 case CHIP_VEGA10:
724 case CHIP_VEGA12:
725 case CHIP_VEGA20:
726 pc_lines = 2048;
727 break;
728 case CHIP_RAVEN:
729 case CHIP_RAVEN2:
730 case CHIP_RENOIR:
731 case CHIP_NAVI10:
732 case CHIP_NAVI12:
733 case CHIP_SIENNA:
734 pc_lines = 1024;
735 break;
736 case CHIP_NAVI14:
737 pc_lines = 512;
738 break;
739 case CHIP_ARCTURUS:
740 break;
741 default:
742 assert(0);
743 }
744
745 info->pc_lines = pc_lines;
746
747 if (info->chip_class >= GFX10) {
748 info->pbb_max_alloc_count = pc_lines / 3;
749 } else {
750 info->pbb_max_alloc_count =
751 MIN2(128, pc_lines / (4 * info->max_se));
752 }
753 }
754
755 /* The number of SDPs is the same as the number of TCCs for now. */
756 if (info->chip_class >= GFX10)
757 info->num_sdp_interfaces = device_info.num_tcc_blocks;
758
759 if (info->chip_class >= GFX10_3)
760 info->max_wave64_per_simd = 16;
761 else if (info->chip_class == GFX10)
762 info->max_wave64_per_simd = 20;
763 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
764 info->max_wave64_per_simd = 8;
765 else
766 info->max_wave64_per_simd = 10;
767
768 if (info->chip_class >= GFX10) {
769 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd;
770 info->min_sgpr_alloc = 128;
771 info->sgpr_alloc_granularity = 128;
772 /* Don't use late alloc on small chips. */
773 info->use_late_alloc = info->num_render_backends > 4;
774 } else if (info->chip_class >= GFX8) {
775 info->num_physical_sgprs_per_simd = 800;
776 info->min_sgpr_alloc = 16;
777 info->sgpr_alloc_granularity = 16;
778 info->use_late_alloc = true;
779 } else {
780 info->num_physical_sgprs_per_simd = 512;
781 info->min_sgpr_alloc = 8;
782 info->sgpr_alloc_granularity = 8;
783 /* Potential hang on Kabini: */
784 info->use_late_alloc = info->family != CHIP_KABINI;
785 }
786
787 info->max_sgpr_alloc = info->family == CHIP_TONGA ||
788 info->family == CHIP_ICELAND ? 96 : 104;
789
790 info->min_wave64_vgpr_alloc = 4;
791 info->max_vgpr_alloc = 256;
792 info->wave64_vgpr_alloc_granularity = 4;
793
794 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
795 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
796
797 return true;
798 }
799
800 void ac_compute_driver_uuid(char *uuid, size_t size)
801 {
802 char amd_uuid[] = "AMD-MESA-DRV";
803
804 assert(size >= sizeof(amd_uuid));
805
806 memset(uuid, 0, size);
807 strncpy(uuid, amd_uuid, size);
808 }
809
810 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
811 {
812 uint32_t *uint_uuid = (uint32_t*)uuid;
813
814 assert(size >= sizeof(uint32_t)*4);
815
816 /**
817 * Use the device info directly instead of using a sha1. GL/VK UUIDs
818 * are 16 byte vs 20 byte for sha1, and the truncation that would be
819 * required would get rid of part of the little entropy we have.
820 * */
821 memset(uuid, 0, size);
822 uint_uuid[0] = info->pci_domain;
823 uint_uuid[1] = info->pci_bus;
824 uint_uuid[2] = info->pci_dev;
825 uint_uuid[3] = info->pci_func;
826 }
827
828 void ac_print_gpu_info(struct radeon_info *info)
829 {
830 printf("Device info:\n");
831 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
832 info->pci_domain, info->pci_bus,
833 info->pci_dev, info->pci_func);
834
835 printf(" name = %s\n", info->name);
836 printf(" marketing_name = %s\n", info->marketing_name);
837 printf(" is_pro_graphics = %u\n", info->is_pro_graphics);
838 printf(" pci_id = 0x%x\n", info->pci_id);
839 printf(" pci_rev_id = 0x%x\n", info->pci_rev_id);
840 printf(" family = %i\n", info->family);
841 printf(" chip_class = %i\n", info->chip_class);
842 printf(" family_id = %i\n", info->family_id);
843 printf(" chip_external_rev = %i\n", info->chip_external_rev);
844 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
845
846 printf("Features:\n");
847 printf(" has_graphics = %i\n", info->has_graphics);
848 printf(" num_rings[RING_GFX] = %i\n", info->num_rings[RING_GFX]);
849 printf(" num_rings[RING_DMA] = %i\n", info->num_rings[RING_DMA]);
850 printf(" num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
851 printf(" num_rings[RING_UVD] = %i\n", info->num_rings[RING_UVD]);
852 printf(" num_rings[RING_VCE] = %i\n", info->num_rings[RING_VCE]);
853 printf(" num_rings[RING_UVD_ENC] = %i\n", info->num_rings[RING_UVD_ENC]);
854 printf(" num_rings[RING_VCN_DEC] = %i\n", info->num_rings[RING_VCN_DEC]);
855 printf(" num_rings[RING_VCN_ENC] = %i\n", info->num_rings[RING_VCN_ENC]);
856 printf(" num_rings[RING_VCN_JPEG] = %i\n", info->num_rings[RING_VCN_JPEG]);
857 printf(" has_clear_state = %u\n", info->has_clear_state);
858 printf(" has_distributed_tess = %u\n", info->has_distributed_tess);
859 printf(" has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
860 printf(" has_rbplus = %u\n", info->has_rbplus);
861 printf(" rbplus_allowed = %u\n", info->rbplus_allowed);
862 printf(" has_load_ctx_reg_pkt = %u\n", info->has_load_ctx_reg_pkt);
863 printf(" has_out_of_order_rast = %u\n", info->has_out_of_order_rast);
864 printf(" cpdma_prefetch_writes_memory = %u\n", info->cpdma_prefetch_writes_memory);
865 printf(" has_gfx9_scissor_bug = %i\n", info->has_gfx9_scissor_bug);
866 printf(" has_tc_compat_zrange_bug = %i\n", info->has_tc_compat_zrange_bug);
867 printf(" has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug);
868 printf(" has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
869
870 printf("Display features:\n");
871 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
872 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
873
874 printf("Memory info:\n");
875 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
876 printf(" gart_page_size = %u\n", info->gart_page_size);
877 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
878 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
879 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
880 printf(" vram_type = %i\n", info->vram_type);
881 printf(" vram_bit_width = %i\n", info->vram_bit_width);
882 printf(" gds_size = %u kB\n", info->gds_size / 1024);
883 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
884 printf(" max_alloc_size = %i MB\n",
885 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
886 printf(" min_alloc_size = %u\n", info->min_alloc_size);
887 printf(" address32_hi = %u\n", info->address32_hi);
888 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
889 printf(" num_sdp_interfaces = %u\n", info->num_sdp_interfaces);
890 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
891 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
892 printf(" tcc_harvested = %u\n", info->tcc_harvested);
893 printf(" pc_lines = %u\n", info->pc_lines);
894 printf(" lds_size_per_workgroup = %u\n", info->lds_size_per_workgroup);
895 printf(" lds_granularity = %i\n", info->lds_granularity);
896 printf(" max_memory_clock = %i\n", info->max_memory_clock);
897 printf(" ce_ram_size = %i\n", info->ce_ram_size);
898 printf(" l1_cache_size = %i\n", info->l1_cache_size);
899 printf(" l2_cache_size = %i\n", info->l2_cache_size);
900
901 printf("CP info:\n");
902 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
903 printf(" ib_alignment = %u\n", info->ib_alignment);
904 printf(" me_fw_version = %i\n", info->me_fw_version);
905 printf(" me_fw_feature = %i\n", info->me_fw_feature);
906 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
907 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
908 printf(" ce_fw_version = %i\n", info->ce_fw_version);
909 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
910
911 printf("Multimedia info:\n");
912 printf(" has_hw_decode = %u\n", info->has_hw_decode);
913 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
914 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
915 printf(" vce_fw_version = %u\n", info->vce_fw_version);
916 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
917
918 printf("Kernel & winsys capabilities:\n");
919 printf(" drm = %i.%i.%i\n", info->drm_major,
920 info->drm_minor, info->drm_patchlevel);
921 printf(" has_userptr = %i\n", info->has_userptr);
922 printf(" has_syncobj = %u\n", info->has_syncobj);
923 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
924 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
925 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
926 printf(" has_local_buffers = %u\n", info->has_local_buffers);
927 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
928 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
929 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
930 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
931 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
932 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
933 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
934 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
935 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
936 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
937 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
938 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
939 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
940 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
941 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
942
943 printf("Shader core info:\n");
944 printf(" max_shader_clock = %i\n", info->max_shader_clock);
945 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
946 printf(" max_good_cu_per_sa = %i\n", info->max_good_cu_per_sa);
947 printf(" min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa);
948 printf(" max_se = %i\n", info->max_se);
949 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
950 printf(" max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
951 printf(" num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd);
952 printf(" num_physical_wave64_vgprs_per_simd = %i\n", info->num_physical_wave64_vgprs_per_simd);
953 printf(" num_simd_per_compute_unit = %i\n", info->num_simd_per_compute_unit);
954 printf(" min_sgpr_alloc = %i\n", info->min_sgpr_alloc);
955 printf(" max_sgpr_alloc = %i\n", info->max_sgpr_alloc);
956 printf(" sgpr_alloc_granularity = %i\n", info->sgpr_alloc_granularity);
957 printf(" min_wave64_vgpr_alloc = %i\n", info->min_wave64_vgpr_alloc);
958 printf(" max_vgpr_alloc = %i\n", info->max_vgpr_alloc);
959 printf(" wave64_vgpr_alloc_granularity = %i\n", info->wave64_vgpr_alloc_granularity);
960
961 printf("Render backend info:\n");
962 printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
963 printf(" num_render_backends = %i\n", info->num_render_backends);
964 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
965 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
966 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
967 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
968 printf(" pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count);
969
970 printf("GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config);
971 if (info->chip_class >= GFX10) {
972 printf(" num_pipes = %u\n",
973 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
974 printf(" pipe_interleave_size = %u\n",
975 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
976 printf(" max_compressed_frags = %u\n",
977 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
978 } else if (info->chip_class == GFX9) {
979 printf(" num_pipes = %u\n",
980 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
981 printf(" pipe_interleave_size = %u\n",
982 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
983 printf(" max_compressed_frags = %u\n",
984 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
985 printf(" bank_interleave_size = %u\n",
986 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
987 printf(" num_banks = %u\n",
988 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
989 printf(" shader_engine_tile_size = %u\n",
990 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
991 printf(" num_shader_engines = %u\n",
992 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
993 printf(" num_gpus = %u (raw)\n",
994 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
995 printf(" multi_gpu_tile_size = %u (raw)\n",
996 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
997 printf(" num_rb_per_se = %u\n",
998 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
999 printf(" row_size = %u\n",
1000 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1001 printf(" num_lower_pipes = %u (raw)\n",
1002 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1003 printf(" se_enable = %u (raw)\n",
1004 G_0098F8_SE_ENABLE(info->gb_addr_config));
1005 } else {
1006 printf(" num_pipes = %u\n",
1007 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1008 printf(" pipe_interleave_size = %u\n",
1009 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
1010 printf(" bank_interleave_size = %u\n",
1011 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1012 printf(" num_shader_engines = %u\n",
1013 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
1014 printf(" shader_engine_tile_size = %u\n",
1015 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1016 printf(" num_gpus = %u (raw)\n",
1017 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
1018 printf(" multi_gpu_tile_size = %u (raw)\n",
1019 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1020 printf(" row_size = %u\n",
1021 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1022 printf(" num_lower_pipes = %u (raw)\n",
1023 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1024 }
1025 }
1026
1027 int
1028 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
1029 {
1030 if (chip_class >= GFX9)
1031 return -1;
1032
1033 switch (family) {
1034 case CHIP_OLAND:
1035 case CHIP_HAINAN:
1036 case CHIP_KAVERI:
1037 case CHIP_KABINI:
1038 case CHIP_ICELAND:
1039 case CHIP_CARRIZO:
1040 case CHIP_STONEY:
1041 return 16;
1042 case CHIP_TAHITI:
1043 case CHIP_PITCAIRN:
1044 case CHIP_VERDE:
1045 case CHIP_BONAIRE:
1046 case CHIP_HAWAII:
1047 case CHIP_TONGA:
1048 case CHIP_FIJI:
1049 case CHIP_POLARIS10:
1050 case CHIP_POLARIS11:
1051 case CHIP_POLARIS12:
1052 case CHIP_VEGAM:
1053 return 32;
1054 default:
1055 unreachable("Unknown GPU");
1056 }
1057 }
1058
1059 void
1060 ac_get_raster_config(struct radeon_info *info,
1061 uint32_t *raster_config_p,
1062 uint32_t *raster_config_1_p,
1063 uint32_t *se_tile_repeat_p)
1064 {
1065 unsigned raster_config, raster_config_1, se_tile_repeat;
1066
1067 switch (info->family) {
1068 /* 1 SE / 1 RB */
1069 case CHIP_HAINAN:
1070 case CHIP_KABINI:
1071 case CHIP_STONEY:
1072 raster_config = 0x00000000;
1073 raster_config_1 = 0x00000000;
1074 break;
1075 /* 1 SE / 4 RBs */
1076 case CHIP_VERDE:
1077 raster_config = 0x0000124a;
1078 raster_config_1 = 0x00000000;
1079 break;
1080 /* 1 SE / 2 RBs (Oland is special) */
1081 case CHIP_OLAND:
1082 raster_config = 0x00000082;
1083 raster_config_1 = 0x00000000;
1084 break;
1085 /* 1 SE / 2 RBs */
1086 case CHIP_KAVERI:
1087 case CHIP_ICELAND:
1088 case CHIP_CARRIZO:
1089 raster_config = 0x00000002;
1090 raster_config_1 = 0x00000000;
1091 break;
1092 /* 2 SEs / 4 RBs */
1093 case CHIP_BONAIRE:
1094 case CHIP_POLARIS11:
1095 case CHIP_POLARIS12:
1096 raster_config = 0x16000012;
1097 raster_config_1 = 0x00000000;
1098 break;
1099 /* 2 SEs / 8 RBs */
1100 case CHIP_TAHITI:
1101 case CHIP_PITCAIRN:
1102 raster_config = 0x2a00126a;
1103 raster_config_1 = 0x00000000;
1104 break;
1105 /* 4 SEs / 8 RBs */
1106 case CHIP_TONGA:
1107 case CHIP_POLARIS10:
1108 raster_config = 0x16000012;
1109 raster_config_1 = 0x0000002a;
1110 break;
1111 /* 4 SEs / 16 RBs */
1112 case CHIP_HAWAII:
1113 case CHIP_FIJI:
1114 case CHIP_VEGAM:
1115 raster_config = 0x3a00161a;
1116 raster_config_1 = 0x0000002e;
1117 break;
1118 default:
1119 fprintf(stderr,
1120 "ac: Unknown GPU, using 0 for raster_config\n");
1121 raster_config = 0x00000000;
1122 raster_config_1 = 0x00000000;
1123 break;
1124 }
1125
1126 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
1127 * This decreases performance by up to 50% when the RB is the bottleneck.
1128 */
1129 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
1130 raster_config = 0x00000000;
1131
1132 /* Fiji: Old kernels have incorrect tiling config. This decreases
1133 * RB performance by 25%. (it disables 1 RB in the second packer)
1134 */
1135 if (info->family == CHIP_FIJI &&
1136 info->cik_macrotile_mode_array[0] == 0x000000e8) {
1137 raster_config = 0x16000012;
1138 raster_config_1 = 0x0000002a;
1139 }
1140
1141 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
1142 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
1143
1144 /* I don't know how to calculate this, though this is probably a good guess. */
1145 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
1146
1147 *raster_config_p = raster_config;
1148 *raster_config_1_p = raster_config_1;
1149 if (se_tile_repeat_p)
1150 *se_tile_repeat_p = se_tile_repeat;
1151 }
1152
1153 void
1154 ac_get_harvested_configs(struct radeon_info *info,
1155 unsigned raster_config,
1156 unsigned *cik_raster_config_1_p,
1157 unsigned *raster_config_se)
1158 {
1159 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
1160 unsigned num_se = MAX2(info->max_se, 1);
1161 unsigned rb_mask = info->enabled_rb_mask;
1162 unsigned num_rb = MIN2(info->num_render_backends, 16);
1163 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
1164 unsigned rb_per_se = num_rb / num_se;
1165 unsigned se_mask[4];
1166 unsigned se;
1167
1168 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1169 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1170 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1171 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1172
1173 assert(num_se == 1 || num_se == 2 || num_se == 4);
1174 assert(sh_per_se == 1 || sh_per_se == 2);
1175 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
1176
1177
1178 if (info->chip_class >= GFX7) {
1179 unsigned raster_config_1 = *cik_raster_config_1_p;
1180 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1181 (!se_mask[2] && !se_mask[3]))) {
1182 raster_config_1 &= C_028354_SE_PAIR_MAP;
1183
1184 if (!se_mask[0] && !se_mask[1]) {
1185 raster_config_1 |=
1186 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
1187 } else {
1188 raster_config_1 |=
1189 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
1190 }
1191 *cik_raster_config_1_p = raster_config_1;
1192 }
1193 }
1194
1195 for (se = 0; se < num_se; se++) {
1196 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1197 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1198 int idx = (se / 2) * 2;
1199
1200 raster_config_se[se] = raster_config;
1201 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1202 raster_config_se[se] &= C_028350_SE_MAP;
1203
1204 if (!se_mask[idx]) {
1205 raster_config_se[se] |=
1206 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
1207 } else {
1208 raster_config_se[se] |=
1209 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
1210 }
1211 }
1212
1213 pkr0_mask &= rb_mask;
1214 pkr1_mask &= rb_mask;
1215 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1216 raster_config_se[se] &= C_028350_PKR_MAP;
1217
1218 if (!pkr0_mask) {
1219 raster_config_se[se] |=
1220 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
1221 } else {
1222 raster_config_se[se] |=
1223 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
1224 }
1225 }
1226
1227 if (rb_per_se >= 2) {
1228 unsigned rb0_mask = 1 << (se * rb_per_se);
1229 unsigned rb1_mask = rb0_mask << 1;
1230
1231 rb0_mask &= rb_mask;
1232 rb1_mask &= rb_mask;
1233 if (!rb0_mask || !rb1_mask) {
1234 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
1235
1236 if (!rb0_mask) {
1237 raster_config_se[se] |=
1238 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
1239 } else {
1240 raster_config_se[se] |=
1241 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
1242 }
1243 }
1244
1245 if (rb_per_se > 2) {
1246 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1247 rb1_mask = rb0_mask << 1;
1248 rb0_mask &= rb_mask;
1249 rb1_mask &= rb_mask;
1250 if (!rb0_mask || !rb1_mask) {
1251 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
1252
1253 if (!rb0_mask) {
1254 raster_config_se[se] |=
1255 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
1256 } else {
1257 raster_config_se[se] |=
1258 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
1259 }
1260 }
1261 }
1262 }
1263 }
1264 }
1265
1266 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
1267 unsigned waves_per_threadgroup,
1268 unsigned max_waves_per_sh,
1269 unsigned threadgroups_per_cu)
1270 {
1271 unsigned compute_resource_limits =
1272 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
1273
1274 if (info->chip_class >= GFX7) {
1275 unsigned num_cu_per_se = info->num_good_compute_units /
1276 info->max_se;
1277
1278 /* Force even distribution on all SIMDs in CU if the workgroup
1279 * size is 64. This has shown some good improvements if # of CUs
1280 * per SE is not a multiple of 4.
1281 */
1282 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
1283 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
1284
1285 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
1286 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
1287 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
1288 } else {
1289 /* GFX6 */
1290 if (max_waves_per_sh) {
1291 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
1292 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
1293 }
1294 }
1295 return compute_resource_limits;
1296 }