src/amd/common/ac_gpu_info.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_GPU_INFO_H
  27 #define AC_GPU_INFO_H
  28
  29 #include <stddef.h>
  30 #include <stdint.h>
  31 #include <stdbool.h>
  32 #include "amd_family.h"
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 struct amdgpu_gpu_info;
  39
  40 struct radeon_info {
  41         /* PCI info: domain:bus:dev:func */
  42         uint32_t                    pci_domain;
  43         uint32_t                    pci_bus;
  44         uint32_t                    pci_dev;
  45         uint32_t                    pci_func;
  46
  47         /* Device info. */
  48         const char                  *name;
  49         const char                  *marketing_name;
  50         bool                        is_pro_graphics;
  51         uint32_t                    pci_id;
  52         uint32_t                    pci_rev_id;
  53         enum radeon_family          family;
  54         enum chip_class             chip_class;
  55         uint32_t                    family_id;
  56         uint32_t                    chip_external_rev;
  57         uint32_t                    clock_crystal_freq;
  58
  59         /* Features. */
  60         bool                        has_graphics; /* false if the chip is compute-only */
  61         uint32_t                    num_rings[NUM_RING_TYPES];
  62         uint32_t                    ib_pad_dw_mask[NUM_RING_TYPES];
  63         bool                        has_clear_state;
  64         bool                        has_distributed_tess;
  65         bool                        has_dcc_constant_encode;
  66         bool                        has_rbplus; /* if RB+ registers exist */
  67         bool                        rbplus_allowed; /* if RB+ is allowed */
  68         bool                        has_load_ctx_reg_pkt;
  69         bool                        has_out_of_order_rast;
  70         bool                        has_packed_math_16bit;
  71         bool                        cpdma_prefetch_writes_memory;
  72         bool                        has_gfx9_scissor_bug;
  73         bool                        has_tc_compat_zrange_bug;
  74         bool                        has_msaa_sample_loc_bug;
  75         bool                        has_ls_vgpr_init_bug;
  76
  77         /* Display features. */
  78         /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
  79         /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
  80         bool                        use_display_dcc_unaligned;
  81         /* Allocate both aligned and unaligned DCC and use the retile blit. */
  82         bool                        use_display_dcc_with_retile_blit;
  83
  84         /* Memory info. */
  85         uint32_t                    pte_fragment_size;
  86         uint32_t                    gart_page_size;
  87         uint64_t                    gart_size;
  88         uint64_t                    vram_size;
  89         uint64_t                    vram_vis_size;
  90         uint32_t                    vram_bit_width;
  91         uint32_t                    vram_type;
  92         unsigned                    gds_size;
  93         unsigned                    gds_gfx_partition_size;
  94         uint64_t                    max_alloc_size;
  95         uint32_t                    min_alloc_size;
  96         uint32_t                    address32_hi;
  97         bool                        has_dedicated_vram;
  98         bool                        has_l2_uncached;
  99         bool                        r600_has_virtual_memory;
 100         uint32_t                    num_sdp_interfaces;
 101         uint32_t                    num_tcc_blocks;
 102         uint32_t                    tcc_cache_line_size;
 103         bool                        tcc_harvested;
 104         unsigned                    pc_lines;
 105         uint32_t                    lds_size_per_workgroup;
 106         uint32_t                    lds_granularity;
 107         uint32_t                    max_memory_clock;
 108         uint32_t                    ce_ram_size;
 109         uint32_t                    l1_cache_size;
 110         uint32_t                    l2_cache_size;
 111
 112         /* CP info. */
 113         bool                        gfx_ib_pad_with_type2;
 114         unsigned                    ib_alignment; /* both start and size alignment */
 115         uint32_t                    me_fw_version;
 116         uint32_t                    me_fw_feature;
 117         uint32_t                    pfp_fw_version;
 118         uint32_t                    pfp_fw_feature;
 119         uint32_t                    ce_fw_version;
 120         uint32_t                    ce_fw_feature;
 121
 122         /* Multimedia info. */
 123         bool                        has_hw_decode;
 124         bool                        uvd_enc_supported;
 125         uint32_t                    uvd_fw_version;
 126         uint32_t                    vce_fw_version;
 127         uint32_t                    vce_harvest_config;
 128
 129         /* Kernel & winsys capabilities. */
 130         uint32_t                    drm_major; /* version */
 131         uint32_t                    drm_minor;
 132         uint32_t                    drm_patchlevel;
 133         bool                        is_amdgpu;
 134         bool                        has_userptr;
 135         bool                        has_syncobj;
 136         bool                        has_syncobj_wait_for_submit;
 137         bool                        has_fence_to_handle;
 138         bool                        has_ctx_priority;
 139         bool                        has_local_buffers;
 140         bool                        kernel_flushes_hdp_before_ib;
 141         bool                        htile_cmask_support_1d_tiling;
 142         bool                        si_TA_CS_BC_BASE_ADDR_allowed;
 143         bool                        has_bo_metadata;
 144         bool                        has_gpu_reset_status_query;
 145         bool                        has_eqaa_surface_allocator;
 146         bool                        has_format_bc1_through_bc7;
 147         bool                        kernel_flushes_tc_l2_after_ib;
 148         bool                        has_indirect_compute_dispatch;
 149         bool                        has_unaligned_shader_loads;
 150         bool                        has_sparse_vm_mappings;
 151         bool                        has_2d_tiling;
 152         bool                        has_read_registers_query;
 153         bool                        has_gds_ordered_append;
 154         bool                        has_scheduled_fence_dependency;
 155
 156         /* Shader cores. */
 157         uint32_t                    cu_mask[4][2];
 158         uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 159         uint32_t                    max_shader_clock;
 160         uint32_t                    num_good_compute_units;
 161         uint32_t                    max_good_cu_per_sa;
 162         uint32_t                    min_good_cu_per_sa; /* min != max if SAs have different # of CUs */
 163         uint32_t                    max_se; /* shader engines */
 164         uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 165         uint32_t                    max_wave64_per_simd;
 166         uint32_t                    num_physical_sgprs_per_simd;
 167         uint32_t                    num_physical_wave64_vgprs_per_simd;
 168         uint32_t                    num_simd_per_compute_unit;
 169         uint32_t                    min_sgpr_alloc;
 170         uint32_t                    max_sgpr_alloc;
 171         uint32_t                    sgpr_alloc_granularity;
 172         uint32_t                    min_wave64_vgpr_alloc;
 173         uint32_t                    max_vgpr_alloc;
 174         uint32_t                    wave64_vgpr_alloc_granularity;
 175         bool                        use_late_alloc; /* VS and GS: late pos/param allocation */
 176
 177         /* Render backends (color + depth blocks). */
 178         uint32_t                    r300_num_gb_pipes;
 179         uint32_t                    r300_num_z_pipes;
 180         uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 181         bool                        r600_gb_backend_map_valid;
 182         uint32_t                    r600_num_banks;
 183         uint32_t                    gb_addr_config;
 184         uint32_t                    pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */
 185         uint32_t                    num_render_backends;
 186         uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 187         uint32_t                    pipe_interleave_bytes;
 188         uint32_t                    enabled_rb_mask; /* GCN harvest config */
 189         uint64_t                    max_alignment; /* from addrlib */
 190         uint32_t                    pbb_max_alloc_count;
 191
 192         /* Tile modes. */
 193         uint32_t                    si_tile_mode_array[32];
 194         uint32_t                    cik_macrotile_mode_array[16];
 195 };
 196
 197 bool ac_query_gpu_info(int fd, void *dev_p,
 198                        struct radeon_info *info,
 199                        struct amdgpu_gpu_info *amdinfo);
 200
 201 void ac_compute_driver_uuid(char *uuid, size_t size);
 202
 203 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
 204 void ac_print_gpu_info(struct radeon_info *info);
 205 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family);
 206 void ac_get_raster_config(struct radeon_info *info,
 207                           uint32_t *raster_config_p,
 208                           uint32_t *raster_config_1_p,
 209                           uint32_t *se_tile_repeat_p);
 210 void ac_get_harvested_configs(struct radeon_info *info,
 211                               unsigned raster_config,
 212                               unsigned *cik_raster_config_1_p,
 213                               unsigned *raster_config_se);
 214 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
 215                                         unsigned waves_per_threadgroup,
 216                                         unsigned max_waves_per_sh,
 217                                         unsigned threadgroups_per_cu);
 218
 219 #ifdef __cplusplus
 220 }
 221 #endif
 222
 223 #endif /* AC_GPU_INFO_H */