2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
29 #include "amd_family.h"
39 struct amdgpu_gpu_info
;
42 /* PCI info: domain:bus:dev:func */
50 const char *marketing_name
;
54 enum radeon_family family
;
55 enum chip_class chip_class
;
57 uint32_t chip_external_rev
;
58 uint32_t clock_crystal_freq
;
61 bool has_graphics
; /* false if the chip is compute-only */
62 uint32_t num_rings
[NUM_RING_TYPES
];
63 uint32_t ib_pad_dw_mask
[NUM_RING_TYPES
];
65 bool has_distributed_tess
;
66 bool has_dcc_constant_encode
;
67 bool has_rbplus
; /* if RB+ registers exist */
68 bool rbplus_allowed
; /* if RB+ is allowed */
69 bool has_load_ctx_reg_pkt
;
70 bool has_out_of_order_rast
;
71 bool has_packed_math_16bit
;
72 bool cpdma_prefetch_writes_memory
;
73 bool has_gfx9_scissor_bug
;
74 bool has_tc_compat_zrange_bug
;
75 bool has_msaa_sample_loc_bug
;
76 bool has_ls_vgpr_init_bug
;
78 /* Display features. */
79 /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
80 /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
81 bool use_display_dcc_unaligned
;
82 /* Allocate both aligned and unaligned DCC and use the retile blit. */
83 bool use_display_dcc_with_retile_blit
;
86 uint32_t pte_fragment_size
;
87 uint32_t gart_page_size
;
90 uint64_t vram_vis_size
;
91 uint32_t vram_bit_width
;
94 unsigned gds_gfx_partition_size
;
95 uint64_t max_alloc_size
;
96 uint32_t min_alloc_size
;
97 uint32_t address32_hi
;
98 bool has_dedicated_vram
;
100 bool r600_has_virtual_memory
;
101 uint32_t num_sdp_interfaces
;
102 uint32_t num_tcc_blocks
;
103 uint32_t tcc_cache_line_size
;
106 uint32_t lds_size_per_workgroup
;
107 uint32_t lds_granularity
;
108 uint32_t max_memory_clock
;
109 uint32_t ce_ram_size
;
110 uint32_t l1_cache_size
;
111 uint32_t l2_cache_size
;
114 bool gfx_ib_pad_with_type2
;
115 unsigned ib_alignment
; /* both start and size alignment */
116 uint32_t me_fw_version
;
117 uint32_t me_fw_feature
;
118 uint32_t pfp_fw_version
;
119 uint32_t pfp_fw_feature
;
120 uint32_t ce_fw_version
;
121 uint32_t ce_fw_feature
;
123 /* Multimedia info. */
125 bool uvd_enc_supported
;
126 uint32_t uvd_fw_version
;
127 uint32_t vce_fw_version
;
128 uint32_t vce_harvest_config
;
130 /* Kernel & winsys capabilities. */
131 uint32_t drm_major
; /* version */
133 uint32_t drm_patchlevel
;
137 bool has_syncobj_wait_for_submit
;
138 bool has_timeline_syncobj
;
139 bool has_fence_to_handle
;
140 bool has_ctx_priority
;
141 bool has_local_buffers
;
142 bool kernel_flushes_hdp_before_ib
;
143 bool htile_cmask_support_1d_tiling
;
144 bool si_TA_CS_BC_BASE_ADDR_allowed
;
145 bool has_bo_metadata
;
146 bool has_gpu_reset_status_query
;
147 bool has_eqaa_surface_allocator
;
148 bool has_format_bc1_through_bc7
;
149 bool kernel_flushes_tc_l2_after_ib
;
150 bool has_indirect_compute_dispatch
;
151 bool has_unaligned_shader_loads
;
152 bool has_sparse_vm_mappings
;
154 bool has_read_registers_query
;
155 bool has_gds_ordered_append
;
156 bool has_scheduled_fence_dependency
;
157 /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */
158 bool mid_command_buffer_preemption_enabled
;
161 uint32_t cu_mask
[4][2];
162 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
163 uint32_t max_shader_clock
;
164 uint32_t num_good_compute_units
;
165 uint32_t max_good_cu_per_sa
;
166 uint32_t min_good_cu_per_sa
; /* min != max if SAs have different # of CUs */
167 uint32_t max_se
; /* shader engines */
168 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
169 uint32_t max_wave64_per_simd
;
170 uint32_t num_physical_sgprs_per_simd
;
171 uint32_t num_physical_wave64_vgprs_per_simd
;
172 uint32_t num_simd_per_compute_unit
;
173 uint32_t min_sgpr_alloc
;
174 uint32_t max_sgpr_alloc
;
175 uint32_t sgpr_alloc_granularity
;
176 uint32_t min_wave64_vgpr_alloc
;
177 uint32_t max_vgpr_alloc
;
178 uint32_t wave64_vgpr_alloc_granularity
;
179 bool use_late_alloc
; /* VS and GS: late pos/param allocation */
181 /* Render backends (color + depth blocks). */
182 uint32_t r300_num_gb_pipes
;
183 uint32_t r300_num_z_pipes
;
184 uint32_t r600_gb_backend_map
; /* R600 harvest config */
185 bool r600_gb_backend_map_valid
;
186 uint32_t r600_num_banks
;
187 uint32_t gb_addr_config
;
188 uint32_t pa_sc_tile_steering_override
; /* CLEAR_STATE also sets this */
189 uint32_t num_render_backends
;
190 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
191 uint32_t pipe_interleave_bytes
;
192 uint32_t enabled_rb_mask
; /* GCN harvest config */
193 uint64_t max_alignment
; /* from addrlib */
194 uint32_t pbb_max_alloc_count
;
197 uint32_t si_tile_mode_array
[32];
198 uint32_t cik_macrotile_mode_array
[16];
201 bool ac_query_gpu_info(int fd
, void *dev_p
, struct radeon_info
*info
,
202 struct amdgpu_gpu_info
*amdinfo
);
204 void ac_compute_driver_uuid(char *uuid
, size_t size
);
206 void ac_compute_device_uuid(struct radeon_info
*info
, char *uuid
, size_t size
);
207 void ac_print_gpu_info(struct radeon_info
*info
);
208 int ac_get_gs_table_depth(enum chip_class chip_class
, enum radeon_family family
);
209 void ac_get_raster_config(struct radeon_info
*info
, uint32_t *raster_config_p
,
210 uint32_t *raster_config_1_p
, uint32_t *se_tile_repeat_p
);
211 void ac_get_harvested_configs(struct radeon_info
*info
, unsigned raster_config
,
212 unsigned *cik_raster_config_1_p
, unsigned *raster_config_se
);
213 unsigned ac_get_compute_resource_limits(struct radeon_info
*info
, unsigned waves_per_threadgroup
,
214 unsigned max_waves_per_sh
, unsigned threadgroups_per_cu
);
220 #endif /* AC_GPU_INFO_H */