src/amd/common/ac_llvm_util.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial portions
  22  * of the Software.
  23  *
  24  */
  25 /* based on pieces from si_pipe.c and radeon_llvm_emit.c */
  26 #include "ac_llvm_util.h"
  27 #include "ac_llvm_build.h"
  28 #include "util/bitscan.h"
  29 #include <llvm-c/Core.h>
  30 #include <llvm-c/Support.h>
  31 #include <llvm-c/Transforms/IPO.h>
  32 #include <llvm-c/Transforms/Scalar.h>
  33 #include <llvm-c/Transforms/Utils.h>
  34 #include "c11/threads.h"
  35 #include "gallivm/lp_bld_misc.h"
  36 #include "util/u_math.h"
  37
  38 #include <assert.h>
  39 #include <stdio.h>
  40 #include <string.h>
  41
  42 static void ac_init_llvm_target()
  43 {
  44         LLVMInitializeAMDGPUTargetInfo();
  45         LLVMInitializeAMDGPUTarget();
  46         LLVMInitializeAMDGPUTargetMC();
  47         LLVMInitializeAMDGPUAsmPrinter();
  48
  49         /* For inline assembly. */
  50         LLVMInitializeAMDGPUAsmParser();
  51
  52         /* Workaround for bug in llvm 4.0 that causes image intrinsics
  53          * to disappear.
  54          * https://reviews.llvm.org/D26348
  55          *
  56          * "mesa" is the prefix for error messages.
  57          *
  58          * -global-isel-abort=2 is a no-op unless global isel has been enabled.
  59          * This option tells the backend to fall-back to SelectionDAG and print
  60          * a diagnostic message if global isel fails.
  61          */
  62         const char *argv[] = { "mesa", "-simplifycfg-sink-common=false", "-global-isel-abort=2" };
  63         LLVMParseCommandLineOptions(ARRAY_SIZE(argv), argv, NULL);
  64 }
  65
  66 static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
  67
  68 void ac_init_llvm_once(void)
  69 {
  70         call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
  71 }
  72
  73 static LLVMTargetRef ac_get_llvm_target(const char *triple)
  74 {
  75         LLVMTargetRef target = NULL;
  76         char *err_message = NULL;
  77
  78         if (LLVMGetTargetFromTriple(triple, &target, &err_message)) {
  79                 fprintf(stderr, "Cannot find target for triple %s ", triple);
  80                 if (err_message) {
  81                         fprintf(stderr, "%s\n", err_message);
  82                 }
  83                 LLVMDisposeMessage(err_message);
  84                 return NULL;
  85         }
  86         return target;
  87 }
  88
  89 const char *ac_get_llvm_processor_name(enum radeon_family family)
  90 {
  91         switch (family) {
  92         case CHIP_TAHITI:
  93                 return "tahiti";
  94         case CHIP_PITCAIRN:
  95                 return "pitcairn";
  96         case CHIP_VERDE:
  97                 return "verde";
  98         case CHIP_OLAND:
  99                 return "oland";
 100         case CHIP_HAINAN:
 101                 return "hainan";
 102         case CHIP_BONAIRE:
 103                 return "bonaire";
 104         case CHIP_KABINI:
 105                 return "kabini";
 106         case CHIP_KAVERI:
 107                 return "kaveri";
 108         case CHIP_HAWAII:
 109                 return "hawaii";
 110         case CHIP_TONGA:
 111                 return "tonga";
 112         case CHIP_ICELAND:
 113                 return "iceland";
 114         case CHIP_CARRIZO:
 115                 return "carrizo";
 116         case CHIP_FIJI:
 117                 return "fiji";
 118         case CHIP_STONEY:
 119                 return "stoney";
 120         case CHIP_POLARIS10:
 121                 return "polaris10";
 122         case CHIP_POLARIS11:
 123         case CHIP_POLARIS12:
 124         case CHIP_VEGAM:
 125                 return "polaris11";
 126         case CHIP_VEGA10:
 127                 return "gfx900";
 128         case CHIP_RAVEN:
 129                 return "gfx902";
 130         case CHIP_VEGA12:
 131                 return "gfx904";
 132         case CHIP_VEGA20:
 133                 return "gfx906";
 134         case CHIP_RAVEN2:
 135                 return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
 136         case CHIP_ARCTURUS:
 137                 return "gfx908";
 138         case CHIP_NAVI10:
 139                 return "gfx1010";
 140         case CHIP_NAVI12:
 141                 return "gfx1011";
 142         case CHIP_NAVI14:
 143                 return "gfx1012";
 144         default:
 145                 return "";
 146         }
 147 }
 148
 149 static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
 150                                                      enum ac_target_machine_options tm_options,
 151                                                      LLVMCodeGenOptLevel level,
 152                                                      const char **out_triple)
 153 {
 154         assert(family >= CHIP_TAHITI);
 155         char features[256];
 156         const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
 157         LLVMTargetRef target = ac_get_llvm_target(triple);
 158
 159         snprintf(features, sizeof(features),
 160                  "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s%s",
 161                  HAVE_LLVM >= 0x0800 ? "" : ",+vgpr-spilling",
 162                  family >= CHIP_NAVI10 && !(tm_options & AC_TM_WAVE32) ?
 163                          ",+wavefrontsize64,-wavefrontsize32" : "",
 164                  tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
 165                  tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
 166                  tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
 167                  tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",
 168                  tm_options & AC_TM_NO_LOAD_STORE_OPT ? ",-load-store-opt" : "");
 169
 170         LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
 171                                      target,
 172                                      triple,
 173                                      ac_get_llvm_processor_name(family),
 174                                      features,
 175                                      level,
 176                                      LLVMRelocDefault,
 177                                      LLVMCodeModelDefault);
 178
 179         if (out_triple)
 180                 *out_triple = triple;
 181         if (tm_options & AC_TM_ENABLE_GLOBAL_ISEL)
 182                 ac_enable_global_isel(tm);
 183         return tm;
 184 }
 185
 186 static LLVMPassManagerRef ac_create_passmgr(LLVMTargetLibraryInfoRef target_library_info,
 187                                             bool check_ir)
 188 {
 189         LLVMPassManagerRef passmgr = LLVMCreatePassManager();
 190         if (!passmgr)
 191                 return NULL;
 192
 193         if (target_library_info)
 194                 LLVMAddTargetLibraryInfo(target_library_info,
 195                                          passmgr);
 196
 197         if (check_ir)
 198                 LLVMAddVerifierPass(passmgr);
 199         LLVMAddAlwaysInlinerPass(passmgr);
 200         /* Normally, the pass manager runs all passes on one function before
 201          * moving onto another. Adding a barrier no-op pass forces the pass
 202          * manager to run the inliner on all functions first, which makes sure
 203          * that the following passes are only run on the remaining non-inline
 204          * function, so it removes useless work done on dead inline functions.
 205          */
 206         ac_llvm_add_barrier_noop_pass(passmgr);
 207         /* This pass should eliminate all the load and store instructions. */
 208         LLVMAddPromoteMemoryToRegisterPass(passmgr);
 209         LLVMAddScalarReplAggregatesPass(passmgr);
 210         LLVMAddLICMPass(passmgr);
 211         LLVMAddAggressiveDCEPass(passmgr);
 212         LLVMAddCFGSimplificationPass(passmgr);
 213         /* This is recommended by the instruction combining pass. */
 214         LLVMAddEarlyCSEMemSSAPass(passmgr);
 215         LLVMAddInstructionCombiningPass(passmgr);
 216         return passmgr;
 217 }
 218
 219 static const char *attr_to_str(enum ac_func_attr attr)
 220 {
 221    switch (attr) {
 222    case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
 223    case AC_FUNC_ATTR_INREG: return "inreg";
 224    case AC_FUNC_ATTR_NOALIAS: return "noalias";
 225    case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
 226    case AC_FUNC_ATTR_READNONE: return "readnone";
 227    case AC_FUNC_ATTR_READONLY: return "readonly";
 228    case AC_FUNC_ATTR_WRITEONLY: return "writeonly";
 229    case AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return "inaccessiblememonly";
 230    case AC_FUNC_ATTR_CONVERGENT: return "convergent";
 231    default:
 232            fprintf(stderr, "Unhandled function attribute: %x\n", attr);
 233            return 0;
 234    }
 235 }
 236
 237 void
 238 ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
 239                      int attr_idx, enum ac_func_attr attr)
 240 {
 241    const char *attr_name = attr_to_str(attr);
 242    unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
 243                                                       strlen(attr_name));
 244    LLVMAttributeRef llvm_attr = LLVMCreateEnumAttribute(ctx, kind_id, 0);
 245
 246    if (LLVMIsAFunction(function))
 247       LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
 248    else
 249       LLVMAddCallSiteAttribute(function, attr_idx, llvm_attr);
 250 }
 251
 252 void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,
 253                             unsigned attrib_mask)
 254 {
 255         attrib_mask |= AC_FUNC_ATTR_NOUNWIND;
 256         attrib_mask &= ~AC_FUNC_ATTR_LEGACY;
 257
 258         while (attrib_mask) {
 259                 enum ac_func_attr attr = 1u << u_bit_scan(&attrib_mask);
 260                 ac_add_function_attr(ctx, function, -1, attr);
 261         }
 262 }
 263
 264 void
 265 ac_dump_module(LLVMModuleRef module)
 266 {
 267         char *str = LLVMPrintModuleToString(module);
 268         fprintf(stderr, "%s", str);
 269         LLVMDisposeMessage(str);
 270 }
 271
 272 void
 273 ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
 274                                      const char *name, unsigned value)
 275 {
 276         char str[16];
 277
 278         snprintf(str, sizeof(str), "0x%x", value);
 279         LLVMAddTargetDependentFunctionAttr(F, name, str);
 280 }
 281
 282 void ac_llvm_set_workgroup_size(LLVMValueRef F, unsigned size)
 283 {
 284         if (!size)
 285                 return;
 286
 287         char str[32];
 288         snprintf(str, sizeof(str), "%u,%u", size, size);
 289         LLVMAddTargetDependentFunctionAttr(F, "amdgpu-flat-work-group-size", str);
 290 }
 291
 292 unsigned
 293 ac_count_scratch_private_memory(LLVMValueRef function)
 294 {
 295         unsigned private_mem_vgprs = 0;
 296
 297         /* Process all LLVM instructions. */
 298         LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(function);
 299         while (bb) {
 300                 LLVMValueRef next = LLVMGetFirstInstruction(bb);
 301
 302                 while (next) {
 303                         LLVMValueRef inst = next;
 304                         next = LLVMGetNextInstruction(next);
 305
 306                         if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
 307                                 continue;
 308
 309                         LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
 310                         /* No idea why LLVM aligns allocas to 4 elements. */
 311                         unsigned alignment = LLVMGetAlignment(inst);
 312                         unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
 313                         private_mem_vgprs += dw_size;
 314                 }
 315                 bb = LLVMGetNextBasicBlock(bb);
 316         }
 317
 318         return private_mem_vgprs;
 319 }
 320
 321 bool
 322 ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
 323                       enum radeon_family family,
 324                       enum ac_target_machine_options tm_options)
 325 {
 326         const char *triple;
 327         memset(compiler, 0, sizeof(*compiler));
 328
 329         compiler->tm = ac_create_target_machine(family, tm_options,
 330                                                 LLVMCodeGenLevelDefault,
 331                                                 &triple);
 332         if (!compiler->tm)
 333                 return false;
 334
 335         if (tm_options & AC_TM_CREATE_LOW_OPT) {
 336                 compiler->low_opt_tm =
 337                         ac_create_target_machine(family, tm_options,
 338                                                  LLVMCodeGenLevelLess, NULL);
 339                 if (!compiler->low_opt_tm)
 340                         goto fail;
 341         }
 342
 343         if (family >= CHIP_NAVI10) {
 344                 assert(!(tm_options & AC_TM_CREATE_LOW_OPT));
 345                 compiler->tm_wave32 = ac_create_target_machine(family,
 346                                                                tm_options | AC_TM_WAVE32,
 347                                                                LLVMCodeGenLevelDefault,
 348                                                                NULL);
 349                 if (!compiler->tm_wave32)
 350                         goto fail;
 351         }
 352
 353         compiler->target_library_info =
 354                 ac_create_target_library_info(triple);
 355         if (!compiler->target_library_info)
 356                 goto fail;
 357
 358         compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
 359                                               tm_options & AC_TM_CHECK_IR);
 360         if (!compiler->passmgr)
 361                 goto fail;
 362
 363         return true;
 364 fail:
 365         ac_destroy_llvm_compiler(compiler);
 366         return false;
 367 }
 368
 369 void
 370 ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler)
 371 {
 372         ac_destroy_llvm_passes(compiler->passes);
 373         ac_destroy_llvm_passes(compiler->passes_wave32);
 374         ac_destroy_llvm_passes(compiler->low_opt_passes);
 375
 376         if (compiler->passmgr)
 377                 LLVMDisposePassManager(compiler->passmgr);
 378         if (compiler->target_library_info)
 379                 ac_dispose_target_library_info(compiler->target_library_info);
 380         if (compiler->low_opt_tm)
 381                 LLVMDisposeTargetMachine(compiler->low_opt_tm);
 382         if (compiler->tm)
 383                 LLVMDisposeTargetMachine(compiler->tm);
 384         if (compiler->tm_wave32)
 385                 LLVMDisposeTargetMachine(compiler->tm_wave32);
 386 }