src/amd/common/ac_nir_to_llvm.h

   1 /*
   2  * Copyright © 2016 Bas Nieuwenhuizen
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef AC_NIR_TO_LLVM_H
  25 #define AC_NIR_TO_LLVM_H
  26
  27 #include <stdbool.h>
  28 #include "llvm-c/Core.h"
  29 #include "llvm-c/TargetMachine.h"
  30 #include "amd_family.h"
  31 #include "../vulkan/radv_descriptor_set.h"
  32 #include "compiler/shader_enums.h"
  33 struct ac_shader_binary;
  34 struct ac_shader_config;
  35 struct nir_shader;
  36 struct nir_variable;
  37 struct radv_pipeline_layout;
  38
  39 struct ac_llvm_context;
  40 struct ac_shader_abi;
  41
  42 struct ac_vs_variant_key {
  43         uint32_t instance_rate_inputs;
  44         uint32_t as_es:1;
  45         uint32_t as_ls:1;
  46         uint32_t export_prim_id:1;
  47 };
  48
  49 struct ac_tes_variant_key {
  50         uint32_t as_es:1;
  51         uint32_t export_prim_id:1;
  52 };
  53
  54 struct ac_tcs_variant_key {
  55         struct ac_vs_variant_key vs_key;
  56         unsigned primitive_mode;
  57         unsigned input_vertices;
  58         uint32_t tes_reads_tess_factors:1;
  59 };
  60
  61 struct ac_fs_variant_key {
  62         uint32_t col_format;
  63         uint8_t log2_ps_iter_samples;
  64         uint8_t log2_num_samples;
  65         uint32_t is_int8;
  66         uint32_t is_int10;
  67         uint32_t multisample : 1;
  68 };
  69
  70 struct ac_shader_variant_key {
  71         union {
  72                 struct ac_vs_variant_key vs;
  73                 struct ac_fs_variant_key fs;
  74                 struct ac_tes_variant_key tes;
  75                 struct ac_tcs_variant_key tcs;
  76         };
  77         bool has_multiview_view_index;
  78 };
  79
  80 struct ac_nir_compiler_options {
  81         struct radv_pipeline_layout *layout;
  82         struct ac_shader_variant_key key;
  83         bool unsafe_math;
  84         bool supports_spill;
  85         bool clamp_shadow_reference;
  86         bool dump_preoptir;
  87         enum radeon_family family;
  88         enum chip_class chip_class;
  89 };
  90
  91 enum ac_ud_index {
  92         AC_UD_SCRATCH_RING_OFFSETS = 0,
  93         AC_UD_PUSH_CONSTANTS = 1,
  94         AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
  95         AC_UD_VIEW_INDEX = 3,
  96         AC_UD_SHADER_START = 4,
  97         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
  98         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
  99         AC_UD_VS_LS_TCS_IN_LAYOUT,
 100         AC_UD_VS_MAX_UD,
 101         AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
 102         AC_UD_PS_MAX_UD,
 103         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 104         AC_UD_CS_MAX_UD,
 105         AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
 106         AC_UD_GS_MAX_UD,
 107         AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
 108         AC_UD_TCS_MAX_UD,
 109         AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
 110         AC_UD_TES_MAX_UD,
 111         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 112 };
 113
 114 /* Interpolation locations */
 115 #define INTERP_CENTER 0
 116 #define INTERP_CENTROID 1
 117 #define INTERP_SAMPLE 2
 118
 119 static inline unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
 120 {
 121         return (index * 4) + chan;
 122 }
 123
 124 void ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class);
 125
 126 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
 127                       struct nir_shader *nir);
 128
 129 void
 130 ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
 131                              struct ac_shader_abi *abi,
 132                              struct nir_shader *nir,
 133                              struct nir_variable *variable,
 134                              gl_shader_stage stage);
 135
 136 void ac_emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage);
 137
 138 bool ac_lower_subgroups(struct nir_shader *shader);
 139
 140 #endif /* AC_NIR_TO_LLVM_H */