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1677d1b3155f4c1e3ec259baf281b1127cf4a358
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "amdgpu_id.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_math.h"
34
35 #include <errno.h>
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40
41 #include "addrlib/addrinterface.h"
42
43 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
44 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
45 #endif
46
47 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
48 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
49 #endif
50
51 static void addrlib_family_rev_id(enum radeon_family family,
52 unsigned *addrlib_family,
53 unsigned *addrlib_revid)
54 {
55 switch (family) {
56 case CHIP_TAHITI:
57 *addrlib_family = FAMILY_SI;
58 *addrlib_revid = SI_TAHITI_P_A0;
59 break;
60 case CHIP_PITCAIRN:
61 *addrlib_family = FAMILY_SI;
62 *addrlib_revid = SI_PITCAIRN_PM_A0;
63 break;
64 case CHIP_VERDE:
65 *addrlib_family = FAMILY_SI;
66 *addrlib_revid = SI_CAPEVERDE_M_A0;
67 break;
68 case CHIP_OLAND:
69 *addrlib_family = FAMILY_SI;
70 *addrlib_revid = SI_OLAND_M_A0;
71 break;
72 case CHIP_HAINAN:
73 *addrlib_family = FAMILY_SI;
74 *addrlib_revid = SI_HAINAN_V_A0;
75 break;
76 case CHIP_BONAIRE:
77 *addrlib_family = FAMILY_CI;
78 *addrlib_revid = CI_BONAIRE_M_A0;
79 break;
80 case CHIP_KAVERI:
81 *addrlib_family = FAMILY_KV;
82 *addrlib_revid = KV_SPECTRE_A0;
83 break;
84 case CHIP_KABINI:
85 *addrlib_family = FAMILY_KV;
86 *addrlib_revid = KB_KALINDI_A0;
87 break;
88 case CHIP_HAWAII:
89 *addrlib_family = FAMILY_CI;
90 *addrlib_revid = CI_HAWAII_P_A0;
91 break;
92 case CHIP_MULLINS:
93 *addrlib_family = FAMILY_KV;
94 *addrlib_revid = ML_GODAVARI_A0;
95 break;
96 case CHIP_TONGA:
97 *addrlib_family = FAMILY_VI;
98 *addrlib_revid = VI_TONGA_P_A0;
99 break;
100 case CHIP_ICELAND:
101 *addrlib_family = FAMILY_VI;
102 *addrlib_revid = VI_ICELAND_M_A0;
103 break;
104 case CHIP_CARRIZO:
105 *addrlib_family = FAMILY_CZ;
106 *addrlib_revid = CARRIZO_A0;
107 break;
108 case CHIP_STONEY:
109 *addrlib_family = FAMILY_CZ;
110 *addrlib_revid = STONEY_A0;
111 break;
112 case CHIP_FIJI:
113 *addrlib_family = FAMILY_VI;
114 *addrlib_revid = VI_FIJI_P_A0;
115 break;
116 case CHIP_POLARIS10:
117 *addrlib_family = FAMILY_VI;
118 *addrlib_revid = VI_POLARIS10_P_A0;
119 break;
120 case CHIP_POLARIS11:
121 *addrlib_family = FAMILY_VI;
122 *addrlib_revid = VI_POLARIS11_M_A0;
123 break;
124 case CHIP_POLARIS12:
125 *addrlib_family = FAMILY_VI;
126 *addrlib_revid = VI_POLARIS12_V_A0;
127 break;
128 case CHIP_VEGA10:
129 *addrlib_family = FAMILY_AI;
130 *addrlib_revid = AI_VEGA10_P_A0;
131 break;
132 case CHIP_RAVEN:
133 *addrlib_family = FAMILY_RV;
134 *addrlib_revid = RAVEN_A0;
135 break;
136 default:
137 fprintf(stderr, "amdgpu: Unknown family.\n");
138 }
139 }
140
141 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
142 {
143 return malloc(pInput->sizeInBytes);
144 }
145
146 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
147 {
148 free(pInput->pVirtAddr);
149 return ADDR_OK;
150 }
151
152 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
153 const struct amdgpu_gpu_info *amdinfo,
154 uint64_t *max_alignment)
155 {
156 ADDR_CREATE_INPUT addrCreateInput = {0};
157 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
158 ADDR_REGISTER_VALUE regValue = {0};
159 ADDR_CREATE_FLAGS createFlags = {{0}};
160 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
161 ADDR_E_RETURNCODE addrRet;
162
163 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
164 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
165
166 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
167 createFlags.value = 0;
168
169 addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
170 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
171 return NULL;
172
173 if (addrCreateInput.chipFamily >= FAMILY_AI) {
174 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
175 regValue.blockVarSizeLog2 = 0;
176 } else {
177 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
178 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
179
180 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
181 regValue.pTileConfig = amdinfo->gb_tile_mode;
182 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
183 if (addrCreateInput.chipFamily == FAMILY_SI) {
184 regValue.pMacroTileConfig = NULL;
185 regValue.noOfMacroEntries = 0;
186 } else {
187 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
188 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
189 }
190
191 createFlags.useTileIndex = 1;
192 createFlags.useHtileSliceAlign = 1;
193
194 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
195 }
196
197 addrCreateInput.callbacks.allocSysMem = allocSysMem;
198 addrCreateInput.callbacks.freeSysMem = freeSysMem;
199 addrCreateInput.callbacks.debugPrint = 0;
200 addrCreateInput.createFlags = createFlags;
201 addrCreateInput.regValue = regValue;
202
203 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
204 if (addrRet != ADDR_OK)
205 return NULL;
206
207 if (max_alignment) {
208 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
209 if (addrRet == ADDR_OK){
210 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
211 }
212 }
213 return addrCreateOutput.hLib;
214 }
215
216 static int surf_config_sanity(const struct ac_surf_config *config)
217 {
218 /* all dimension must be at least 1 ! */
219 if (!config->info.width || !config->info.height || !config->info.depth ||
220 !config->info.array_size || !config->info.levels)
221 return -EINVAL;
222
223 switch (config->info.samples) {
224 case 0:
225 case 1:
226 case 2:
227 case 4:
228 case 8:
229 break;
230 default:
231 return -EINVAL;
232 }
233
234 if (config->is_3d && config->info.array_size > 1)
235 return -EINVAL;
236 if (config->is_cube && config->info.depth > 1)
237 return -EINVAL;
238
239 return 0;
240 }
241
242 static int gfx6_compute_level(ADDR_HANDLE addrlib,
243 const struct ac_surf_config *config,
244 struct radeon_surf *surf, bool is_stencil,
245 unsigned level, bool compressed,
246 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
247 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
248 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
249 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
250 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
251 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
252 {
253 struct legacy_surf_level *surf_level;
254 ADDR_E_RETURNCODE ret;
255
256 AddrSurfInfoIn->mipLevel = level;
257 AddrSurfInfoIn->width = u_minify(config->info.width, level);
258 AddrSurfInfoIn->height = u_minify(config->info.height, level);
259
260 if (config->is_3d)
261 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
262 else if (config->is_cube)
263 AddrSurfInfoIn->numSlices = 6;
264 else
265 AddrSurfInfoIn->numSlices = config->info.array_size;
266
267 if (level > 0) {
268 /* Set the base level pitch. This is needed for calculation
269 * of non-zero levels. */
270 if (is_stencil)
271 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
272 else
273 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
274
275 /* Convert blocks to pixels for compressed formats. */
276 if (compressed)
277 AddrSurfInfoIn->basePitch *= surf->blk_w;
278 }
279
280 ret = AddrComputeSurfaceInfo(addrlib,
281 AddrSurfInfoIn,
282 AddrSurfInfoOut);
283 if (ret != ADDR_OK) {
284 return ret;
285 }
286
287 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
288 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
289 surf_level->slice_size = AddrSurfInfoOut->sliceSize;
290 surf_level->nblk_x = AddrSurfInfoOut->pitch;
291 surf_level->nblk_y = AddrSurfInfoOut->height;
292
293 switch (AddrSurfInfoOut->tileMode) {
294 case ADDR_TM_LINEAR_ALIGNED:
295 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
296 break;
297 case ADDR_TM_1D_TILED_THIN1:
298 surf_level->mode = RADEON_SURF_MODE_1D;
299 break;
300 case ADDR_TM_2D_TILED_THIN1:
301 surf_level->mode = RADEON_SURF_MODE_2D;
302 break;
303 default:
304 assert(0);
305 }
306
307 if (is_stencil)
308 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
309 else
310 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
311
312 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
313
314 /* Clear DCC fields at the beginning. */
315 surf_level->dcc_offset = 0;
316
317 /* The previous level's flag tells us if we can use DCC for this level. */
318 if (AddrSurfInfoIn->flags.dccCompatible &&
319 (level == 0 || AddrDccOut->subLvlCompressible)) {
320 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
321 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
322 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
323 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
324 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
325
326 ret = AddrComputeDccInfo(addrlib,
327 AddrDccIn,
328 AddrDccOut);
329
330 if (ret == ADDR_OK) {
331 surf_level->dcc_offset = surf->dcc_size;
332 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
333 surf->num_dcc_levels = level + 1;
334 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
335 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
336 }
337 }
338
339 /* TC-compatible HTILE. */
340 if (!is_stencil &&
341 AddrSurfInfoIn->flags.depth &&
342 surf_level->mode == RADEON_SURF_MODE_2D &&
343 level == 0) {
344 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
345 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
346 AddrHtileIn->height = AddrSurfInfoOut->height;
347 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
348 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
349 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
350 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
351 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
352 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
353
354 ret = AddrComputeHtileInfo(addrlib,
355 AddrHtileIn,
356 AddrHtileOut);
357
358 if (ret == ADDR_OK) {
359 surf->htile_size = AddrHtileOut->htileBytes;
360 surf->htile_slice_size = AddrHtileOut->sliceSize;
361 surf->htile_alignment = AddrHtileOut->baseAlign;
362 }
363 }
364
365 return 0;
366 }
367
368 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
369 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
370
371 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
372 const struct radeon_info *info)
373 {
374 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
375
376 if (info->chip_class >= CIK)
377 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
378 else
379 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
380 }
381
382 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
383 {
384 unsigned index, tileb;
385
386 tileb = 8 * 8 * surf->bpe;
387 tileb = MIN2(surf->u.legacy.tile_split, tileb);
388
389 for (index = 0; tileb > 64; index++)
390 tileb >>= 1;
391
392 assert(index < 16);
393 return index;
394 }
395
396 /**
397 * Copy surface-global settings like pipe/bank config from level 0 surface
398 * computation.
399 */
400 static void gfx6_surface_settings(const struct radeon_info* info,
401 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
402 struct radeon_surf *surf)
403 {
404 surf->surf_alignment = csio->baseAlign;
405 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
406 gfx6_set_micro_tile_mode(surf, info);
407
408 /* For 2D modes only. */
409 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
410 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
411 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
412 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
413 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
414 surf->u.legacy.num_banks = csio->pTileInfo->banks;
415 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
416 } else {
417 surf->u.legacy.macro_tile_index = 0;
418 }
419 }
420
421 /**
422 * Fill in the tiling information in \p surf based on the given surface config.
423 *
424 * The following fields of \p surf must be initialized by the caller:
425 * blk_w, blk_h, bpe, flags.
426 */
427 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
428 const struct radeon_info *info,
429 const struct ac_surf_config *config,
430 enum radeon_surf_mode mode,
431 struct radeon_surf *surf)
432 {
433 unsigned level;
434 bool compressed;
435 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
436 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
437 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
438 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
439 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
440 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
441 ADDR_TILEINFO AddrTileInfoIn = {0};
442 ADDR_TILEINFO AddrTileInfoOut = {0};
443 int r;
444
445 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
446 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
447 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
448 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
449 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
450 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
451 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
452
453 compressed = surf->blk_w == 4 && surf->blk_h == 4;
454
455 /* MSAA and FMASK require 2D tiling. */
456 if (config->info.samples > 1 ||
457 (surf->flags & RADEON_SURF_FMASK))
458 mode = RADEON_SURF_MODE_2D;
459
460 /* DB doesn't support linear layouts. */
461 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
462 mode < RADEON_SURF_MODE_1D)
463 mode = RADEON_SURF_MODE_1D;
464
465 /* Set the requested tiling mode. */
466 switch (mode) {
467 case RADEON_SURF_MODE_LINEAR_ALIGNED:
468 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
469 break;
470 case RADEON_SURF_MODE_1D:
471 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
472 break;
473 case RADEON_SURF_MODE_2D:
474 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
475 break;
476 default:
477 assert(0);
478 }
479
480 /* The format must be set correctly for the allocation of compressed
481 * textures to work. In other cases, setting the bpp is sufficient.
482 */
483 if (compressed) {
484 switch (surf->bpe) {
485 case 8:
486 AddrSurfInfoIn.format = ADDR_FMT_BC1;
487 break;
488 case 16:
489 AddrSurfInfoIn.format = ADDR_FMT_BC3;
490 break;
491 default:
492 assert(0);
493 }
494 }
495 else {
496 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
497 }
498
499 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
500 config->info.samples ? config->info.samples : 1;
501 AddrSurfInfoIn.tileIndex = -1;
502
503 /* Set the micro tile type. */
504 if (surf->flags & RADEON_SURF_SCANOUT)
505 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
506 else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
507 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
508 else
509 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
510
511 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
512 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
513 AddrSurfInfoIn.flags.cube = config->is_cube;
514 AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
515 AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
516 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
517 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
518
519 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
520 * requested, because TC-compatible HTILE requires 2D tiling.
521 */
522 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
523 !AddrSurfInfoIn.flags.fmask &&
524 config->info.samples <= 1 &&
525 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
526
527 /* DCC notes:
528 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
529 * with samples >= 4.
530 * - Mipmapped array textures have low performance (discovered by a closed
531 * driver team).
532 */
533 AddrSurfInfoIn.flags.dccCompatible =
534 info->chip_class >= VI &&
535 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
536 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
537 !compressed && AddrDccIn.numSamples <= 1 &&
538 ((config->info.array_size == 1 && config->info.depth == 1) ||
539 config->info.levels == 1);
540
541 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
542 AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
543
544 /* noStencil = 0 can result in a depth part that is incompatible with
545 * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
546 * this case, we may end up setting stencil_adjusted).
547 *
548 * TODO: update addrlib to a newer version, remove this, and
549 * use flags.matchStencilTileCfg = 1 as an alternative fix.
550 */
551 if (config->info.levels > 1)
552 AddrSurfInfoIn.flags.noStencil = 1;
553
554 /* Set preferred macrotile parameters. This is usually required
555 * for shared resources. This is for 2D tiling only. */
556 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
557 surf->u.legacy.bankw && surf->u.legacy.bankh &&
558 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
559 assert(!(surf->flags & RADEON_SURF_FMASK));
560
561 /* If any of these parameters are incorrect, the calculation
562 * will fail. */
563 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
564 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
565 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
566 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
567 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
568 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
569 AddrSurfInfoIn.flags.opt4Space = 0;
570 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
571
572 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
573 * the tile index, because we are expected to know it if
574 * we know the other parameters.
575 *
576 * This is something that can easily be fixed in Addrlib.
577 * For now, just figure it out here.
578 * Note that only 2D_TILE_THIN1 is handled here.
579 */
580 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
581 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
582
583 if (info->chip_class == SI) {
584 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
585 if (surf->bpe == 2)
586 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
587 else
588 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
589 } else {
590 if (surf->bpe == 1)
591 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
592 else if (surf->bpe == 2)
593 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
594 else if (surf->bpe == 4)
595 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
596 else
597 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
598 }
599 } else {
600 /* CIK - VI */
601 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
602 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
603 else
604 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
605
606 /* Addrlib doesn't set this if tileIndex is forced like above. */
607 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
608 }
609 }
610
611 surf->num_dcc_levels = 0;
612 surf->surf_size = 0;
613 surf->dcc_size = 0;
614 surf->dcc_alignment = 1;
615 surf->htile_size = 0;
616 surf->htile_slice_size = 0;
617 surf->htile_alignment = 1;
618
619 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
620 !(surf->flags & RADEON_SURF_ZBUFFER);
621
622 /* Calculate texture layout information. */
623 if (!only_stencil) {
624 for (level = 0; level < config->info.levels; level++) {
625 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
626 &AddrSurfInfoIn, &AddrSurfInfoOut,
627 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
628 if (r)
629 return r;
630
631 if (level > 0)
632 continue;
633
634 gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
635 }
636 }
637
638 /* Calculate texture layout information for stencil. */
639 if (surf->flags & RADEON_SURF_SBUFFER) {
640 AddrSurfInfoIn.bpp = 8;
641 AddrSurfInfoIn.flags.depth = 0;
642 AddrSurfInfoIn.flags.stencil = 1;
643 AddrSurfInfoIn.flags.tcCompatible = 0;
644 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
645 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
646
647 for (level = 0; level < config->info.levels; level++) {
648 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
649 &AddrSurfInfoIn, &AddrSurfInfoOut,
650 &AddrDccIn, &AddrDccOut,
651 NULL, NULL);
652 if (r)
653 return r;
654
655 /* DB uses the depth pitch for both stencil and depth. */
656 if (!only_stencil) {
657 if (surf->u.legacy.stencil_level[level].nblk_x !=
658 surf->u.legacy.level[level].nblk_x)
659 surf->u.legacy.stencil_adjusted = true;
660 } else {
661 surf->u.legacy.level[level].nblk_x =
662 surf->u.legacy.stencil_level[level].nblk_x;
663 }
664
665 if (level == 0) {
666 if (only_stencil)
667 gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
668
669 /* For 2D modes only. */
670 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
671 surf->u.legacy.stencil_tile_split =
672 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
673 }
674 }
675 }
676 }
677
678 /* Recalculate the whole DCC miptree size including disabled levels.
679 * This is what addrlib does, but calling addrlib would be a lot more
680 * complicated.
681 */
682 if (surf->dcc_size && config->info.levels > 1) {
683 surf->dcc_size = align64(surf->surf_size >> 8,
684 info->pipe_interleave_bytes *
685 info->num_tile_pipes);
686 }
687
688 /* Make sure HTILE covers the whole miptree, because the shader reads
689 * TC-compatible HTILE even for levels where it's disabled by DB.
690 */
691 if (surf->htile_size && config->info.levels > 1)
692 surf->htile_size *= 2;
693
694 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
695
696 /* workout base swizzle */
697 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
698 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
699 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
700
701 AddrBaseSwizzleIn.surfIndex = config->info.surf_index;
702 AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
703 AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex;
704 AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
705 AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode;
706 AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn, &AddrBaseSwizzleOut);
707 surf->u.legacy.tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
708 }
709 return 0;
710 }
711
712 /* This is only called when expecting a tiled layout. */
713 static int
714 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
715 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
716 bool is_fmask, AddrSwizzleMode *swizzle_mode)
717 {
718 ADDR_E_RETURNCODE ret;
719 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
720 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
721
722 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
723 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
724
725 sin.flags = in->flags;
726 sin.resourceType = in->resourceType;
727 sin.format = in->format;
728 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
729 /* TODO: We could allow some of these: */
730 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
731 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
732 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
733 sin.bpp = in->bpp;
734 sin.width = in->width;
735 sin.height = in->height;
736 sin.numSlices = in->numSlices;
737 sin.numMipLevels = in->numMipLevels;
738 sin.numSamples = in->numSamples;
739 sin.numFrags = in->numFrags;
740
741 if (is_fmask) {
742 sin.flags.color = 0;
743 sin.flags.fmask = 1;
744 }
745
746 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
747 if (ret != ADDR_OK)
748 return ret;
749
750 *swizzle_mode = sout.swizzleMode;
751 return 0;
752 }
753
754 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
755 struct radeon_surf *surf, bool compressed,
756 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
757 {
758 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
759 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
760 ADDR_E_RETURNCODE ret;
761
762 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
763 out.pMipInfo = mip_info;
764
765 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
766 if (ret != ADDR_OK)
767 return ret;
768
769 if (in->flags.stencil) {
770 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
771 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
772 out.mipChainPitch - 1;
773 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
774 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
775 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
776 return 0;
777 }
778
779 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
780 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
781 out.mipChainPitch - 1;
782
783 /* CMASK fast clear uses these even if FMASK isn't allocated.
784 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
785 */
786 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
787 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
788
789 surf->u.gfx9.surf_slice_size = out.sliceSize;
790 surf->u.gfx9.surf_pitch = out.pitch;
791 surf->u.gfx9.surf_height = out.height;
792 surf->surf_size = out.surfSize;
793 surf->surf_alignment = out.baseAlign;
794
795 if (in->swizzleMode == ADDR_SW_LINEAR) {
796 for (unsigned i = 0; i < in->numMipLevels; i++)
797 surf->u.gfx9.offset[i] = mip_info[i].offset;
798 }
799
800 if (in->flags.depth) {
801 assert(in->swizzleMode != ADDR_SW_LINEAR);
802
803 /* HTILE */
804 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
805 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
806
807 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
808 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
809
810 hin.hTileFlags.pipeAligned = 1;
811 hin.hTileFlags.rbAligned = 1;
812 hin.depthFlags = in->flags;
813 hin.swizzleMode = in->swizzleMode;
814 hin.unalignedWidth = in->width;
815 hin.unalignedHeight = in->height;
816 hin.numSlices = in->numSlices;
817 hin.numMipLevels = in->numMipLevels;
818
819 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
820 if (ret != ADDR_OK)
821 return ret;
822
823 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
824 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
825 surf->htile_size = hout.htileBytes;
826 surf->htile_slice_size = hout.sliceSize;
827 surf->htile_alignment = hout.baseAlign;
828 } else {
829 /* DCC */
830 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
831 !(surf->flags & RADEON_SURF_SCANOUT) &&
832 !compressed &&
833 in->swizzleMode != ADDR_SW_LINEAR &&
834 /* TODO: We could support DCC with MSAA. */
835 in->numSamples == 1) {
836 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
837 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
838
839 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
840 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
841
842 din.dccKeyFlags.pipeAligned = 1;
843 din.dccKeyFlags.rbAligned = 1;
844 din.colorFlags = in->flags;
845 din.resourceType = in->resourceType;
846 din.swizzleMode = in->swizzleMode;
847 din.bpp = in->bpp;
848 din.unalignedWidth = in->width;
849 din.unalignedHeight = in->height;
850 din.numSlices = in->numSlices;
851 din.numFrags = in->numFrags;
852 din.numMipLevels = in->numMipLevels;
853 din.dataSurfaceSize = out.surfSize;
854
855 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
856 if (ret != ADDR_OK)
857 return ret;
858
859 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
860 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
861 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
862 surf->dcc_size = dout.dccRamSize;
863 surf->dcc_alignment = dout.dccRamBaseAlign;
864 }
865
866 /* FMASK */
867 if (in->numSamples > 1) {
868 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
869 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
870
871 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
872 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
873
874 ret = gfx9_get_preferred_swizzle_mode(addrlib, in, true, &fin.swizzleMode);
875 if (ret != ADDR_OK)
876 return ret;
877
878 fin.unalignedWidth = in->width;
879 fin.unalignedHeight = in->height;
880 fin.numSlices = in->numSlices;
881 fin.numSamples = in->numSamples;
882 fin.numFrags = in->numFrags;
883
884 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
885 if (ret != ADDR_OK)
886 return ret;
887
888 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
889 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
890 surf->u.gfx9.fmask_size = fout.fmaskBytes;
891 surf->u.gfx9.fmask_alignment = fout.baseAlign;
892 }
893
894 /* CMASK */
895 if (in->swizzleMode != ADDR_SW_LINEAR) {
896 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
897 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
898
899 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
900 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
901
902 cin.cMaskFlags.pipeAligned = 1;
903 cin.cMaskFlags.rbAligned = 1;
904 cin.colorFlags = in->flags;
905 cin.resourceType = in->resourceType;
906 cin.unalignedWidth = in->width;
907 cin.unalignedHeight = in->height;
908 cin.numSlices = in->numSlices;
909
910 if (in->numSamples > 1)
911 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
912 else
913 cin.swizzleMode = in->swizzleMode;
914
915 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
916 if (ret != ADDR_OK)
917 return ret;
918
919 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
920 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
921 surf->u.gfx9.cmask_size = cout.cmaskBytes;
922 surf->u.gfx9.cmask_alignment = cout.baseAlign;
923 }
924 }
925
926 return 0;
927 }
928
929 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
930 const struct ac_surf_config *config,
931 enum radeon_surf_mode mode,
932 struct radeon_surf *surf)
933 {
934 bool compressed;
935 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
936 int r;
937
938 assert(!(surf->flags & RADEON_SURF_FMASK));
939
940 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
941
942 compressed = surf->blk_w == 4 && surf->blk_h == 4;
943
944 /* The format must be set correctly for the allocation of compressed
945 * textures to work. In other cases, setting the bpp is sufficient. */
946 if (compressed) {
947 switch (surf->bpe) {
948 case 8:
949 AddrSurfInfoIn.format = ADDR_FMT_BC1;
950 break;
951 case 16:
952 AddrSurfInfoIn.format = ADDR_FMT_BC3;
953 break;
954 default:
955 assert(0);
956 }
957 } else {
958 AddrSurfInfoIn.bpp = surf->bpe * 8;
959 }
960
961 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
962 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
963 AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
964 AddrSurfInfoIn.flags.texture = 1;
965 AddrSurfInfoIn.flags.opt4space = 1;
966
967 AddrSurfInfoIn.numMipLevels = config->info.levels;
968 AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
969 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
970
971 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
972 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
973 * must sample 1D textures as 2D. */
974 if (config->is_3d)
975 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
976 else
977 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
978
979 AddrSurfInfoIn.width = config->info.width;
980 AddrSurfInfoIn.height = config->info.height;
981
982 if (config->is_3d)
983 AddrSurfInfoIn.numSlices = config->info.depth;
984 else if (config->is_cube)
985 AddrSurfInfoIn.numSlices = 6;
986 else
987 AddrSurfInfoIn.numSlices = config->info.array_size;
988
989 switch (mode) {
990 case RADEON_SURF_MODE_LINEAR_ALIGNED:
991 assert(config->info.samples <= 1);
992 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
993 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
994 break;
995
996 case RADEON_SURF_MODE_1D:
997 case RADEON_SURF_MODE_2D:
998 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
999 &AddrSurfInfoIn.swizzleMode);
1000 if (r)
1001 return r;
1002 break;
1003
1004 default:
1005 assert(0);
1006 }
1007
1008 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1009
1010 surf->surf_size = 0;
1011 surf->dcc_size = 0;
1012 surf->htile_size = 0;
1013 surf->htile_slice_size = 0;
1014 surf->u.gfx9.surf_offset = 0;
1015 surf->u.gfx9.stencil_offset = 0;
1016 surf->u.gfx9.fmask_size = 0;
1017 surf->u.gfx9.cmask_size = 0;
1018
1019 /* Calculate texture layout information. */
1020 r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1021 if (r)
1022 return r;
1023
1024 /* Calculate texture layout information for stencil. */
1025 if (surf->flags & RADEON_SURF_SBUFFER) {
1026 AddrSurfInfoIn.bpp = 8;
1027 AddrSurfInfoIn.flags.depth = 0;
1028 AddrSurfInfoIn.flags.stencil = 1;
1029
1030 r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1031 if (r)
1032 return r;
1033 }
1034
1035 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1036 surf->num_dcc_levels = surf->dcc_size ? config->info.levels : 0;
1037
1038 switch (surf->u.gfx9.surf.swizzle_mode) {
1039 /* S = standard. */
1040 case ADDR_SW_256B_S:
1041 case ADDR_SW_4KB_S:
1042 case ADDR_SW_64KB_S:
1043 case ADDR_SW_VAR_S:
1044 case ADDR_SW_64KB_S_T:
1045 case ADDR_SW_4KB_S_X:
1046 case ADDR_SW_64KB_S_X:
1047 case ADDR_SW_VAR_S_X:
1048 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1049 break;
1050
1051 /* D = display. */
1052 case ADDR_SW_LINEAR:
1053 case ADDR_SW_256B_D:
1054 case ADDR_SW_4KB_D:
1055 case ADDR_SW_64KB_D:
1056 case ADDR_SW_VAR_D:
1057 case ADDR_SW_64KB_D_T:
1058 case ADDR_SW_4KB_D_X:
1059 case ADDR_SW_64KB_D_X:
1060 case ADDR_SW_VAR_D_X:
1061 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1062 break;
1063
1064 /* R = rotated. */
1065 case ADDR_SW_256B_R:
1066 case ADDR_SW_4KB_R:
1067 case ADDR_SW_64KB_R:
1068 case ADDR_SW_VAR_R:
1069 case ADDR_SW_64KB_R_T:
1070 case ADDR_SW_4KB_R_X:
1071 case ADDR_SW_64KB_R_X:
1072 case ADDR_SW_VAR_R_X:
1073 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1074 break;
1075
1076 /* Z = depth. */
1077 case ADDR_SW_4KB_Z:
1078 case ADDR_SW_64KB_Z:
1079 case ADDR_SW_VAR_Z:
1080 case ADDR_SW_64KB_Z_T:
1081 case ADDR_SW_4KB_Z_X:
1082 case ADDR_SW_64KB_Z_X:
1083 case ADDR_SW_VAR_Z_X:
1084 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1085 break;
1086
1087 default:
1088 assert(0);
1089 }
1090
1091 return 0;
1092 }
1093
1094 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1095 const struct ac_surf_config *config,
1096 enum radeon_surf_mode mode,
1097 struct radeon_surf *surf)
1098 {
1099 int r;
1100
1101 r = surf_config_sanity(config);
1102 if (r)
1103 return r;
1104
1105 if (info->chip_class >= GFX9)
1106 return gfx9_compute_surface(addrlib, config, mode, surf);
1107 else
1108 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1109 }