ac/radeonsi: move amdgpu_addr_create to ac_surface
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amdgpu_id.h"
30 #include "util/macros.h"
31 #include "util/u_math.h"
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <amdgpu.h>
36
37 #include "addrlib/addrinterface.h"
38
39 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
40 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
41 #endif
42
43 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
44 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
45 #endif
46
47 static void addrlib_family_rev_id(enum radeon_family family,
48 unsigned *addrlib_family,
49 unsigned *addrlib_revid)
50 {
51 switch (family) {
52 case CHIP_TAHITI:
53 *addrlib_family = FAMILY_SI;
54 *addrlib_revid = SI_TAHITI_P_A0;
55 break;
56 case CHIP_PITCAIRN:
57 *addrlib_family = FAMILY_SI;
58 *addrlib_revid = SI_PITCAIRN_PM_A0;
59 break;
60 case CHIP_VERDE:
61 *addrlib_family = FAMILY_SI;
62 *addrlib_revid = SI_CAPEVERDE_M_A0;
63 break;
64 case CHIP_OLAND:
65 *addrlib_family = FAMILY_SI;
66 *addrlib_revid = SI_OLAND_M_A0;
67 break;
68 case CHIP_HAINAN:
69 *addrlib_family = FAMILY_SI;
70 *addrlib_revid = SI_HAINAN_V_A0;
71 break;
72 case CHIP_BONAIRE:
73 *addrlib_family = FAMILY_CI;
74 *addrlib_revid = CI_BONAIRE_M_A0;
75 break;
76 case CHIP_KAVERI:
77 *addrlib_family = FAMILY_KV;
78 *addrlib_revid = KV_SPECTRE_A0;
79 break;
80 case CHIP_KABINI:
81 *addrlib_family = FAMILY_KV;
82 *addrlib_revid = KB_KALINDI_A0;
83 break;
84 case CHIP_HAWAII:
85 *addrlib_family = FAMILY_CI;
86 *addrlib_revid = CI_HAWAII_P_A0;
87 break;
88 case CHIP_MULLINS:
89 *addrlib_family = FAMILY_KV;
90 *addrlib_revid = ML_GODAVARI_A0;
91 break;
92 case CHIP_TONGA:
93 *addrlib_family = FAMILY_VI;
94 *addrlib_revid = VI_TONGA_P_A0;
95 break;
96 case CHIP_ICELAND:
97 *addrlib_family = FAMILY_VI;
98 *addrlib_revid = VI_ICELAND_M_A0;
99 break;
100 case CHIP_CARRIZO:
101 *addrlib_family = FAMILY_CZ;
102 *addrlib_revid = CARRIZO_A0;
103 break;
104 case CHIP_STONEY:
105 *addrlib_family = FAMILY_CZ;
106 *addrlib_revid = STONEY_A0;
107 break;
108 case CHIP_FIJI:
109 *addrlib_family = FAMILY_VI;
110 *addrlib_revid = VI_FIJI_P_A0;
111 break;
112 case CHIP_POLARIS10:
113 *addrlib_family = FAMILY_VI;
114 *addrlib_revid = VI_POLARIS10_P_A0;
115 break;
116 case CHIP_POLARIS11:
117 *addrlib_family = FAMILY_VI;
118 *addrlib_revid = VI_POLARIS11_M_A0;
119 break;
120 case CHIP_POLARIS12:
121 *addrlib_family = FAMILY_VI;
122 *addrlib_revid = VI_POLARIS12_V_A0;
123 break;
124 case CHIP_VEGA10:
125 *addrlib_family = FAMILY_AI;
126 *addrlib_revid = AI_VEGA10_P_A0;
127 break;
128 case CHIP_RAVEN:
129 *addrlib_family = FAMILY_RV;
130 *addrlib_revid = RAVEN_A0;
131 break;
132 default:
133 fprintf(stderr, "amdgpu: Unknown family.\n");
134 }
135 }
136
137 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
138 {
139 return malloc(pInput->sizeInBytes);
140 }
141
142 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
143 {
144 free(pInput->pVirtAddr);
145 return ADDR_OK;
146 }
147
148 ADDR_HANDLE amdgpu_addr_create(enum radeon_family family,
149 const struct amdgpu_gpu_info *info)
150 {
151 ADDR_CREATE_INPUT addrCreateInput = {0};
152 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
153 ADDR_REGISTER_VALUE regValue = {0};
154 ADDR_CREATE_FLAGS createFlags = {{0}};
155 ADDR_E_RETURNCODE addrRet;
156
157 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
158 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
159
160 regValue.gbAddrConfig = info->gb_addr_cfg;
161 createFlags.value = 0;
162
163 addrlib_family_rev_id(family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
164 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
165 return NULL;
166
167 if (addrCreateInput.chipFamily >= FAMILY_AI) {
168 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
169 regValue.blockVarSizeLog2 = 0;
170 } else {
171 regValue.noOfBanks = info->mc_arb_ramcfg & 0x3;
172 regValue.noOfRanks = (info->mc_arb_ramcfg & 0x4) >> 2;
173
174 regValue.backendDisables = info->enabled_rb_pipes_mask;
175 regValue.pTileConfig = info->gb_tile_mode;
176 regValue.noOfEntries = ARRAY_SIZE(info->gb_tile_mode);
177 if (addrCreateInput.chipFamily == FAMILY_SI) {
178 regValue.pMacroTileConfig = NULL;
179 regValue.noOfMacroEntries = 0;
180 } else {
181 regValue.pMacroTileConfig = info->gb_macro_tile_mode;
182 regValue.noOfMacroEntries = ARRAY_SIZE(info->gb_macro_tile_mode);
183 }
184
185 createFlags.useTileIndex = 1;
186 createFlags.useHtileSliceAlign = 1;
187
188 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
189 }
190
191 addrCreateInput.callbacks.allocSysMem = allocSysMem;
192 addrCreateInput.callbacks.freeSysMem = freeSysMem;
193 addrCreateInput.callbacks.debugPrint = 0;
194 addrCreateInput.createFlags = createFlags;
195 addrCreateInput.regValue = regValue;
196
197 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
198 if (addrRet != ADDR_OK)
199 return NULL;
200
201 return addrCreateOutput.hLib;
202 }