2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amdgpu_id.h"
30 #include "util/macros.h"
31 #include "util/u_math.h"
37 #include "addrlib/addrinterface.h"
39 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
40 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
43 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
44 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
47 static void addrlib_family_rev_id(enum radeon_family family
,
48 unsigned *addrlib_family
,
49 unsigned *addrlib_revid
)
53 *addrlib_family
= FAMILY_SI
;
54 *addrlib_revid
= SI_TAHITI_P_A0
;
57 *addrlib_family
= FAMILY_SI
;
58 *addrlib_revid
= SI_PITCAIRN_PM_A0
;
61 *addrlib_family
= FAMILY_SI
;
62 *addrlib_revid
= SI_CAPEVERDE_M_A0
;
65 *addrlib_family
= FAMILY_SI
;
66 *addrlib_revid
= SI_OLAND_M_A0
;
69 *addrlib_family
= FAMILY_SI
;
70 *addrlib_revid
= SI_HAINAN_V_A0
;
73 *addrlib_family
= FAMILY_CI
;
74 *addrlib_revid
= CI_BONAIRE_M_A0
;
77 *addrlib_family
= FAMILY_KV
;
78 *addrlib_revid
= KV_SPECTRE_A0
;
81 *addrlib_family
= FAMILY_KV
;
82 *addrlib_revid
= KB_KALINDI_A0
;
85 *addrlib_family
= FAMILY_CI
;
86 *addrlib_revid
= CI_HAWAII_P_A0
;
89 *addrlib_family
= FAMILY_KV
;
90 *addrlib_revid
= ML_GODAVARI_A0
;
93 *addrlib_family
= FAMILY_VI
;
94 *addrlib_revid
= VI_TONGA_P_A0
;
97 *addrlib_family
= FAMILY_VI
;
98 *addrlib_revid
= VI_ICELAND_M_A0
;
101 *addrlib_family
= FAMILY_CZ
;
102 *addrlib_revid
= CARRIZO_A0
;
105 *addrlib_family
= FAMILY_CZ
;
106 *addrlib_revid
= STONEY_A0
;
109 *addrlib_family
= FAMILY_VI
;
110 *addrlib_revid
= VI_FIJI_P_A0
;
113 *addrlib_family
= FAMILY_VI
;
114 *addrlib_revid
= VI_POLARIS10_P_A0
;
117 *addrlib_family
= FAMILY_VI
;
118 *addrlib_revid
= VI_POLARIS11_M_A0
;
121 *addrlib_family
= FAMILY_VI
;
122 *addrlib_revid
= VI_POLARIS12_V_A0
;
125 *addrlib_family
= FAMILY_AI
;
126 *addrlib_revid
= AI_VEGA10_P_A0
;
129 *addrlib_family
= FAMILY_RV
;
130 *addrlib_revid
= RAVEN_A0
;
133 fprintf(stderr
, "amdgpu: Unknown family.\n");
137 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
139 return malloc(pInput
->sizeInBytes
);
142 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
144 free(pInput
->pVirtAddr
);
148 ADDR_HANDLE
amdgpu_addr_create(enum radeon_family family
,
149 const struct amdgpu_gpu_info
*info
)
151 ADDR_CREATE_INPUT addrCreateInput
= {0};
152 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
153 ADDR_REGISTER_VALUE regValue
= {0};
154 ADDR_CREATE_FLAGS createFlags
= {{0}};
155 ADDR_E_RETURNCODE addrRet
;
157 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
158 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
160 regValue
.gbAddrConfig
= info
->gb_addr_cfg
;
161 createFlags
.value
= 0;
163 addrlib_family_rev_id(family
, &addrCreateInput
.chipFamily
, &addrCreateInput
.chipRevision
);
164 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
167 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
168 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
169 regValue
.blockVarSizeLog2
= 0;
171 regValue
.noOfBanks
= info
->mc_arb_ramcfg
& 0x3;
172 regValue
.noOfRanks
= (info
->mc_arb_ramcfg
& 0x4) >> 2;
174 regValue
.backendDisables
= info
->enabled_rb_pipes_mask
;
175 regValue
.pTileConfig
= info
->gb_tile_mode
;
176 regValue
.noOfEntries
= ARRAY_SIZE(info
->gb_tile_mode
);
177 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
178 regValue
.pMacroTileConfig
= NULL
;
179 regValue
.noOfMacroEntries
= 0;
181 regValue
.pMacroTileConfig
= info
->gb_macro_tile_mode
;
182 regValue
.noOfMacroEntries
= ARRAY_SIZE(info
->gb_macro_tile_mode
);
185 createFlags
.useTileIndex
= 1;
186 createFlags
.useHtileSliceAlign
= 1;
188 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
191 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
192 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
193 addrCreateInput
.callbacks
.debugPrint
= 0;
194 addrCreateInput
.createFlags
= createFlags
;
195 addrCreateInput
.regValue
= regValue
;
197 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
198 if (addrRet
!= ADDR_OK
)
201 return addrCreateOutput
.hLib
;