2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
40 #include <amdgpu_drm.h>
42 #include "addrlib/inc/addrinterface.h"
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
52 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
54 return malloc(pInput
->sizeInBytes
);
57 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
59 free(pInput
->pVirtAddr
);
63 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
64 const struct amdgpu_gpu_info
*amdinfo
,
65 uint64_t *max_alignment
)
67 ADDR_CREATE_INPUT addrCreateInput
= {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
69 ADDR_REGISTER_VALUE regValue
= {0};
70 ADDR_CREATE_FLAGS createFlags
= {{0}};
71 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput
= {0};
72 ADDR_E_RETURNCODE addrRet
;
74 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
75 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
77 regValue
.gbAddrConfig
= amdinfo
->gb_addr_cfg
;
78 createFlags
.value
= 0;
80 addrCreateInput
.chipFamily
= info
->family_id
;
81 addrCreateInput
.chipRevision
= info
->chip_external_rev
;
83 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
86 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
87 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
88 regValue
.blockVarSizeLog2
= 0;
90 regValue
.noOfBanks
= amdinfo
->mc_arb_ramcfg
& 0x3;
91 regValue
.noOfRanks
= (amdinfo
->mc_arb_ramcfg
& 0x4) >> 2;
93 regValue
.backendDisables
= amdinfo
->enabled_rb_pipes_mask
;
94 regValue
.pTileConfig
= amdinfo
->gb_tile_mode
;
95 regValue
.noOfEntries
= ARRAY_SIZE(amdinfo
->gb_tile_mode
);
96 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
97 regValue
.pMacroTileConfig
= NULL
;
98 regValue
.noOfMacroEntries
= 0;
100 regValue
.pMacroTileConfig
= amdinfo
->gb_macro_tile_mode
;
101 regValue
.noOfMacroEntries
= ARRAY_SIZE(amdinfo
->gb_macro_tile_mode
);
104 createFlags
.useTileIndex
= 1;
105 createFlags
.useHtileSliceAlign
= 1;
107 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
110 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
111 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
112 addrCreateInput
.callbacks
.debugPrint
= 0;
113 addrCreateInput
.createFlags
= createFlags
;
114 addrCreateInput
.regValue
= regValue
;
116 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
117 if (addrRet
!= ADDR_OK
)
121 addrRet
= AddrGetMaxAlignments(addrCreateOutput
.hLib
, &addrGetMaxAlignmentsOutput
);
122 if (addrRet
== ADDR_OK
){
123 *max_alignment
= addrGetMaxAlignmentsOutput
.baseAlign
;
126 return addrCreateOutput
.hLib
;
129 static int surf_config_sanity(const struct ac_surf_config
*config
,
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
135 assert(!(flags
& RADEON_SURF_FMASK
));
136 if (flags
& RADEON_SURF_FMASK
)
139 /* all dimension must be at least 1 ! */
140 if (!config
->info
.width
|| !config
->info
.height
|| !config
->info
.depth
||
141 !config
->info
.array_size
|| !config
->info
.levels
)
144 switch (config
->info
.samples
) {
152 if (flags
& RADEON_SURF_Z_OR_SBUFFER
)
159 if (!(flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
160 switch (config
->info
.storage_samples
) {
172 if (config
->is_3d
&& config
->info
.array_size
> 1)
174 if (config
->is_cube
&& config
->info
.depth
> 1)
180 static int gfx6_compute_level(ADDR_HANDLE addrlib
,
181 const struct ac_surf_config
*config
,
182 struct radeon_surf
*surf
, bool is_stencil
,
183 unsigned level
, bool compressed
,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT
*AddrSurfInfoIn
,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut
,
186 ADDR_COMPUTE_DCCINFO_INPUT
*AddrDccIn
,
187 ADDR_COMPUTE_DCCINFO_OUTPUT
*AddrDccOut
,
188 ADDR_COMPUTE_HTILE_INFO_INPUT
*AddrHtileIn
,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT
*AddrHtileOut
)
191 struct legacy_surf_level
*surf_level
;
192 ADDR_E_RETURNCODE ret
;
194 AddrSurfInfoIn
->mipLevel
= level
;
195 AddrSurfInfoIn
->width
= u_minify(config
->info
.width
, level
);
196 AddrSurfInfoIn
->height
= u_minify(config
->info
.height
, level
);
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
201 if (config
->info
.levels
== 1 &&
202 AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
&&
203 AddrSurfInfoIn
->bpp
&&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn
->bpp
)) {
205 unsigned alignment
= 256 / (AddrSurfInfoIn
->bpp
/ 8);
207 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, alignment
);
211 AddrSurfInfoIn
->numSlices
= u_minify(config
->info
.depth
, level
);
212 else if (config
->is_cube
)
213 AddrSurfInfoIn
->numSlices
= 6;
215 AddrSurfInfoIn
->numSlices
= config
->info
.array_size
;
218 /* Set the base level pitch. This is needed for calculation
219 * of non-zero levels. */
221 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.stencil_level
[0].nblk_x
;
223 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.level
[0].nblk_x
;
225 /* Convert blocks to pixels for compressed formats. */
227 AddrSurfInfoIn
->basePitch
*= surf
->blk_w
;
230 ret
= AddrComputeSurfaceInfo(addrlib
,
233 if (ret
!= ADDR_OK
) {
237 surf_level
= is_stencil
? &surf
->u
.legacy
.stencil_level
[level
] : &surf
->u
.legacy
.level
[level
];
238 surf_level
->offset
= align64(surf
->surf_size
, AddrSurfInfoOut
->baseAlign
);
239 surf_level
->slice_size_dw
= AddrSurfInfoOut
->sliceSize
/ 4;
240 surf_level
->nblk_x
= AddrSurfInfoOut
->pitch
;
241 surf_level
->nblk_y
= AddrSurfInfoOut
->height
;
243 switch (AddrSurfInfoOut
->tileMode
) {
244 case ADDR_TM_LINEAR_ALIGNED
:
245 surf_level
->mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
247 case ADDR_TM_1D_TILED_THIN1
:
248 surf_level
->mode
= RADEON_SURF_MODE_1D
;
250 case ADDR_TM_2D_TILED_THIN1
:
251 surf_level
->mode
= RADEON_SURF_MODE_2D
;
258 surf
->u
.legacy
.stencil_tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
260 surf
->u
.legacy
.tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
262 surf
->surf_size
= surf_level
->offset
+ AddrSurfInfoOut
->surfSize
;
264 /* Clear DCC fields at the beginning. */
265 surf_level
->dcc_offset
= 0;
267 /* The previous level's flag tells us if we can use DCC for this level. */
268 if (AddrSurfInfoIn
->flags
.dccCompatible
&&
269 (level
== 0 || AddrDccOut
->subLvlCompressible
)) {
270 bool prev_level_clearable
= level
== 0 ||
271 AddrDccOut
->dccRamSizeAligned
;
273 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->surfSize
;
274 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
275 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
276 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
277 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
279 ret
= AddrComputeDccInfo(addrlib
,
283 if (ret
== ADDR_OK
) {
284 surf_level
->dcc_offset
= surf
->dcc_size
;
285 surf
->num_dcc_levels
= level
+ 1;
286 surf
->dcc_size
= surf_level
->dcc_offset
+ AddrDccOut
->dccRamSize
;
287 surf
->dcc_alignment
= MAX2(surf
->dcc_alignment
, AddrDccOut
->dccRamBaseAlign
);
289 /* If the DCC size of a subresource (1 mip level or 1 slice)
290 * is not aligned, the DCC memory layout is not contiguous for
291 * that subresource, which means we can't use fast clear.
293 * We only do fast clears for whole mipmap levels. If we did
294 * per-slice fast clears, the same restriction would apply.
295 * (i.e. only compute the slice size and see if it's aligned)
297 * The last level can be non-contiguous and still be clearable
298 * if it's interleaved with the next level that doesn't exist.
300 if (AddrDccOut
->dccRamSizeAligned
||
301 (prev_level_clearable
&& level
== config
->info
.levels
- 1))
302 surf_level
->dcc_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
304 surf_level
->dcc_fast_clear_size
= 0;
308 /* TC-compatible HTILE. */
310 AddrSurfInfoIn
->flags
.depth
&&
311 surf_level
->mode
== RADEON_SURF_MODE_2D
&&
313 AddrHtileIn
->flags
.tcCompatible
= AddrSurfInfoIn
->flags
.tcCompatible
;
314 AddrHtileIn
->pitch
= AddrSurfInfoOut
->pitch
;
315 AddrHtileIn
->height
= AddrSurfInfoOut
->height
;
316 AddrHtileIn
->numSlices
= AddrSurfInfoOut
->depth
;
317 AddrHtileIn
->blockWidth
= ADDR_HTILE_BLOCKSIZE_8
;
318 AddrHtileIn
->blockHeight
= ADDR_HTILE_BLOCKSIZE_8
;
319 AddrHtileIn
->pTileInfo
= AddrSurfInfoOut
->pTileInfo
;
320 AddrHtileIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
321 AddrHtileIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
323 ret
= AddrComputeHtileInfo(addrlib
,
327 if (ret
== ADDR_OK
) {
328 surf
->htile_size
= AddrHtileOut
->htileBytes
;
329 surf
->htile_slice_size
= AddrHtileOut
->sliceSize
;
330 surf
->htile_alignment
= AddrHtileOut
->baseAlign
;
337 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
338 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
339 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
341 static void gfx6_set_micro_tile_mode(struct radeon_surf
*surf
,
342 const struct radeon_info
*info
)
344 uint32_t tile_mode
= info
->si_tile_mode_array
[surf
->u
.legacy
.tiling_index
[0]];
346 if (info
->chip_class
>= GFX7
)
347 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE_NEW(tile_mode
);
349 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE(tile_mode
);
352 static unsigned cik_get_macro_tile_index(struct radeon_surf
*surf
)
354 unsigned index
, tileb
;
356 tileb
= 8 * 8 * surf
->bpe
;
357 tileb
= MIN2(surf
->u
.legacy
.tile_split
, tileb
);
359 for (index
= 0; tileb
> 64; index
++)
366 static bool get_display_flag(const struct ac_surf_config
*config
,
367 const struct radeon_surf
*surf
)
369 unsigned num_channels
= config
->info
.num_channels
;
370 unsigned bpe
= surf
->bpe
;
372 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
373 surf
->flags
& RADEON_SURF_SCANOUT
&&
374 config
->info
.samples
<= 1 &&
375 surf
->blk_w
<= 2 && surf
->blk_h
== 1) {
377 if (surf
->blk_w
== 2 && surf
->blk_h
== 1)
380 if (/* RGBA8 or RGBA16F */
381 (bpe
>= 4 && bpe
<= 8 && num_channels
== 4) ||
382 /* R5G6B5 or R5G5B5A1 */
383 (bpe
== 2 && num_channels
>= 3) ||
385 (bpe
== 1 && num_channels
== 1))
392 * This must be called after the first level is computed.
394 * Copy surface-global settings like pipe/bank config from level 0 surface
395 * computation, and compute tile swizzle.
397 static int gfx6_surface_settings(ADDR_HANDLE addrlib
,
398 const struct radeon_info
*info
,
399 const struct ac_surf_config
*config
,
400 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* csio
,
401 struct radeon_surf
*surf
)
403 surf
->surf_alignment
= csio
->baseAlign
;
404 surf
->u
.legacy
.pipe_config
= csio
->pTileInfo
->pipeConfig
- 1;
405 gfx6_set_micro_tile_mode(surf
, info
);
407 /* For 2D modes only. */
408 if (csio
->tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
409 surf
->u
.legacy
.bankw
= csio
->pTileInfo
->bankWidth
;
410 surf
->u
.legacy
.bankh
= csio
->pTileInfo
->bankHeight
;
411 surf
->u
.legacy
.mtilea
= csio
->pTileInfo
->macroAspectRatio
;
412 surf
->u
.legacy
.tile_split
= csio
->pTileInfo
->tileSplitBytes
;
413 surf
->u
.legacy
.num_banks
= csio
->pTileInfo
->banks
;
414 surf
->u
.legacy
.macro_tile_index
= csio
->macroModeIndex
;
416 surf
->u
.legacy
.macro_tile_index
= 0;
419 /* Compute tile swizzle. */
420 /* TODO: fix tile swizzle with mipmapping for GFX6 */
421 if ((info
->chip_class
>= GFX7
|| config
->info
.levels
== 1) &&
422 config
->info
.surf_index
&&
423 surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
&&
424 !(surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_SHAREABLE
)) &&
425 !get_display_flag(config
, surf
)) {
426 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn
= {0};
427 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut
= {0};
429 AddrBaseSwizzleIn
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
430 AddrBaseSwizzleOut
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
432 AddrBaseSwizzleIn
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
433 AddrBaseSwizzleIn
.tileIndex
= csio
->tileIndex
;
434 AddrBaseSwizzleIn
.macroModeIndex
= csio
->macroModeIndex
;
435 AddrBaseSwizzleIn
.pTileInfo
= csio
->pTileInfo
;
436 AddrBaseSwizzleIn
.tileMode
= csio
->tileMode
;
438 int r
= AddrComputeBaseSwizzle(addrlib
, &AddrBaseSwizzleIn
,
439 &AddrBaseSwizzleOut
);
443 assert(AddrBaseSwizzleOut
.tileSwizzle
<=
444 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
445 surf
->tile_swizzle
= AddrBaseSwizzleOut
.tileSwizzle
;
450 static void ac_compute_cmask(const struct radeon_info
*info
,
451 const struct ac_surf_config
*config
,
452 struct radeon_surf
*surf
)
454 unsigned pipe_interleave_bytes
= info
->pipe_interleave_bytes
;
455 unsigned num_pipes
= info
->num_tile_pipes
;
456 unsigned cl_width
, cl_height
;
458 if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)
461 assert(info
->chip_class
<= GFX8
);
476 case 16: /* Hawaii */
485 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
487 unsigned width
= align(surf
->u
.legacy
.level
[0].nblk_x
, cl_width
*8);
488 unsigned height
= align(surf
->u
.legacy
.level
[0].nblk_y
, cl_height
*8);
489 unsigned slice_elements
= (width
* height
) / (8*8);
491 /* Each element of CMASK is a nibble. */
492 unsigned slice_bytes
= slice_elements
/ 2;
494 surf
->u
.legacy
.cmask_slice_tile_max
= (width
* height
) / (128*128);
495 if (surf
->u
.legacy
.cmask_slice_tile_max
)
496 surf
->u
.legacy
.cmask_slice_tile_max
-= 1;
500 num_layers
= config
->info
.depth
;
501 else if (config
->is_cube
)
504 num_layers
= config
->info
.array_size
;
506 surf
->cmask_alignment
= MAX2(256, base_align
);
507 surf
->cmask_size
= align(slice_bytes
, base_align
) * num_layers
;
511 * Fill in the tiling information in \p surf based on the given surface config.
513 * The following fields of \p surf must be initialized by the caller:
514 * blk_w, blk_h, bpe, flags.
516 static int gfx6_compute_surface(ADDR_HANDLE addrlib
,
517 const struct radeon_info
*info
,
518 const struct ac_surf_config
*config
,
519 enum radeon_surf_mode mode
,
520 struct radeon_surf
*surf
)
524 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
525 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut
= {0};
526 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn
= {0};
527 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut
= {0};
528 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn
= {0};
529 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut
= {0};
530 ADDR_TILEINFO AddrTileInfoIn
= {0};
531 ADDR_TILEINFO AddrTileInfoOut
= {0};
534 AddrSurfInfoIn
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT
);
535 AddrSurfInfoOut
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT
);
536 AddrDccIn
.size
= sizeof(ADDR_COMPUTE_DCCINFO_INPUT
);
537 AddrDccOut
.size
= sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT
);
538 AddrHtileIn
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT
);
539 AddrHtileOut
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT
);
540 AddrSurfInfoOut
.pTileInfo
= &AddrTileInfoOut
;
542 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
544 /* MSAA requires 2D tiling. */
545 if (config
->info
.samples
> 1)
546 mode
= RADEON_SURF_MODE_2D
;
548 /* DB doesn't support linear layouts. */
549 if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
) &&
550 mode
< RADEON_SURF_MODE_1D
)
551 mode
= RADEON_SURF_MODE_1D
;
553 /* Set the requested tiling mode. */
555 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
556 AddrSurfInfoIn
.tileMode
= ADDR_TM_LINEAR_ALIGNED
;
558 case RADEON_SURF_MODE_1D
:
559 AddrSurfInfoIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
561 case RADEON_SURF_MODE_2D
:
562 AddrSurfInfoIn
.tileMode
= ADDR_TM_2D_TILED_THIN1
;
568 /* The format must be set correctly for the allocation of compressed
569 * textures to work. In other cases, setting the bpp is sufficient.
574 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
577 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
584 AddrDccIn
.bpp
= AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
587 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numSamples
=
588 MAX2(1, config
->info
.samples
);
589 AddrSurfInfoIn
.tileIndex
= -1;
591 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
592 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numFrags
=
593 MAX2(1, config
->info
.storage_samples
);
596 /* Set the micro tile type. */
597 if (surf
->flags
& RADEON_SURF_SCANOUT
)
598 AddrSurfInfoIn
.tileType
= ADDR_DISPLAYABLE
;
599 else if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)
600 AddrSurfInfoIn
.tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
602 AddrSurfInfoIn
.tileType
= ADDR_NON_DISPLAYABLE
;
604 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
605 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
606 AddrSurfInfoIn
.flags
.cube
= config
->is_cube
;
607 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
608 AddrSurfInfoIn
.flags
.pow2Pad
= config
->info
.levels
> 1;
609 AddrSurfInfoIn
.flags
.tcCompatible
= (surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) != 0;
611 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
612 * requested, because TC-compatible HTILE requires 2D tiling.
614 AddrSurfInfoIn
.flags
.opt4Space
= !AddrSurfInfoIn
.flags
.tcCompatible
&&
615 !AddrSurfInfoIn
.flags
.fmask
&&
616 config
->info
.samples
<= 1 &&
617 (surf
->flags
& RADEON_SURF_OPTIMIZE_FOR_SPACE
);
620 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
622 * - Mipmapped array textures have low performance (discovered by a closed
625 AddrSurfInfoIn
.flags
.dccCompatible
=
626 info
->chip_class
>= GFX8
&&
627 !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
628 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
630 ((config
->info
.array_size
== 1 && config
->info
.depth
== 1) ||
631 config
->info
.levels
== 1);
633 AddrSurfInfoIn
.flags
.noStencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) == 0;
634 AddrSurfInfoIn
.flags
.compressZ
= !!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
636 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
637 * for Z and stencil. This can cause a number of problems which we work
640 * - a depth part that is incompatible with mipmapped texturing
641 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
642 * incorrect tiling applied to the stencil part, stencil buffer
643 * memory accesses that go out of bounds) even without mipmapping
645 * Some piglit tests that are prone to different types of related
647 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
648 * ./bin/framebuffer-blit-levels {draw,read} stencil
649 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
650 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
651 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
653 int stencil_tile_idx
= -1;
655 if (AddrSurfInfoIn
.flags
.depth
&& !AddrSurfInfoIn
.flags
.noStencil
&&
656 (config
->info
.levels
> 1 || info
->family
== CHIP_STONEY
)) {
657 /* Compute stencilTileIdx that is compatible with the (depth)
658 * tileIdx. This degrades the depth surface if necessary to
659 * ensure that a matching stencilTileIdx exists. */
660 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 1;
662 /* Keep the depth mip-tail compatible with texturing. */
663 AddrSurfInfoIn
.flags
.noStencil
= 1;
666 /* Set preferred macrotile parameters. This is usually required
667 * for shared resources. This is for 2D tiling only. */
668 if (AddrSurfInfoIn
.tileMode
>= ADDR_TM_2D_TILED_THIN1
&&
669 surf
->u
.legacy
.bankw
&& surf
->u
.legacy
.bankh
&&
670 surf
->u
.legacy
.mtilea
&& surf
->u
.legacy
.tile_split
) {
671 /* If any of these parameters are incorrect, the calculation
673 AddrTileInfoIn
.banks
= surf
->u
.legacy
.num_banks
;
674 AddrTileInfoIn
.bankWidth
= surf
->u
.legacy
.bankw
;
675 AddrTileInfoIn
.bankHeight
= surf
->u
.legacy
.bankh
;
676 AddrTileInfoIn
.macroAspectRatio
= surf
->u
.legacy
.mtilea
;
677 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.tile_split
;
678 AddrTileInfoIn
.pipeConfig
= surf
->u
.legacy
.pipe_config
+ 1; /* +1 compared to GB_TILE_MODE */
679 AddrSurfInfoIn
.flags
.opt4Space
= 0;
680 AddrSurfInfoIn
.pTileInfo
= &AddrTileInfoIn
;
682 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
683 * the tile index, because we are expected to know it if
684 * we know the other parameters.
686 * This is something that can easily be fixed in Addrlib.
687 * For now, just figure it out here.
688 * Note that only 2D_TILE_THIN1 is handled here.
690 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
691 assert(AddrSurfInfoIn
.tileMode
== ADDR_TM_2D_TILED_THIN1
);
693 if (info
->chip_class
== GFX6
) {
694 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
) {
696 AddrSurfInfoIn
.tileIndex
= 11; /* 16bpp */
698 AddrSurfInfoIn
.tileIndex
= 12; /* 32bpp */
701 AddrSurfInfoIn
.tileIndex
= 14; /* 8bpp */
702 else if (surf
->bpe
== 2)
703 AddrSurfInfoIn
.tileIndex
= 15; /* 16bpp */
704 else if (surf
->bpe
== 4)
705 AddrSurfInfoIn
.tileIndex
= 16; /* 32bpp */
707 AddrSurfInfoIn
.tileIndex
= 17; /* 64bpp (and 128bpp) */
711 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
)
712 AddrSurfInfoIn
.tileIndex
= 10; /* 2D displayable */
714 AddrSurfInfoIn
.tileIndex
= 14; /* 2D non-displayable */
716 /* Addrlib doesn't set this if tileIndex is forced like above. */
717 AddrSurfInfoOut
.macroModeIndex
= cik_get_macro_tile_index(surf
);
721 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
722 surf
->num_dcc_levels
= 0;
725 surf
->dcc_alignment
= 1;
726 surf
->htile_size
= 0;
727 surf
->htile_slice_size
= 0;
728 surf
->htile_alignment
= 1;
730 const bool only_stencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) &&
731 !(surf
->flags
& RADEON_SURF_ZBUFFER
);
733 /* Calculate texture layout information. */
735 for (level
= 0; level
< config
->info
.levels
; level
++) {
736 r
= gfx6_compute_level(addrlib
, config
, surf
, false, level
, compressed
,
737 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
738 &AddrDccIn
, &AddrDccOut
, &AddrHtileIn
, &AddrHtileOut
);
745 /* Check that we actually got a TC-compatible HTILE if
746 * we requested it (only for level 0, since we're not
747 * supporting HTILE on higher mip levels anyway). */
748 assert(AddrSurfInfoOut
.tcCompatible
||
749 !AddrSurfInfoIn
.flags
.tcCompatible
||
750 AddrSurfInfoIn
.flags
.matchStencilTileCfg
);
752 if (AddrSurfInfoIn
.flags
.matchStencilTileCfg
) {
753 if (!AddrSurfInfoOut
.tcCompatible
) {
754 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
755 surf
->flags
&= ~RADEON_SURF_TC_COMPATIBLE_HTILE
;
758 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 0;
759 AddrSurfInfoIn
.tileIndex
= AddrSurfInfoOut
.tileIndex
;
760 stencil_tile_idx
= AddrSurfInfoOut
.stencilTileIdx
;
762 assert(stencil_tile_idx
>= 0);
765 r
= gfx6_surface_settings(addrlib
, info
, config
,
766 &AddrSurfInfoOut
, surf
);
772 /* Calculate texture layout information for stencil. */
773 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
774 AddrSurfInfoIn
.tileIndex
= stencil_tile_idx
;
775 AddrSurfInfoIn
.bpp
= 8;
776 AddrSurfInfoIn
.flags
.depth
= 0;
777 AddrSurfInfoIn
.flags
.stencil
= 1;
778 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
779 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
780 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.stencil_tile_split
;
782 for (level
= 0; level
< config
->info
.levels
; level
++) {
783 r
= gfx6_compute_level(addrlib
, config
, surf
, true, level
, compressed
,
784 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
785 &AddrDccIn
, &AddrDccOut
,
790 /* DB uses the depth pitch for both stencil and depth. */
792 if (surf
->u
.legacy
.stencil_level
[level
].nblk_x
!=
793 surf
->u
.legacy
.level
[level
].nblk_x
)
794 surf
->u
.legacy
.stencil_adjusted
= true;
796 surf
->u
.legacy
.level
[level
].nblk_x
=
797 surf
->u
.legacy
.stencil_level
[level
].nblk_x
;
802 r
= gfx6_surface_settings(addrlib
, info
, config
,
803 &AddrSurfInfoOut
, surf
);
808 /* For 2D modes only. */
809 if (AddrSurfInfoOut
.tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
810 surf
->u
.legacy
.stencil_tile_split
=
811 AddrSurfInfoOut
.pTileInfo
->tileSplitBytes
;
818 if (config
->info
.samples
>= 2 && AddrSurfInfoIn
.flags
.color
) {
819 ADDR_COMPUTE_FMASK_INFO_INPUT fin
= {0};
820 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
821 ADDR_TILEINFO fmask_tile_info
= {};
823 fin
.size
= sizeof(fin
);
824 fout
.size
= sizeof(fout
);
826 fin
.tileMode
= AddrSurfInfoOut
.tileMode
;
827 fin
.pitch
= AddrSurfInfoOut
.pitch
;
828 fin
.height
= config
->info
.height
;
829 fin
.numSlices
= AddrSurfInfoIn
.numSlices
;
830 fin
.numSamples
= AddrSurfInfoIn
.numSamples
;
831 fin
.numFrags
= AddrSurfInfoIn
.numFrags
;
833 fout
.pTileInfo
= &fmask_tile_info
;
835 r
= AddrComputeFmaskInfo(addrlib
, &fin
, &fout
);
839 surf
->fmask_size
= fout
.fmaskBytes
;
840 surf
->fmask_alignment
= fout
.baseAlign
;
841 surf
->fmask_tile_swizzle
= 0;
843 surf
->u
.legacy
.fmask
.slice_tile_max
=
844 (fout
.pitch
* fout
.height
) / 64;
845 if (surf
->u
.legacy
.fmask
.slice_tile_max
)
846 surf
->u
.legacy
.fmask
.slice_tile_max
-= 1;
848 surf
->u
.legacy
.fmask
.tiling_index
= fout
.tileIndex
;
849 surf
->u
.legacy
.fmask
.bankh
= fout
.pTileInfo
->bankHeight
;
850 surf
->u
.legacy
.fmask
.pitch_in_pixels
= fout
.pitch
;
852 /* Compute tile swizzle for FMASK. */
853 if (config
->info
.fmask_surf_index
&&
854 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
855 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin
= {0};
856 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout
= {0};
858 xin
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
859 xout
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
861 /* This counter starts from 1 instead of 0. */
862 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
863 xin
.tileIndex
= fout
.tileIndex
;
864 xin
.macroModeIndex
= fout
.macroModeIndex
;
865 xin
.pTileInfo
= fout
.pTileInfo
;
866 xin
.tileMode
= fin
.tileMode
;
868 int r
= AddrComputeBaseSwizzle(addrlib
, &xin
, &xout
);
872 assert(xout
.tileSwizzle
<=
873 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
874 surf
->fmask_tile_swizzle
= xout
.tileSwizzle
;
878 /* Recalculate the whole DCC miptree size including disabled levels.
879 * This is what addrlib does, but calling addrlib would be a lot more
882 if (surf
->dcc_size
&& config
->info
.levels
> 1) {
883 /* The smallest miplevels that are never compressed by DCC
884 * still read the DCC buffer via TC if the base level uses DCC,
885 * and for some reason the DCC buffer needs to be larger if
886 * the miptree uses non-zero tile_swizzle. Otherwise there are
889 * "dcc_alignment * 4" was determined by trial and error.
891 surf
->dcc_size
= align64(surf
->surf_size
>> 8,
892 surf
->dcc_alignment
* 4);
895 /* Make sure HTILE covers the whole miptree, because the shader reads
896 * TC-compatible HTILE even for levels where it's disabled by DB.
898 if (surf
->htile_size
&& config
->info
.levels
> 1 &&
899 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) {
900 /* MSAA can't occur with levels > 1, so ignore the sample count. */
901 const unsigned total_pixels
= surf
->surf_size
/ surf
->bpe
;
902 const unsigned htile_block_size
= 8 * 8;
903 const unsigned htile_element_size
= 4;
905 surf
->htile_size
= (total_pixels
/ htile_block_size
) *
907 surf
->htile_size
= align(surf
->htile_size
, surf
->htile_alignment
);
910 surf
->is_linear
= surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
;
911 surf
->is_displayable
= surf
->is_linear
||
912 surf
->micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
||
913 surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
;
915 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
916 * used at the same time. This case is not currently expected to occur
917 * because we don't use rotated. Enforce this restriction on all chips
918 * to facilitate testing.
920 if (surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
) {
921 assert(!"rotate micro tile mode is unsupported");
925 ac_compute_cmask(info
, config
, surf
);
929 /* This is only called when expecting a tiled layout. */
931 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib
,
932 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
,
933 bool is_fmask
, AddrSwizzleMode
*swizzle_mode
)
935 ADDR_E_RETURNCODE ret
;
936 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin
= {0};
937 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout
= {0};
939 sin
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
);
940 sout
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
);
942 sin
.flags
= in
->flags
;
943 sin
.resourceType
= in
->resourceType
;
944 sin
.format
= in
->format
;
945 sin
.resourceLoction
= ADDR_RSRC_LOC_INVIS
;
946 /* TODO: We could allow some of these: */
947 sin
.forbiddenBlock
.micro
= 1; /* don't allow the 256B swizzle modes */
948 sin
.forbiddenBlock
.var
= 1; /* don't allow the variable-sized swizzle modes */
949 sin
.forbiddenBlock
.linear
= 1; /* don't allow linear swizzle modes */
951 sin
.width
= in
->width
;
952 sin
.height
= in
->height
;
953 sin
.numSlices
= in
->numSlices
;
954 sin
.numMipLevels
= in
->numMipLevels
;
955 sin
.numSamples
= in
->numSamples
;
956 sin
.numFrags
= in
->numFrags
;
959 sin
.flags
.display
= 0;
964 ret
= Addr2GetPreferredSurfaceSetting(addrlib
, &sin
, &sout
);
968 *swizzle_mode
= sout
.swizzleMode
;
972 static int gfx9_compute_miptree(ADDR_HANDLE addrlib
,
973 const struct radeon_info
*info
,
974 const struct ac_surf_config
*config
,
975 struct radeon_surf
*surf
, bool compressed
,
976 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
)
978 ADDR2_MIP_INFO mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
979 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out
= {0};
980 ADDR_E_RETURNCODE ret
;
982 out
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
);
983 out
.pMipInfo
= mip_info
;
985 ret
= Addr2ComputeSurfaceInfo(addrlib
, in
, &out
);
989 if (in
->flags
.stencil
) {
990 surf
->u
.gfx9
.stencil
.swizzle_mode
= in
->swizzleMode
;
991 surf
->u
.gfx9
.stencil
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
992 out
.mipChainPitch
- 1;
993 surf
->surf_alignment
= MAX2(surf
->surf_alignment
, out
.baseAlign
);
994 surf
->u
.gfx9
.stencil_offset
= align(surf
->surf_size
, out
.baseAlign
);
995 surf
->surf_size
= surf
->u
.gfx9
.stencil_offset
+ out
.surfSize
;
999 surf
->u
.gfx9
.surf
.swizzle_mode
= in
->swizzleMode
;
1000 surf
->u
.gfx9
.surf
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1001 out
.mipChainPitch
- 1;
1003 /* CMASK fast clear uses these even if FMASK isn't allocated.
1004 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1006 surf
->u
.gfx9
.fmask
.swizzle_mode
= surf
->u
.gfx9
.surf
.swizzle_mode
& ~0x3;
1007 surf
->u
.gfx9
.fmask
.epitch
= surf
->u
.gfx9
.surf
.epitch
;
1009 surf
->u
.gfx9
.surf_slice_size
= out
.sliceSize
;
1010 surf
->u
.gfx9
.surf_pitch
= out
.pitch
;
1011 surf
->u
.gfx9
.surf_height
= out
.height
;
1012 surf
->surf_size
= out
.surfSize
;
1013 surf
->surf_alignment
= out
.baseAlign
;
1015 if (in
->swizzleMode
== ADDR_SW_LINEAR
) {
1016 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++)
1017 surf
->u
.gfx9
.offset
[i
] = mip_info
[i
].offset
;
1020 if (in
->flags
.depth
) {
1021 assert(in
->swizzleMode
!= ADDR_SW_LINEAR
);
1024 ADDR2_COMPUTE_HTILE_INFO_INPUT hin
= {0};
1025 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout
= {0};
1027 hin
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT
);
1028 hout
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT
);
1030 hin
.hTileFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1031 hin
.hTileFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1032 hin
.depthFlags
= in
->flags
;
1033 hin
.swizzleMode
= in
->swizzleMode
;
1034 hin
.unalignedWidth
= in
->width
;
1035 hin
.unalignedHeight
= in
->height
;
1036 hin
.numSlices
= in
->numSlices
;
1037 hin
.numMipLevels
= in
->numMipLevels
;
1038 hin
.firstMipIdInTail
= out
.firstMipIdInTail
;
1040 ret
= Addr2ComputeHtileInfo(addrlib
, &hin
, &hout
);
1044 surf
->u
.gfx9
.htile
.rb_aligned
= hin
.hTileFlags
.rbAligned
;
1045 surf
->u
.gfx9
.htile
.pipe_aligned
= hin
.hTileFlags
.pipeAligned
;
1046 surf
->htile_size
= hout
.htileBytes
;
1047 surf
->htile_slice_size
= hout
.sliceSize
;
1048 surf
->htile_alignment
= hout
.baseAlign
;
1050 /* Compute tile swizzle for the color surface.
1051 * All *_X and *_T modes can use the swizzle.
1053 if (config
->info
.surf_index
&&
1054 in
->swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1055 !out
.mipChainInTail
&&
1056 !(surf
->flags
& RADEON_SURF_SHAREABLE
) &&
1057 !in
->flags
.display
) {
1058 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1059 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1061 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1062 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1064 xin
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
1065 xin
.flags
= in
->flags
;
1066 xin
.swizzleMode
= in
->swizzleMode
;
1067 xin
.resourceType
= in
->resourceType
;
1068 xin
.format
= in
->format
;
1069 xin
.numSamples
= in
->numSamples
;
1070 xin
.numFrags
= in
->numFrags
;
1072 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1076 assert(xout
.pipeBankXor
<=
1077 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
1078 surf
->tile_swizzle
= xout
.pipeBankXor
;
1082 if (!(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
1084 in
->swizzleMode
!= ADDR_SW_LINEAR
) {
1085 ADDR2_COMPUTE_DCCINFO_INPUT din
= {0};
1086 ADDR2_COMPUTE_DCCINFO_OUTPUT dout
= {0};
1087 ADDR2_META_MIP_INFO meta_mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1089 din
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_INPUT
);
1090 dout
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT
);
1091 dout
.pMipInfo
= meta_mip_info
;
1093 din
.dccKeyFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1094 din
.dccKeyFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1095 din
.colorFlags
= in
->flags
;
1096 din
.resourceType
= in
->resourceType
;
1097 din
.swizzleMode
= in
->swizzleMode
;
1099 din
.unalignedWidth
= in
->width
;
1100 din
.unalignedHeight
= in
->height
;
1101 din
.numSlices
= in
->numSlices
;
1102 din
.numFrags
= in
->numFrags
;
1103 din
.numMipLevels
= in
->numMipLevels
;
1104 din
.dataSurfaceSize
= out
.surfSize
;
1105 din
.firstMipIdInTail
= out
.firstMipIdInTail
;
1107 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1111 surf
->u
.gfx9
.dcc
.rb_aligned
= din
.dccKeyFlags
.rbAligned
;
1112 surf
->u
.gfx9
.dcc
.pipe_aligned
= din
.dccKeyFlags
.pipeAligned
;
1113 surf
->dcc_size
= dout
.dccRamSize
;
1114 surf
->dcc_alignment
= dout
.dccRamBaseAlign
;
1115 surf
->num_dcc_levels
= in
->numMipLevels
;
1117 /* Disable DCC for levels that are in the mip tail.
1119 * There are two issues that this is intended to
1122 * 1. Multiple mip levels may share a cache line. This
1123 * can lead to corruption when switching between
1124 * rendering to different mip levels because the
1125 * RBs don't maintain coherency.
1127 * 2. Texturing with metadata after rendering sometimes
1128 * fails with corruption, probably for a similar
1131 * Working around these issues for all levels in the
1132 * mip tail may be overly conservative, but it's what
1135 * Alternative solutions that also work but are worse:
1136 * - Disable DCC entirely.
1137 * - Flush TC L2 after rendering.
1139 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++) {
1140 if (meta_mip_info
[i
].inMiptail
) {
1141 surf
->num_dcc_levels
= i
;
1146 if (!surf
->num_dcc_levels
)
1149 surf
->u
.gfx9
.display_dcc_size
= surf
->dcc_size
;
1150 surf
->u
.gfx9
.display_dcc_alignment
= surf
->dcc_alignment
;
1151 surf
->u
.gfx9
.display_dcc_pitch_max
= dout
.pitch
- 1;
1153 /* Compute displayable DCC. */
1154 if (in
->flags
.display
&&
1155 surf
->num_dcc_levels
&&
1156 info
->use_display_dcc_with_retile_blit
) {
1157 /* Compute displayable DCC info. */
1158 din
.dccKeyFlags
.pipeAligned
= 0;
1159 din
.dccKeyFlags
.rbAligned
= 0;
1161 assert(din
.numSlices
== 1);
1162 assert(din
.numMipLevels
== 1);
1163 assert(din
.numFrags
== 1);
1164 assert(surf
->tile_swizzle
== 0);
1165 assert(surf
->u
.gfx9
.dcc
.pipe_aligned
||
1166 surf
->u
.gfx9
.dcc
.rb_aligned
);
1168 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1172 surf
->u
.gfx9
.display_dcc_size
= dout
.dccRamSize
;
1173 surf
->u
.gfx9
.display_dcc_alignment
= dout
.dccRamBaseAlign
;
1174 surf
->u
.gfx9
.display_dcc_pitch_max
= dout
.pitch
- 1;
1175 assert(surf
->u
.gfx9
.display_dcc_size
<= surf
->dcc_size
);
1177 /* Compute address mapping from non-displayable to displayable DCC. */
1178 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin
= {};
1179 addrin
.size
= sizeof(addrin
);
1180 addrin
.colorFlags
.color
= 1;
1181 addrin
.swizzleMode
= din
.swizzleMode
;
1182 addrin
.resourceType
= din
.resourceType
;
1183 addrin
.bpp
= din
.bpp
;
1184 addrin
.unalignedWidth
= din
.unalignedWidth
;
1185 addrin
.unalignedHeight
= din
.unalignedHeight
;
1186 addrin
.numSlices
= 1;
1187 addrin
.numMipLevels
= 1;
1188 addrin
.numFrags
= 1;
1190 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout
= {};
1191 addrout
.size
= sizeof(addrout
);
1193 surf
->u
.gfx9
.dcc_retile_num_elements
=
1194 DIV_ROUND_UP(in
->width
, dout
.compressBlkWidth
) *
1195 DIV_ROUND_UP(in
->height
, dout
.compressBlkHeight
) * 2;
1196 /* Align the size to 4 (for the compute shader). */
1197 surf
->u
.gfx9
.dcc_retile_num_elements
=
1198 align(surf
->u
.gfx9
.dcc_retile_num_elements
, 4);
1200 surf
->u
.gfx9
.dcc_retile_map
=
1201 malloc(surf
->u
.gfx9
.dcc_retile_num_elements
* 4);
1202 if (!surf
->u
.gfx9
.dcc_retile_map
)
1203 return ADDR_OUTOFMEMORY
;
1206 surf
->u
.gfx9
.dcc_retile_use_uint16
= true;
1208 for (unsigned y
= 0; y
< in
->height
; y
+= dout
.compressBlkHeight
) {
1211 for (unsigned x
= 0; x
< in
->width
; x
+= dout
.compressBlkWidth
) {
1214 /* Compute src DCC address */
1215 addrin
.dccKeyFlags
.pipeAligned
= surf
->u
.gfx9
.dcc
.pipe_aligned
;
1216 addrin
.dccKeyFlags
.rbAligned
= surf
->u
.gfx9
.dcc
.rb_aligned
;
1219 ret
= Addr2ComputeDccAddrFromCoord(addrlib
, &addrin
, &addrout
);
1223 surf
->u
.gfx9
.dcc_retile_map
[index
* 2] = addrout
.addr
;
1224 if (addrout
.addr
> USHRT_MAX
)
1225 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1227 /* Compute dst DCC address */
1228 addrin
.dccKeyFlags
.pipeAligned
= 0;
1229 addrin
.dccKeyFlags
.rbAligned
= 0;
1232 ret
= Addr2ComputeDccAddrFromCoord(addrlib
, &addrin
, &addrout
);
1236 surf
->u
.gfx9
.dcc_retile_map
[index
* 2 + 1] = addrout
.addr
;
1237 if (addrout
.addr
> USHRT_MAX
)
1238 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1240 assert(index
* 2 + 1 < surf
->u
.gfx9
.dcc_retile_num_elements
);
1244 /* Fill the remaining pairs with the last one (for the compute shader). */
1245 for (unsigned i
= index
* 2; i
< surf
->u
.gfx9
.dcc_retile_num_elements
; i
++)
1246 surf
->u
.gfx9
.dcc_retile_map
[i
] = surf
->u
.gfx9
.dcc_retile_map
[i
- 2];
1251 if (in
->numSamples
> 1) {
1252 ADDR2_COMPUTE_FMASK_INFO_INPUT fin
= {0};
1253 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
1255 fin
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT
);
1256 fout
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT
);
1258 ret
= gfx9_get_preferred_swizzle_mode(addrlib
, in
,
1259 true, &fin
.swizzleMode
);
1263 fin
.unalignedWidth
= in
->width
;
1264 fin
.unalignedHeight
= in
->height
;
1265 fin
.numSlices
= in
->numSlices
;
1266 fin
.numSamples
= in
->numSamples
;
1267 fin
.numFrags
= in
->numFrags
;
1269 ret
= Addr2ComputeFmaskInfo(addrlib
, &fin
, &fout
);
1273 surf
->u
.gfx9
.fmask
.swizzle_mode
= fin
.swizzleMode
;
1274 surf
->u
.gfx9
.fmask
.epitch
= fout
.pitch
- 1;
1275 surf
->fmask_size
= fout
.fmaskBytes
;
1276 surf
->fmask_alignment
= fout
.baseAlign
;
1278 /* Compute tile swizzle for the FMASK surface. */
1279 if (config
->info
.fmask_surf_index
&&
1280 fin
.swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1281 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
1282 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1283 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1285 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1286 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1288 /* This counter starts from 1 instead of 0. */
1289 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
1290 xin
.flags
= in
->flags
;
1291 xin
.swizzleMode
= fin
.swizzleMode
;
1292 xin
.resourceType
= in
->resourceType
;
1293 xin
.format
= in
->format
;
1294 xin
.numSamples
= in
->numSamples
;
1295 xin
.numFrags
= in
->numFrags
;
1297 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1301 assert(xout
.pipeBankXor
<=
1302 u_bit_consecutive(0, sizeof(surf
->fmask_tile_swizzle
) * 8));
1303 surf
->fmask_tile_swizzle
= xout
.pipeBankXor
;
1308 if (in
->swizzleMode
!= ADDR_SW_LINEAR
) {
1309 ADDR2_COMPUTE_CMASK_INFO_INPUT cin
= {0};
1310 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout
= {0};
1312 cin
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT
);
1313 cout
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT
);
1315 if (in
->numSamples
> 1) {
1316 /* FMASK is always aligned. */
1317 cin
.cMaskFlags
.pipeAligned
= 1;
1318 cin
.cMaskFlags
.rbAligned
= 1;
1320 cin
.cMaskFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1321 cin
.cMaskFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1323 cin
.colorFlags
= in
->flags
;
1324 cin
.resourceType
= in
->resourceType
;
1325 cin
.unalignedWidth
= in
->width
;
1326 cin
.unalignedHeight
= in
->height
;
1327 cin
.numSlices
= in
->numSlices
;
1329 if (in
->numSamples
> 1)
1330 cin
.swizzleMode
= surf
->u
.gfx9
.fmask
.swizzle_mode
;
1332 cin
.swizzleMode
= in
->swizzleMode
;
1334 ret
= Addr2ComputeCmaskInfo(addrlib
, &cin
, &cout
);
1338 surf
->u
.gfx9
.cmask
.rb_aligned
= cin
.cMaskFlags
.rbAligned
;
1339 surf
->u
.gfx9
.cmask
.pipe_aligned
= cin
.cMaskFlags
.pipeAligned
;
1340 surf
->cmask_size
= cout
.cmaskBytes
;
1341 surf
->cmask_alignment
= cout
.baseAlign
;
1348 static int gfx9_compute_surface(ADDR_HANDLE addrlib
,
1349 const struct radeon_info
*info
,
1350 const struct ac_surf_config
*config
,
1351 enum radeon_surf_mode mode
,
1352 struct radeon_surf
*surf
)
1355 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
1358 AddrSurfInfoIn
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT
);
1360 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
1362 /* The format must be set correctly for the allocation of compressed
1363 * textures to work. In other cases, setting the bpp is sufficient. */
1365 switch (surf
->bpe
) {
1367 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
1370 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
1376 switch (surf
->bpe
) {
1378 assert(!(surf
->flags
& RADEON_SURF_ZBUFFER
));
1379 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1382 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1383 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1384 AddrSurfInfoIn
.format
= ADDR_FMT_16
;
1387 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1388 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1389 AddrSurfInfoIn
.format
= ADDR_FMT_32
;
1392 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1393 AddrSurfInfoIn
.format
= ADDR_FMT_32_32
;
1396 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1397 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32
;
1400 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1401 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32_32
;
1406 AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
1409 bool is_color_surface
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
1410 AddrSurfInfoIn
.flags
.color
= is_color_surface
&&
1411 !(surf
->flags
& RADEON_SURF_NO_RENDER_TARGET
);
1412 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
1413 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
1414 /* flags.texture currently refers to TC-compatible HTILE */
1415 AddrSurfInfoIn
.flags
.texture
= is_color_surface
||
1416 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1417 AddrSurfInfoIn
.flags
.opt4space
= 1;
1419 AddrSurfInfoIn
.numMipLevels
= config
->info
.levels
;
1420 AddrSurfInfoIn
.numSamples
= MAX2(1, config
->info
.samples
);
1421 AddrSurfInfoIn
.numFrags
= AddrSurfInfoIn
.numSamples
;
1423 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
))
1424 AddrSurfInfoIn
.numFrags
= MAX2(1, config
->info
.storage_samples
);
1426 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1427 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1428 * must sample 1D textures as 2D. */
1430 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_3D
;
1432 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_2D
;
1434 AddrSurfInfoIn
.width
= config
->info
.width
;
1435 AddrSurfInfoIn
.height
= config
->info
.height
;
1438 AddrSurfInfoIn
.numSlices
= config
->info
.depth
;
1439 else if (config
->is_cube
)
1440 AddrSurfInfoIn
.numSlices
= 6;
1442 AddrSurfInfoIn
.numSlices
= config
->info
.array_size
;
1444 /* This is propagated to HTILE/DCC/CMASK. */
1445 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 0;
1446 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 0;
1448 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1449 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1451 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1452 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1453 * after rendering, so PIPE_ALIGNED=1 is recommended.
1455 if (info
->use_display_dcc_unaligned
&& is_color_surface
&&
1456 AddrSurfInfoIn
.flags
.display
) {
1457 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 1;
1458 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 1;
1462 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1463 assert(config
->info
.samples
<= 1);
1464 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1465 AddrSurfInfoIn
.swizzleMode
= ADDR_SW_LINEAR
;
1468 case RADEON_SURF_MODE_1D
:
1469 case RADEON_SURF_MODE_2D
:
1470 if (surf
->flags
& RADEON_SURF_IMPORTED
) {
1471 AddrSurfInfoIn
.swizzleMode
= surf
->u
.gfx9
.surf
.swizzle_mode
;
1475 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1476 false, &AddrSurfInfoIn
.swizzleMode
);
1485 surf
->u
.gfx9
.resource_type
= AddrSurfInfoIn
.resourceType
;
1486 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
1488 surf
->num_dcc_levels
= 0;
1489 surf
->surf_size
= 0;
1490 surf
->fmask_size
= 0;
1492 surf
->htile_size
= 0;
1493 surf
->htile_slice_size
= 0;
1494 surf
->u
.gfx9
.surf_offset
= 0;
1495 surf
->u
.gfx9
.stencil_offset
= 0;
1496 surf
->cmask_size
= 0;
1497 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1498 surf
->u
.gfx9
.dcc_retile_num_elements
= 0;
1499 surf
->u
.gfx9
.dcc_retile_map
= NULL
;
1501 /* Calculate texture layout information. */
1502 r
= gfx9_compute_miptree(addrlib
, info
, config
, surf
, compressed
,
1507 /* Calculate texture layout information for stencil. */
1508 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
1509 AddrSurfInfoIn
.flags
.stencil
= 1;
1510 AddrSurfInfoIn
.bpp
= 8;
1511 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1513 if (!AddrSurfInfoIn
.flags
.depth
) {
1514 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1515 false, &AddrSurfInfoIn
.swizzleMode
);
1519 AddrSurfInfoIn
.flags
.depth
= 0;
1521 r
= gfx9_compute_miptree(addrlib
, info
, config
, surf
, compressed
,
1527 surf
->is_linear
= surf
->u
.gfx9
.surf
.swizzle_mode
== ADDR_SW_LINEAR
;
1529 /* Query whether the surface is displayable. */
1530 bool displayable
= false;
1531 if (!config
->is_3d
&& !config
->is_cube
) {
1532 r
= Addr2IsValidDisplaySwizzleMode(addrlib
, surf
->u
.gfx9
.surf
.swizzle_mode
,
1533 surf
->bpe
* 8, &displayable
);
1537 /* Display needs unaligned DCC. */
1538 if (info
->use_display_dcc_unaligned
&&
1539 surf
->num_dcc_levels
&&
1540 (surf
->u
.gfx9
.dcc
.pipe_aligned
||
1541 surf
->u
.gfx9
.dcc
.rb_aligned
))
1542 displayable
= false;
1544 surf
->is_displayable
= displayable
;
1546 switch (surf
->u
.gfx9
.surf
.swizzle_mode
) {
1548 case ADDR_SW_256B_S
:
1550 case ADDR_SW_64KB_S
:
1552 case ADDR_SW_64KB_S_T
:
1553 case ADDR_SW_4KB_S_X
:
1554 case ADDR_SW_64KB_S_X
:
1555 case ADDR_SW_VAR_S_X
:
1556 surf
->micro_tile_mode
= RADEON_MICRO_MODE_THIN
;
1560 case ADDR_SW_LINEAR
:
1561 case ADDR_SW_256B_D
:
1563 case ADDR_SW_64KB_D
:
1565 case ADDR_SW_64KB_D_T
:
1566 case ADDR_SW_4KB_D_X
:
1567 case ADDR_SW_64KB_D_X
:
1568 case ADDR_SW_VAR_D_X
:
1569 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DISPLAY
;
1573 case ADDR_SW_256B_R
:
1575 case ADDR_SW_64KB_R
:
1577 case ADDR_SW_64KB_R_T
:
1578 case ADDR_SW_4KB_R_X
:
1579 case ADDR_SW_64KB_R_X
:
1580 case ADDR_SW_VAR_R_X
:
1581 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1582 * used at the same time. This case is not currently expected to occur
1583 * because we don't use rotated. Enforce this restriction on all chips
1584 * to facilitate testing.
1586 assert(!"rotate micro tile mode is unsupported");
1592 case ADDR_SW_64KB_Z
:
1594 case ADDR_SW_64KB_Z_T
:
1595 case ADDR_SW_4KB_Z_X
:
1596 case ADDR_SW_64KB_Z_X
:
1597 case ADDR_SW_VAR_Z_X
:
1598 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DEPTH
;
1608 free(surf
->u
.gfx9
.dcc_retile_map
);
1609 surf
->u
.gfx9
.dcc_retile_map
= NULL
;
1613 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
1614 const struct ac_surf_config
*config
,
1615 enum radeon_surf_mode mode
,
1616 struct radeon_surf
*surf
)
1620 r
= surf_config_sanity(config
, surf
->flags
);
1624 if (info
->chip_class
>= GFX9
)
1625 return gfx9_compute_surface(addrlib
, info
, config
, mode
, surf
);
1627 return gfx6_compute_surface(addrlib
, info
, config
, mode
, surf
);