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ac/surface/gfx9: fix a typo in CMASK RB/pipe alignment
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static unsigned get_first(unsigned x, unsigned y)
53 {
54 return x;
55 }
56
57 static void addrlib_family_rev_id(enum radeon_family family,
58 unsigned *addrlib_family,
59 unsigned *addrlib_revid)
60 {
61 switch (family) {
62 case CHIP_TAHITI:
63 *addrlib_family = FAMILY_SI;
64 *addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
65 break;
66 case CHIP_PITCAIRN:
67 *addrlib_family = FAMILY_SI;
68 *addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
69 break;
70 case CHIP_VERDE:
71 *addrlib_family = FAMILY_SI;
72 *addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
73 break;
74 case CHIP_OLAND:
75 *addrlib_family = FAMILY_SI;
76 *addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
77 break;
78 case CHIP_HAINAN:
79 *addrlib_family = FAMILY_SI;
80 *addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
81 break;
82 case CHIP_BONAIRE:
83 *addrlib_family = FAMILY_CI;
84 *addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
85 break;
86 case CHIP_KAVERI:
87 *addrlib_family = FAMILY_KV;
88 *addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
89 break;
90 case CHIP_KABINI:
91 *addrlib_family = FAMILY_KV;
92 *addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
93 break;
94 case CHIP_HAWAII:
95 *addrlib_family = FAMILY_CI;
96 *addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
97 break;
98 case CHIP_MULLINS:
99 *addrlib_family = FAMILY_KV;
100 *addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE);
101 break;
102 case CHIP_TONGA:
103 *addrlib_family = FAMILY_VI;
104 *addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
105 break;
106 case CHIP_ICELAND:
107 *addrlib_family = FAMILY_VI;
108 *addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
109 break;
110 case CHIP_CARRIZO:
111 *addrlib_family = FAMILY_CZ;
112 *addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
113 break;
114 case CHIP_STONEY:
115 *addrlib_family = FAMILY_CZ;
116 *addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
117 break;
118 case CHIP_FIJI:
119 *addrlib_family = FAMILY_VI;
120 *addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
121 break;
122 case CHIP_POLARIS10:
123 *addrlib_family = FAMILY_VI;
124 *addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
125 break;
126 case CHIP_POLARIS11:
127 *addrlib_family = FAMILY_VI;
128 *addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
129 break;
130 case CHIP_POLARIS12:
131 *addrlib_family = FAMILY_VI;
132 *addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
133 break;
134 case CHIP_VEGAM:
135 *addrlib_family = FAMILY_VI;
136 *addrlib_revid = get_first(AMDGPU_VEGAM_RANGE);
137 break;
138 case CHIP_VEGA10:
139 *addrlib_family = FAMILY_AI;
140 *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
141 break;
142 case CHIP_VEGA12:
143 *addrlib_family = FAMILY_AI;
144 *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
145 break;
146 case CHIP_RAVEN:
147 *addrlib_family = FAMILY_RV;
148 *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
149 break;
150 default:
151 fprintf(stderr, "amdgpu: Unknown family.\n");
152 }
153 }
154
155 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
156 {
157 return malloc(pInput->sizeInBytes);
158 }
159
160 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
161 {
162 free(pInput->pVirtAddr);
163 return ADDR_OK;
164 }
165
166 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
167 const struct amdgpu_gpu_info *amdinfo,
168 uint64_t *max_alignment)
169 {
170 ADDR_CREATE_INPUT addrCreateInput = {0};
171 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
172 ADDR_REGISTER_VALUE regValue = {0};
173 ADDR_CREATE_FLAGS createFlags = {{0}};
174 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
175 ADDR_E_RETURNCODE addrRet;
176
177 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
178 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
179
180 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
181 createFlags.value = 0;
182
183 addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
184 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
185 return NULL;
186
187 if (addrCreateInput.chipFamily >= FAMILY_AI) {
188 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
189 regValue.blockVarSizeLog2 = 0;
190 } else {
191 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
192 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
193
194 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
195 regValue.pTileConfig = amdinfo->gb_tile_mode;
196 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
197 if (addrCreateInput.chipFamily == FAMILY_SI) {
198 regValue.pMacroTileConfig = NULL;
199 regValue.noOfMacroEntries = 0;
200 } else {
201 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
202 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
203 }
204
205 createFlags.useTileIndex = 1;
206 createFlags.useHtileSliceAlign = 1;
207
208 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
209 }
210
211 addrCreateInput.callbacks.allocSysMem = allocSysMem;
212 addrCreateInput.callbacks.freeSysMem = freeSysMem;
213 addrCreateInput.callbacks.debugPrint = 0;
214 addrCreateInput.createFlags = createFlags;
215 addrCreateInput.regValue = regValue;
216
217 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
218 if (addrRet != ADDR_OK)
219 return NULL;
220
221 if (max_alignment) {
222 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
223 if (addrRet == ADDR_OK){
224 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
225 }
226 }
227 return addrCreateOutput.hLib;
228 }
229
230 static int surf_config_sanity(const struct ac_surf_config *config)
231 {
232 /* all dimension must be at least 1 ! */
233 if (!config->info.width || !config->info.height || !config->info.depth ||
234 !config->info.array_size || !config->info.levels)
235 return -EINVAL;
236
237 switch (config->info.samples) {
238 case 0:
239 case 1:
240 case 2:
241 case 4:
242 case 8:
243 break;
244 default:
245 return -EINVAL;
246 }
247
248 if (config->is_3d && config->info.array_size > 1)
249 return -EINVAL;
250 if (config->is_cube && config->info.depth > 1)
251 return -EINVAL;
252
253 return 0;
254 }
255
256 static int gfx6_compute_level(ADDR_HANDLE addrlib,
257 const struct ac_surf_config *config,
258 struct radeon_surf *surf, bool is_stencil,
259 unsigned level, bool compressed,
260 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
261 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
262 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
263 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
264 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
265 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
266 {
267 struct legacy_surf_level *surf_level;
268 ADDR_E_RETURNCODE ret;
269
270 AddrSurfInfoIn->mipLevel = level;
271 AddrSurfInfoIn->width = u_minify(config->info.width, level);
272 AddrSurfInfoIn->height = u_minify(config->info.height, level);
273
274 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
275 * because GFX9 needs linear alignment of 256 bytes.
276 */
277 if (config->info.levels == 1 &&
278 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
279 AddrSurfInfoIn->bpp) {
280 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
281
282 assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
283 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
284 }
285
286 if (config->is_3d)
287 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
288 else if (config->is_cube)
289 AddrSurfInfoIn->numSlices = 6;
290 else
291 AddrSurfInfoIn->numSlices = config->info.array_size;
292
293 if (level > 0) {
294 /* Set the base level pitch. This is needed for calculation
295 * of non-zero levels. */
296 if (is_stencil)
297 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
298 else
299 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
300
301 /* Convert blocks to pixels for compressed formats. */
302 if (compressed)
303 AddrSurfInfoIn->basePitch *= surf->blk_w;
304 }
305
306 ret = AddrComputeSurfaceInfo(addrlib,
307 AddrSurfInfoIn,
308 AddrSurfInfoOut);
309 if (ret != ADDR_OK) {
310 return ret;
311 }
312
313 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
314 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
315 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
316 surf_level->nblk_x = AddrSurfInfoOut->pitch;
317 surf_level->nblk_y = AddrSurfInfoOut->height;
318
319 switch (AddrSurfInfoOut->tileMode) {
320 case ADDR_TM_LINEAR_ALIGNED:
321 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
322 break;
323 case ADDR_TM_1D_TILED_THIN1:
324 surf_level->mode = RADEON_SURF_MODE_1D;
325 break;
326 case ADDR_TM_2D_TILED_THIN1:
327 surf_level->mode = RADEON_SURF_MODE_2D;
328 break;
329 default:
330 assert(0);
331 }
332
333 if (is_stencil)
334 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
335 else
336 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
337
338 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
339
340 /* Clear DCC fields at the beginning. */
341 surf_level->dcc_offset = 0;
342
343 /* The previous level's flag tells us if we can use DCC for this level. */
344 if (AddrSurfInfoIn->flags.dccCompatible &&
345 (level == 0 || AddrDccOut->subLvlCompressible)) {
346 bool prev_level_clearable = level == 0 ||
347 AddrDccOut->dccRamSizeAligned;
348
349 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
350 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
351 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
352 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
353 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
354
355 ret = AddrComputeDccInfo(addrlib,
356 AddrDccIn,
357 AddrDccOut);
358
359 if (ret == ADDR_OK) {
360 surf_level->dcc_offset = surf->dcc_size;
361 surf->num_dcc_levels = level + 1;
362 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
363 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
364
365 /* If the DCC size of a subresource (1 mip level or 1 slice)
366 * is not aligned, the DCC memory layout is not contiguous for
367 * that subresource, which means we can't use fast clear.
368 *
369 * We only do fast clears for whole mipmap levels. If we did
370 * per-slice fast clears, the same restriction would apply.
371 * (i.e. only compute the slice size and see if it's aligned)
372 *
373 * The last level can be non-contiguous and still be clearable
374 * if it's interleaved with the next level that doesn't exist.
375 */
376 if (AddrDccOut->dccRamSizeAligned ||
377 (prev_level_clearable && level == config->info.levels - 1))
378 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
379 else
380 surf_level->dcc_fast_clear_size = 0;
381 }
382 }
383
384 /* TC-compatible HTILE. */
385 if (!is_stencil &&
386 AddrSurfInfoIn->flags.depth &&
387 surf_level->mode == RADEON_SURF_MODE_2D &&
388 level == 0) {
389 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
390 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
391 AddrHtileIn->height = AddrSurfInfoOut->height;
392 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
393 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
394 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
395 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
396 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
397 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
398
399 ret = AddrComputeHtileInfo(addrlib,
400 AddrHtileIn,
401 AddrHtileOut);
402
403 if (ret == ADDR_OK) {
404 surf->htile_size = AddrHtileOut->htileBytes;
405 surf->htile_slice_size = AddrHtileOut->sliceSize;
406 surf->htile_alignment = AddrHtileOut->baseAlign;
407 }
408 }
409
410 return 0;
411 }
412
413 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
414 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
415
416 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
417 const struct radeon_info *info)
418 {
419 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
420
421 if (info->chip_class >= CIK)
422 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
423 else
424 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
425 }
426
427 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
428 {
429 unsigned index, tileb;
430
431 tileb = 8 * 8 * surf->bpe;
432 tileb = MIN2(surf->u.legacy.tile_split, tileb);
433
434 for (index = 0; tileb > 64; index++)
435 tileb >>= 1;
436
437 assert(index < 16);
438 return index;
439 }
440
441 static bool get_display_flag(const struct ac_surf_config *config,
442 const struct radeon_surf *surf)
443 {
444 unsigned num_channels = config->info.num_channels;
445 unsigned bpe = surf->bpe;
446
447 if (surf->flags & RADEON_SURF_SCANOUT &&
448 !(surf->flags & RADEON_SURF_FMASK) &&
449 config->info.samples <= 1 &&
450 surf->blk_w <= 2 && surf->blk_h == 1) {
451 /* subsampled */
452 if (surf->blk_w == 2 && surf->blk_h == 1)
453 return true;
454
455 if (/* RGBA8 or RGBA16F */
456 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
457 /* R5G6B5 or R5G5B5A1 */
458 (bpe == 2 && num_channels >= 3) ||
459 /* C8 palette */
460 (bpe == 1 && num_channels == 1))
461 return true;
462 }
463 return false;
464 }
465
466 /**
467 * This must be called after the first level is computed.
468 *
469 * Copy surface-global settings like pipe/bank config from level 0 surface
470 * computation, and compute tile swizzle.
471 */
472 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
473 const struct radeon_info *info,
474 const struct ac_surf_config *config,
475 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
476 struct radeon_surf *surf)
477 {
478 surf->surf_alignment = csio->baseAlign;
479 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
480 gfx6_set_micro_tile_mode(surf, info);
481
482 /* For 2D modes only. */
483 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
484 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
485 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
486 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
487 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
488 surf->u.legacy.num_banks = csio->pTileInfo->banks;
489 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
490 } else {
491 surf->u.legacy.macro_tile_index = 0;
492 }
493
494 /* Compute tile swizzle. */
495 /* TODO: fix tile swizzle with mipmapping for SI */
496 if ((info->chip_class >= CIK || config->info.levels == 1) &&
497 config->info.surf_index &&
498 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
499 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
500 !get_display_flag(config, surf)) {
501 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
502 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
503
504 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
505 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
506
507 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
508 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
509 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
510 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
511 AddrBaseSwizzleIn.tileMode = csio->tileMode;
512
513 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
514 &AddrBaseSwizzleOut);
515 if (r != ADDR_OK)
516 return r;
517
518 assert(AddrBaseSwizzleOut.tileSwizzle <=
519 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
520 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
521 }
522 return 0;
523 }
524
525 /**
526 * Fill in the tiling information in \p surf based on the given surface config.
527 *
528 * The following fields of \p surf must be initialized by the caller:
529 * blk_w, blk_h, bpe, flags.
530 */
531 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
532 const struct radeon_info *info,
533 const struct ac_surf_config *config,
534 enum radeon_surf_mode mode,
535 struct radeon_surf *surf)
536 {
537 unsigned level;
538 bool compressed;
539 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
540 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
541 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
542 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
543 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
544 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
545 ADDR_TILEINFO AddrTileInfoIn = {0};
546 ADDR_TILEINFO AddrTileInfoOut = {0};
547 int r;
548
549 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
550 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
551 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
552 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
553 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
554 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
555 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
556
557 compressed = surf->blk_w == 4 && surf->blk_h == 4;
558
559 /* MSAA and FMASK require 2D tiling. */
560 if (config->info.samples > 1 ||
561 (surf->flags & RADEON_SURF_FMASK))
562 mode = RADEON_SURF_MODE_2D;
563
564 /* DB doesn't support linear layouts. */
565 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
566 mode < RADEON_SURF_MODE_1D)
567 mode = RADEON_SURF_MODE_1D;
568
569 /* Set the requested tiling mode. */
570 switch (mode) {
571 case RADEON_SURF_MODE_LINEAR_ALIGNED:
572 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
573 break;
574 case RADEON_SURF_MODE_1D:
575 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
576 break;
577 case RADEON_SURF_MODE_2D:
578 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
579 break;
580 default:
581 assert(0);
582 }
583
584 /* The format must be set correctly for the allocation of compressed
585 * textures to work. In other cases, setting the bpp is sufficient.
586 */
587 if (compressed) {
588 switch (surf->bpe) {
589 case 8:
590 AddrSurfInfoIn.format = ADDR_FMT_BC1;
591 break;
592 case 16:
593 AddrSurfInfoIn.format = ADDR_FMT_BC3;
594 break;
595 default:
596 assert(0);
597 }
598 }
599 else {
600 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
601 }
602
603 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
604 config->info.samples ? config->info.samples : 1;
605 AddrSurfInfoIn.tileIndex = -1;
606
607 /* Set the micro tile type. */
608 if (surf->flags & RADEON_SURF_SCANOUT)
609 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
610 else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
611 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
612 else
613 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
614
615 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
616 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
617 AddrSurfInfoIn.flags.cube = config->is_cube;
618 AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
619 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
620 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
621 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
622
623 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
624 * requested, because TC-compatible HTILE requires 2D tiling.
625 */
626 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
627 !AddrSurfInfoIn.flags.fmask &&
628 config->info.samples <= 1 &&
629 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
630
631 /* DCC notes:
632 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
633 * with samples >= 4.
634 * - Mipmapped array textures have low performance (discovered by a closed
635 * driver team).
636 */
637 AddrSurfInfoIn.flags.dccCompatible =
638 info->chip_class >= VI &&
639 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
640 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
641 !compressed &&
642 ((config->info.array_size == 1 && config->info.depth == 1) ||
643 config->info.levels == 1);
644
645 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
646 AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
647
648 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
649 * for Z and stencil. This can cause a number of problems which we work
650 * around here:
651 *
652 * - a depth part that is incompatible with mipmapped texturing
653 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
654 * incorrect tiling applied to the stencil part, stencil buffer
655 * memory accesses that go out of bounds) even without mipmapping
656 *
657 * Some piglit tests that are prone to different types of related
658 * failures:
659 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
660 * ./bin/framebuffer-blit-levels {draw,read} stencil
661 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
662 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
663 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
664 */
665 int stencil_tile_idx = -1;
666
667 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
668 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
669 /* Compute stencilTileIdx that is compatible with the (depth)
670 * tileIdx. This degrades the depth surface if necessary to
671 * ensure that a matching stencilTileIdx exists. */
672 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
673
674 /* Keep the depth mip-tail compatible with texturing. */
675 AddrSurfInfoIn.flags.noStencil = 1;
676 }
677
678 /* Set preferred macrotile parameters. This is usually required
679 * for shared resources. This is for 2D tiling only. */
680 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
681 surf->u.legacy.bankw && surf->u.legacy.bankh &&
682 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
683 assert(!(surf->flags & RADEON_SURF_FMASK));
684
685 /* If any of these parameters are incorrect, the calculation
686 * will fail. */
687 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
688 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
689 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
690 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
691 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
692 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
693 AddrSurfInfoIn.flags.opt4Space = 0;
694 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
695
696 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
697 * the tile index, because we are expected to know it if
698 * we know the other parameters.
699 *
700 * This is something that can easily be fixed in Addrlib.
701 * For now, just figure it out here.
702 * Note that only 2D_TILE_THIN1 is handled here.
703 */
704 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
705 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
706
707 if (info->chip_class == SI) {
708 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
709 if (surf->bpe == 2)
710 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
711 else
712 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
713 } else {
714 if (surf->bpe == 1)
715 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
716 else if (surf->bpe == 2)
717 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
718 else if (surf->bpe == 4)
719 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
720 else
721 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
722 }
723 } else {
724 /* CIK - VI */
725 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
726 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
727 else
728 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
729
730 /* Addrlib doesn't set this if tileIndex is forced like above. */
731 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
732 }
733 }
734
735 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
736 surf->num_dcc_levels = 0;
737 surf->surf_size = 0;
738 surf->dcc_size = 0;
739 surf->dcc_alignment = 1;
740 surf->htile_size = 0;
741 surf->htile_slice_size = 0;
742 surf->htile_alignment = 1;
743
744 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
745 !(surf->flags & RADEON_SURF_ZBUFFER);
746
747 /* Calculate texture layout information. */
748 if (!only_stencil) {
749 for (level = 0; level < config->info.levels; level++) {
750 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
751 &AddrSurfInfoIn, &AddrSurfInfoOut,
752 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
753 if (r)
754 return r;
755
756 if (level > 0)
757 continue;
758
759 /* Check that we actually got a TC-compatible HTILE if
760 * we requested it (only for level 0, since we're not
761 * supporting HTILE on higher mip levels anyway). */
762 assert(AddrSurfInfoOut.tcCompatible ||
763 !AddrSurfInfoIn.flags.tcCompatible ||
764 AddrSurfInfoIn.flags.matchStencilTileCfg);
765
766 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
767 if (!AddrSurfInfoOut.tcCompatible) {
768 AddrSurfInfoIn.flags.tcCompatible = 0;
769 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
770 }
771
772 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
773 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
774 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
775
776 assert(stencil_tile_idx >= 0);
777 }
778
779 r = gfx6_surface_settings(addrlib, info, config,
780 &AddrSurfInfoOut, surf);
781 if (r)
782 return r;
783 }
784 }
785
786 /* Calculate texture layout information for stencil. */
787 if (surf->flags & RADEON_SURF_SBUFFER) {
788 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
789 AddrSurfInfoIn.bpp = 8;
790 AddrSurfInfoIn.flags.depth = 0;
791 AddrSurfInfoIn.flags.stencil = 1;
792 AddrSurfInfoIn.flags.tcCompatible = 0;
793 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
794 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
795
796 for (level = 0; level < config->info.levels; level++) {
797 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
798 &AddrSurfInfoIn, &AddrSurfInfoOut,
799 &AddrDccIn, &AddrDccOut,
800 NULL, NULL);
801 if (r)
802 return r;
803
804 /* DB uses the depth pitch for both stencil and depth. */
805 if (!only_stencil) {
806 if (surf->u.legacy.stencil_level[level].nblk_x !=
807 surf->u.legacy.level[level].nblk_x)
808 surf->u.legacy.stencil_adjusted = true;
809 } else {
810 surf->u.legacy.level[level].nblk_x =
811 surf->u.legacy.stencil_level[level].nblk_x;
812 }
813
814 if (level == 0) {
815 if (only_stencil) {
816 r = gfx6_surface_settings(addrlib, info, config,
817 &AddrSurfInfoOut, surf);
818 if (r)
819 return r;
820 }
821
822 /* For 2D modes only. */
823 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
824 surf->u.legacy.stencil_tile_split =
825 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
826 }
827 }
828 }
829 }
830
831 /* Recalculate the whole DCC miptree size including disabled levels.
832 * This is what addrlib does, but calling addrlib would be a lot more
833 * complicated.
834 */
835 if (surf->dcc_size && config->info.levels > 1) {
836 /* The smallest miplevels that are never compressed by DCC
837 * still read the DCC buffer via TC if the base level uses DCC,
838 * and for some reason the DCC buffer needs to be larger if
839 * the miptree uses non-zero tile_swizzle. Otherwise there are
840 * VM faults.
841 *
842 * "dcc_alignment * 4" was determined by trial and error.
843 */
844 surf->dcc_size = align64(surf->surf_size >> 8,
845 surf->dcc_alignment * 4);
846 }
847
848 /* Make sure HTILE covers the whole miptree, because the shader reads
849 * TC-compatible HTILE even for levels where it's disabled by DB.
850 */
851 if (surf->htile_size && config->info.levels > 1)
852 surf->htile_size *= 2;
853
854 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
855 surf->is_displayable = surf->is_linear ||
856 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
857 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
858 return 0;
859 }
860
861 /* This is only called when expecting a tiled layout. */
862 static int
863 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
864 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
865 bool is_fmask, unsigned flags,
866 AddrSwizzleMode *swizzle_mode)
867 {
868 ADDR_E_RETURNCODE ret;
869 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
870 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
871
872 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
873 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
874
875 sin.flags = in->flags;
876 sin.resourceType = in->resourceType;
877 sin.format = in->format;
878 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
879 /* TODO: We could allow some of these: */
880 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
881 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
882 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
883 sin.bpp = in->bpp;
884 sin.width = in->width;
885 sin.height = in->height;
886 sin.numSlices = in->numSlices;
887 sin.numMipLevels = in->numMipLevels;
888 sin.numSamples = in->numSamples;
889 sin.numFrags = in->numFrags;
890
891 if (flags & RADEON_SURF_SCANOUT) {
892 sin.preferredSwSet.sw_D = 1;
893 /* Raven only allows S for displayable surfaces with < 64 bpp, so
894 * allow it as fallback */
895 sin.preferredSwSet.sw_S = 1;
896 } else if (in->flags.depth || in->flags.stencil || is_fmask)
897 sin.preferredSwSet.sw_Z = 1;
898 else
899 sin.preferredSwSet.sw_S = 1;
900
901 if (is_fmask) {
902 sin.flags.display = 0;
903 sin.flags.color = 0;
904 sin.flags.fmask = 1;
905 }
906
907 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
908 if (ret != ADDR_OK)
909 return ret;
910
911 *swizzle_mode = sout.swizzleMode;
912 return 0;
913 }
914
915 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
916 const struct ac_surf_config *config,
917 struct radeon_surf *surf, bool compressed,
918 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
919 {
920 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
921 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
922 ADDR_E_RETURNCODE ret;
923
924 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
925 out.pMipInfo = mip_info;
926
927 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
928 if (ret != ADDR_OK)
929 return ret;
930
931 if (in->flags.stencil) {
932 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
933 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
934 out.mipChainPitch - 1;
935 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
936 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
937 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
938 return 0;
939 }
940
941 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
942 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
943 out.mipChainPitch - 1;
944
945 /* CMASK fast clear uses these even if FMASK isn't allocated.
946 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
947 */
948 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
949 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
950
951 surf->u.gfx9.surf_slice_size = out.sliceSize;
952 surf->u.gfx9.surf_pitch = out.pitch;
953 surf->u.gfx9.surf_height = out.height;
954 surf->surf_size = out.surfSize;
955 surf->surf_alignment = out.baseAlign;
956
957 if (in->swizzleMode == ADDR_SW_LINEAR) {
958 for (unsigned i = 0; i < in->numMipLevels; i++)
959 surf->u.gfx9.offset[i] = mip_info[i].offset;
960 }
961
962 if (in->flags.depth) {
963 assert(in->swizzleMode != ADDR_SW_LINEAR);
964
965 /* HTILE */
966 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
967 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
968
969 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
970 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
971
972 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
973 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
974 hin.depthFlags = in->flags;
975 hin.swizzleMode = in->swizzleMode;
976 hin.unalignedWidth = in->width;
977 hin.unalignedHeight = in->height;
978 hin.numSlices = in->numSlices;
979 hin.numMipLevels = in->numMipLevels;
980
981 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
982 if (ret != ADDR_OK)
983 return ret;
984
985 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
986 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
987 surf->htile_size = hout.htileBytes;
988 surf->htile_slice_size = hout.sliceSize;
989 surf->htile_alignment = hout.baseAlign;
990 } else {
991 /* Compute tile swizzle for the color surface.
992 * All *_X and *_T modes can use the swizzle.
993 */
994 if (config->info.surf_index &&
995 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
996 !out.mipChainInTail &&
997 !(surf->flags & RADEON_SURF_SHAREABLE) &&
998 !in->flags.display) {
999 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1000 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1001
1002 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1003 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1004
1005 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1006 xin.flags = in->flags;
1007 xin.swizzleMode = in->swizzleMode;
1008 xin.resourceType = in->resourceType;
1009 xin.format = in->format;
1010 xin.numSamples = in->numSamples;
1011 xin.numFrags = in->numFrags;
1012
1013 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1014 if (ret != ADDR_OK)
1015 return ret;
1016
1017 assert(xout.pipeBankXor <=
1018 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1019 surf->tile_swizzle = xout.pipeBankXor;
1020 }
1021
1022 /* DCC */
1023 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1024 !compressed &&
1025 in->swizzleMode != ADDR_SW_LINEAR) {
1026 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1027 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1028 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1029
1030 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1031 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1032 dout.pMipInfo = meta_mip_info;
1033
1034 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1035 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1036 din.colorFlags = in->flags;
1037 din.resourceType = in->resourceType;
1038 din.swizzleMode = in->swizzleMode;
1039 din.bpp = in->bpp;
1040 din.unalignedWidth = in->width;
1041 din.unalignedHeight = in->height;
1042 din.numSlices = in->numSlices;
1043 din.numFrags = in->numFrags;
1044 din.numMipLevels = in->numMipLevels;
1045 din.dataSurfaceSize = out.surfSize;
1046
1047 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1048 if (ret != ADDR_OK)
1049 return ret;
1050
1051 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1052 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1053 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
1054 surf->dcc_size = dout.dccRamSize;
1055 surf->dcc_alignment = dout.dccRamBaseAlign;
1056 surf->num_dcc_levels = in->numMipLevels;
1057
1058 /* Disable DCC for levels that are in the mip tail.
1059 *
1060 * There are two issues that this is intended to
1061 * address:
1062 *
1063 * 1. Multiple mip levels may share a cache line. This
1064 * can lead to corruption when switching between
1065 * rendering to different mip levels because the
1066 * RBs don't maintain coherency.
1067 *
1068 * 2. Texturing with metadata after rendering sometimes
1069 * fails with corruption, probably for a similar
1070 * reason.
1071 *
1072 * Working around these issues for all levels in the
1073 * mip tail may be overly conservative, but it's what
1074 * Vulkan does.
1075 *
1076 * Alternative solutions that also work but are worse:
1077 * - Disable DCC entirely.
1078 * - Flush TC L2 after rendering.
1079 */
1080 for (unsigned i = 0; i < in->numMipLevels; i++) {
1081 if (meta_mip_info[i].inMiptail) {
1082 surf->num_dcc_levels = i;
1083 break;
1084 }
1085 }
1086
1087 if (!surf->num_dcc_levels)
1088 surf->dcc_size = 0;
1089 }
1090
1091 /* FMASK */
1092 if (in->numSamples > 1) {
1093 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1094 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1095
1096 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1097 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1098
1099 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1100 true, surf->flags,
1101 &fin.swizzleMode);
1102 if (ret != ADDR_OK)
1103 return ret;
1104
1105 fin.unalignedWidth = in->width;
1106 fin.unalignedHeight = in->height;
1107 fin.numSlices = in->numSlices;
1108 fin.numSamples = in->numSamples;
1109 fin.numFrags = in->numFrags;
1110
1111 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1112 if (ret != ADDR_OK)
1113 return ret;
1114
1115 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1116 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1117 surf->u.gfx9.fmask_size = fout.fmaskBytes;
1118 surf->u.gfx9.fmask_alignment = fout.baseAlign;
1119
1120 /* Compute tile swizzle for the FMASK surface. */
1121 if (config->info.fmask_surf_index &&
1122 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1123 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1124 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1125 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1126
1127 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1128 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1129
1130 /* This counter starts from 1 instead of 0. */
1131 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1132 xin.flags = in->flags;
1133 xin.swizzleMode = in->swizzleMode;
1134 xin.resourceType = in->resourceType;
1135 xin.format = in->format;
1136 xin.numSamples = in->numSamples;
1137 xin.numFrags = in->numFrags;
1138
1139 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1140 if (ret != ADDR_OK)
1141 return ret;
1142
1143 assert(xout.pipeBankXor <=
1144 u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
1145 surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
1146 }
1147 }
1148
1149 /* CMASK */
1150 if (in->swizzleMode != ADDR_SW_LINEAR) {
1151 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1152 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1153
1154 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1155 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1156
1157 if (in->numSamples > 1) {
1158 /* FMASK is always aligned. */
1159 cin.cMaskFlags.pipeAligned = 1;
1160 cin.cMaskFlags.rbAligned = 1;
1161 } else {
1162 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1163 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1164 }
1165 cin.colorFlags = in->flags;
1166 cin.resourceType = in->resourceType;
1167 cin.unalignedWidth = in->width;
1168 cin.unalignedHeight = in->height;
1169 cin.numSlices = in->numSlices;
1170
1171 if (in->numSamples > 1)
1172 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1173 else
1174 cin.swizzleMode = in->swizzleMode;
1175
1176 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1177 if (ret != ADDR_OK)
1178 return ret;
1179
1180 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1181 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1182 surf->u.gfx9.cmask_size = cout.cmaskBytes;
1183 surf->u.gfx9.cmask_alignment = cout.baseAlign;
1184 }
1185 }
1186
1187 return 0;
1188 }
1189
1190 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1191 const struct radeon_info *info,
1192 const struct ac_surf_config *config,
1193 enum radeon_surf_mode mode,
1194 struct radeon_surf *surf)
1195 {
1196 bool compressed;
1197 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1198 int r;
1199
1200 assert(!(surf->flags & RADEON_SURF_FMASK));
1201
1202 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1203
1204 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1205
1206 /* The format must be set correctly for the allocation of compressed
1207 * textures to work. In other cases, setting the bpp is sufficient. */
1208 if (compressed) {
1209 switch (surf->bpe) {
1210 case 8:
1211 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1212 break;
1213 case 16:
1214 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1215 break;
1216 default:
1217 assert(0);
1218 }
1219 } else {
1220 switch (surf->bpe) {
1221 case 1:
1222 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1223 AddrSurfInfoIn.format = ADDR_FMT_8;
1224 break;
1225 case 2:
1226 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1227 !(surf->flags & RADEON_SURF_SBUFFER));
1228 AddrSurfInfoIn.format = ADDR_FMT_16;
1229 break;
1230 case 4:
1231 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1232 !(surf->flags & RADEON_SURF_SBUFFER));
1233 AddrSurfInfoIn.format = ADDR_FMT_32;
1234 break;
1235 case 8:
1236 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1237 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1238 break;
1239 case 16:
1240 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1241 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1242 break;
1243 default:
1244 assert(0);
1245 }
1246 AddrSurfInfoIn.bpp = surf->bpe * 8;
1247 }
1248
1249 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1250 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1251 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1252 /* flags.texture currently refers to TC-compatible HTILE */
1253 AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1254 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1255 AddrSurfInfoIn.flags.opt4space = 1;
1256
1257 AddrSurfInfoIn.numMipLevels = config->info.levels;
1258 AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
1259 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1260
1261 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1262 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1263 * must sample 1D textures as 2D. */
1264 if (config->is_3d)
1265 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1266 else
1267 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1268
1269 AddrSurfInfoIn.width = config->info.width;
1270 AddrSurfInfoIn.height = config->info.height;
1271
1272 if (config->is_3d)
1273 AddrSurfInfoIn.numSlices = config->info.depth;
1274 else if (config->is_cube)
1275 AddrSurfInfoIn.numSlices = 6;
1276 else
1277 AddrSurfInfoIn.numSlices = config->info.array_size;
1278
1279 /* This is propagated to HTILE/DCC/CMASK. */
1280 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1281 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1282
1283 switch (mode) {
1284 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1285 assert(config->info.samples <= 1);
1286 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1287 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1288 break;
1289
1290 case RADEON_SURF_MODE_1D:
1291 case RADEON_SURF_MODE_2D:
1292 if (surf->flags & RADEON_SURF_IMPORTED) {
1293 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1294 break;
1295 }
1296
1297 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1298 false, surf->flags,
1299 &AddrSurfInfoIn.swizzleMode);
1300 if (r)
1301 return r;
1302 break;
1303
1304 default:
1305 assert(0);
1306 }
1307
1308 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1309 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1310
1311 surf->num_dcc_levels = 0;
1312 surf->surf_size = 0;
1313 surf->dcc_size = 0;
1314 surf->htile_size = 0;
1315 surf->htile_slice_size = 0;
1316 surf->u.gfx9.surf_offset = 0;
1317 surf->u.gfx9.stencil_offset = 0;
1318 surf->u.gfx9.fmask_size = 0;
1319 surf->u.gfx9.cmask_size = 0;
1320
1321 /* Calculate texture layout information. */
1322 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1323 &AddrSurfInfoIn);
1324 if (r)
1325 return r;
1326
1327 /* Calculate texture layout information for stencil. */
1328 if (surf->flags & RADEON_SURF_SBUFFER) {
1329 AddrSurfInfoIn.flags.stencil = 1;
1330 AddrSurfInfoIn.bpp = 8;
1331 AddrSurfInfoIn.format = ADDR_FMT_8;
1332
1333 if (!AddrSurfInfoIn.flags.depth) {
1334 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1335 false, surf->flags,
1336 &AddrSurfInfoIn.swizzleMode);
1337 if (r)
1338 return r;
1339 } else
1340 AddrSurfInfoIn.flags.depth = 0;
1341
1342 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1343 &AddrSurfInfoIn);
1344 if (r)
1345 return r;
1346 }
1347
1348 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1349
1350 /* Query whether the surface is displayable. */
1351 bool displayable = false;
1352 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1353 surf->bpe * 8, &displayable);
1354 if (r)
1355 return r;
1356 surf->is_displayable = displayable;
1357
1358 switch (surf->u.gfx9.surf.swizzle_mode) {
1359 /* S = standard. */
1360 case ADDR_SW_256B_S:
1361 case ADDR_SW_4KB_S:
1362 case ADDR_SW_64KB_S:
1363 case ADDR_SW_VAR_S:
1364 case ADDR_SW_64KB_S_T:
1365 case ADDR_SW_4KB_S_X:
1366 case ADDR_SW_64KB_S_X:
1367 case ADDR_SW_VAR_S_X:
1368 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1369 break;
1370
1371 /* D = display. */
1372 case ADDR_SW_LINEAR:
1373 case ADDR_SW_256B_D:
1374 case ADDR_SW_4KB_D:
1375 case ADDR_SW_64KB_D:
1376 case ADDR_SW_VAR_D:
1377 case ADDR_SW_64KB_D_T:
1378 case ADDR_SW_4KB_D_X:
1379 case ADDR_SW_64KB_D_X:
1380 case ADDR_SW_VAR_D_X:
1381 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1382 break;
1383
1384 /* R = rotated. */
1385 case ADDR_SW_256B_R:
1386 case ADDR_SW_4KB_R:
1387 case ADDR_SW_64KB_R:
1388 case ADDR_SW_VAR_R:
1389 case ADDR_SW_64KB_R_T:
1390 case ADDR_SW_4KB_R_X:
1391 case ADDR_SW_64KB_R_X:
1392 case ADDR_SW_VAR_R_X:
1393 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1394 break;
1395
1396 /* Z = depth. */
1397 case ADDR_SW_4KB_Z:
1398 case ADDR_SW_64KB_Z:
1399 case ADDR_SW_VAR_Z:
1400 case ADDR_SW_64KB_Z_T:
1401 case ADDR_SW_4KB_Z_X:
1402 case ADDR_SW_64KB_Z_X:
1403 case ADDR_SW_VAR_Z_X:
1404 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1405 break;
1406
1407 default:
1408 assert(0);
1409 }
1410
1411 /* Temporary workaround to prevent VM faults and hangs. */
1412 if (info->family == CHIP_VEGA12)
1413 surf->u.gfx9.fmask_size *= 8;
1414
1415 return 0;
1416 }
1417
1418 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1419 const struct ac_surf_config *config,
1420 enum radeon_surf_mode mode,
1421 struct radeon_surf *surf)
1422 {
1423 int r;
1424
1425 r = surf_config_sanity(config);
1426 if (r)
1427 return r;
1428
1429 if (info->chip_class >= GFX9)
1430 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1431 else
1432 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1433 }