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ac/surface: don't allocate FMASK if there is no graphics
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/inc/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
53 {
54 return malloc(pInput->sizeInBytes);
55 }
56
57 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
58 {
59 free(pInput->pVirtAddr);
60 return ADDR_OK;
61 }
62
63 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
64 const struct amdgpu_gpu_info *amdinfo,
65 uint64_t *max_alignment)
66 {
67 ADDR_CREATE_INPUT addrCreateInput = {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
69 ADDR_REGISTER_VALUE regValue = {0};
70 ADDR_CREATE_FLAGS createFlags = {{0}};
71 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
72 ADDR_E_RETURNCODE addrRet;
73
74 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
75 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
76
77 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
78 createFlags.value = 0;
79
80 addrCreateInput.chipFamily = info->family_id;
81 addrCreateInput.chipRevision = info->chip_external_rev;
82
83 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
84 return NULL;
85
86 if (addrCreateInput.chipFamily >= FAMILY_AI) {
87 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
88 regValue.blockVarSizeLog2 = 0;
89 } else {
90 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
91 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
92
93 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
94 regValue.pTileConfig = amdinfo->gb_tile_mode;
95 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
96 if (addrCreateInput.chipFamily == FAMILY_SI) {
97 regValue.pMacroTileConfig = NULL;
98 regValue.noOfMacroEntries = 0;
99 } else {
100 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
101 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
102 }
103
104 createFlags.useTileIndex = 1;
105 createFlags.useHtileSliceAlign = 1;
106
107 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
108 }
109
110 addrCreateInput.callbacks.allocSysMem = allocSysMem;
111 addrCreateInput.callbacks.freeSysMem = freeSysMem;
112 addrCreateInput.callbacks.debugPrint = 0;
113 addrCreateInput.createFlags = createFlags;
114 addrCreateInput.regValue = regValue;
115
116 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
117 if (addrRet != ADDR_OK)
118 return NULL;
119
120 if (max_alignment) {
121 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
122 if (addrRet == ADDR_OK){
123 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
124 }
125 }
126 return addrCreateOutput.hLib;
127 }
128
129 static int surf_config_sanity(const struct ac_surf_config *config,
130 unsigned flags)
131 {
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
134 */
135 assert(!(flags & RADEON_SURF_FMASK));
136 if (flags & RADEON_SURF_FMASK)
137 return -EINVAL;
138
139 /* all dimension must be at least 1 ! */
140 if (!config->info.width || !config->info.height || !config->info.depth ||
141 !config->info.array_size || !config->info.levels)
142 return -EINVAL;
143
144 switch (config->info.samples) {
145 case 0:
146 case 1:
147 case 2:
148 case 4:
149 case 8:
150 break;
151 case 16:
152 if (flags & RADEON_SURF_Z_OR_SBUFFER)
153 return -EINVAL;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
160 switch (config->info.storage_samples) {
161 case 0:
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 break;
167 default:
168 return -EINVAL;
169 }
170 }
171
172 if (config->is_3d && config->info.array_size > 1)
173 return -EINVAL;
174 if (config->is_cube && config->info.depth > 1)
175 return -EINVAL;
176
177 return 0;
178 }
179
180 static int gfx6_compute_level(ADDR_HANDLE addrlib,
181 const struct ac_surf_config *config,
182 struct radeon_surf *surf, bool is_stencil,
183 unsigned level, bool compressed,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
186 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
187 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
188 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
190 {
191 struct legacy_surf_level *surf_level;
192 ADDR_E_RETURNCODE ret;
193
194 AddrSurfInfoIn->mipLevel = level;
195 AddrSurfInfoIn->width = u_minify(config->info.width, level);
196 AddrSurfInfoIn->height = u_minify(config->info.height, level);
197
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
200 */
201 if (config->info.levels == 1 &&
202 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
203 AddrSurfInfoIn->bpp &&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
205 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
206
207 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
208 }
209
210 if (config->is_3d)
211 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
212 else if (config->is_cube)
213 AddrSurfInfoIn->numSlices = 6;
214 else
215 AddrSurfInfoIn->numSlices = config->info.array_size;
216
217 if (level > 0) {
218 /* Set the base level pitch. This is needed for calculation
219 * of non-zero levels. */
220 if (is_stencil)
221 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
222 else
223 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
224
225 /* Convert blocks to pixels for compressed formats. */
226 if (compressed)
227 AddrSurfInfoIn->basePitch *= surf->blk_w;
228 }
229
230 ret = AddrComputeSurfaceInfo(addrlib,
231 AddrSurfInfoIn,
232 AddrSurfInfoOut);
233 if (ret != ADDR_OK) {
234 return ret;
235 }
236
237 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
238 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
239 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
240 surf_level->nblk_x = AddrSurfInfoOut->pitch;
241 surf_level->nblk_y = AddrSurfInfoOut->height;
242
243 switch (AddrSurfInfoOut->tileMode) {
244 case ADDR_TM_LINEAR_ALIGNED:
245 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
246 break;
247 case ADDR_TM_1D_TILED_THIN1:
248 surf_level->mode = RADEON_SURF_MODE_1D;
249 break;
250 case ADDR_TM_2D_TILED_THIN1:
251 surf_level->mode = RADEON_SURF_MODE_2D;
252 break;
253 default:
254 assert(0);
255 }
256
257 if (is_stencil)
258 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
259 else
260 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
261
262 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
263
264 /* Clear DCC fields at the beginning. */
265 surf_level->dcc_offset = 0;
266
267 /* The previous level's flag tells us if we can use DCC for this level. */
268 if (AddrSurfInfoIn->flags.dccCompatible &&
269 (level == 0 || AddrDccOut->subLvlCompressible)) {
270 bool prev_level_clearable = level == 0 ||
271 AddrDccOut->dccRamSizeAligned;
272
273 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
274 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
275 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
276 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
277 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
278
279 ret = AddrComputeDccInfo(addrlib,
280 AddrDccIn,
281 AddrDccOut);
282
283 if (ret == ADDR_OK) {
284 surf_level->dcc_offset = surf->dcc_size;
285 surf->num_dcc_levels = level + 1;
286 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
287 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
288
289 /* If the DCC size of a subresource (1 mip level or 1 slice)
290 * is not aligned, the DCC memory layout is not contiguous for
291 * that subresource, which means we can't use fast clear.
292 *
293 * We only do fast clears for whole mipmap levels. If we did
294 * per-slice fast clears, the same restriction would apply.
295 * (i.e. only compute the slice size and see if it's aligned)
296 *
297 * The last level can be non-contiguous and still be clearable
298 * if it's interleaved with the next level that doesn't exist.
299 */
300 if (AddrDccOut->dccRamSizeAligned ||
301 (prev_level_clearable && level == config->info.levels - 1))
302 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
303 else
304 surf_level->dcc_fast_clear_size = 0;
305
306 /* Compute the DCC slice size because addrlib doesn't
307 * provide this info. As DCC memory is linear (each
308 * slice is the same size) it's easy to compute.
309 */
310 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
311
312 /* For arrays, we have to compute the DCC info again
313 * with one slice size to get a correct fast clear
314 * size.
315 */
316 if (config->info.array_size > 1) {
317 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
318 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
319 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
320 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
321 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
322
323 ret = AddrComputeDccInfo(addrlib,
324 AddrDccIn, AddrDccOut);
325 if (ret == ADDR_OK) {
326 /* If the DCC memory isn't properly
327 * aligned, the data are interleaved
328 * accross slices.
329 */
330 if (AddrDccOut->dccRamSizeAligned)
331 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
332 else
333 surf_level->dcc_slice_fast_clear_size = 0;
334 }
335 } else {
336 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
337 }
338 }
339 }
340
341 /* HTILE. */
342 if (!is_stencil &&
343 AddrSurfInfoIn->flags.depth &&
344 surf_level->mode == RADEON_SURF_MODE_2D &&
345 level == 0 &&
346 !(surf->flags & RADEON_SURF_NO_HTILE)) {
347 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
348 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
349 AddrHtileIn->height = AddrSurfInfoOut->height;
350 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
351 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
352 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
353 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
354 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
355 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
356
357 ret = AddrComputeHtileInfo(addrlib,
358 AddrHtileIn,
359 AddrHtileOut);
360
361 if (ret == ADDR_OK) {
362 surf->htile_size = AddrHtileOut->htileBytes;
363 surf->htile_slice_size = AddrHtileOut->sliceSize;
364 surf->htile_alignment = AddrHtileOut->baseAlign;
365 }
366 }
367
368 return 0;
369 }
370
371 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
372 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
373 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
374
375 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
376 const struct radeon_info *info)
377 {
378 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
379
380 if (info->chip_class >= GFX7)
381 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
382 else
383 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
384 }
385
386 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
387 {
388 unsigned index, tileb;
389
390 tileb = 8 * 8 * surf->bpe;
391 tileb = MIN2(surf->u.legacy.tile_split, tileb);
392
393 for (index = 0; tileb > 64; index++)
394 tileb >>= 1;
395
396 assert(index < 16);
397 return index;
398 }
399
400 static bool get_display_flag(const struct ac_surf_config *config,
401 const struct radeon_surf *surf)
402 {
403 unsigned num_channels = config->info.num_channels;
404 unsigned bpe = surf->bpe;
405
406 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
407 surf->flags & RADEON_SURF_SCANOUT &&
408 config->info.samples <= 1 &&
409 surf->blk_w <= 2 && surf->blk_h == 1) {
410 /* subsampled */
411 if (surf->blk_w == 2 && surf->blk_h == 1)
412 return true;
413
414 if (/* RGBA8 or RGBA16F */
415 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
416 /* R5G6B5 or R5G5B5A1 */
417 (bpe == 2 && num_channels >= 3) ||
418 /* C8 palette */
419 (bpe == 1 && num_channels == 1))
420 return true;
421 }
422 return false;
423 }
424
425 /**
426 * This must be called after the first level is computed.
427 *
428 * Copy surface-global settings like pipe/bank config from level 0 surface
429 * computation, and compute tile swizzle.
430 */
431 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
432 const struct radeon_info *info,
433 const struct ac_surf_config *config,
434 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
435 struct radeon_surf *surf)
436 {
437 surf->surf_alignment = csio->baseAlign;
438 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
439 gfx6_set_micro_tile_mode(surf, info);
440
441 /* For 2D modes only. */
442 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
443 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
444 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
445 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
446 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
447 surf->u.legacy.num_banks = csio->pTileInfo->banks;
448 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
449 } else {
450 surf->u.legacy.macro_tile_index = 0;
451 }
452
453 /* Compute tile swizzle. */
454 /* TODO: fix tile swizzle with mipmapping for GFX6 */
455 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
456 config->info.surf_index &&
457 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
458 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
459 !get_display_flag(config, surf)) {
460 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
461 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
462
463 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
464 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
465
466 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
467 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
468 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
469 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
470 AddrBaseSwizzleIn.tileMode = csio->tileMode;
471
472 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
473 &AddrBaseSwizzleOut);
474 if (r != ADDR_OK)
475 return r;
476
477 assert(AddrBaseSwizzleOut.tileSwizzle <=
478 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
479 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
480 }
481 return 0;
482 }
483
484 static void ac_compute_cmask(const struct radeon_info *info,
485 const struct ac_surf_config *config,
486 struct radeon_surf *surf)
487 {
488 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
489 unsigned num_pipes = info->num_tile_pipes;
490 unsigned cl_width, cl_height;
491
492 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
493 (config->info.samples >= 2 && !surf->fmask_size))
494 return;
495
496 assert(info->chip_class <= GFX8);
497
498 switch (num_pipes) {
499 case 2:
500 cl_width = 32;
501 cl_height = 16;
502 break;
503 case 4:
504 cl_width = 32;
505 cl_height = 32;
506 break;
507 case 8:
508 cl_width = 64;
509 cl_height = 32;
510 break;
511 case 16: /* Hawaii */
512 cl_width = 64;
513 cl_height = 64;
514 break;
515 default:
516 assert(0);
517 return;
518 }
519
520 unsigned base_align = num_pipes * pipe_interleave_bytes;
521
522 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
523 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
524 unsigned slice_elements = (width * height) / (8*8);
525
526 /* Each element of CMASK is a nibble. */
527 unsigned slice_bytes = slice_elements / 2;
528
529 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
530 if (surf->u.legacy.cmask_slice_tile_max)
531 surf->u.legacy.cmask_slice_tile_max -= 1;
532
533 unsigned num_layers;
534 if (config->is_3d)
535 num_layers = config->info.depth;
536 else if (config->is_cube)
537 num_layers = 6;
538 else
539 num_layers = config->info.array_size;
540
541 surf->cmask_alignment = MAX2(256, base_align);
542 surf->cmask_slice_size = align(slice_bytes, base_align);
543 surf->cmask_size = surf->cmask_slice_size * num_layers;
544 }
545
546 /**
547 * Fill in the tiling information in \p surf based on the given surface config.
548 *
549 * The following fields of \p surf must be initialized by the caller:
550 * blk_w, blk_h, bpe, flags.
551 */
552 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
553 const struct radeon_info *info,
554 const struct ac_surf_config *config,
555 enum radeon_surf_mode mode,
556 struct radeon_surf *surf)
557 {
558 unsigned level;
559 bool compressed;
560 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
561 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
562 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
563 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
564 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
565 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
566 ADDR_TILEINFO AddrTileInfoIn = {0};
567 ADDR_TILEINFO AddrTileInfoOut = {0};
568 int r;
569
570 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
571 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
572 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
573 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
574 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
575 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
576 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
577
578 compressed = surf->blk_w == 4 && surf->blk_h == 4;
579
580 /* MSAA requires 2D tiling. */
581 if (config->info.samples > 1)
582 mode = RADEON_SURF_MODE_2D;
583
584 /* DB doesn't support linear layouts. */
585 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
586 mode < RADEON_SURF_MODE_1D)
587 mode = RADEON_SURF_MODE_1D;
588
589 /* Set the requested tiling mode. */
590 switch (mode) {
591 case RADEON_SURF_MODE_LINEAR_ALIGNED:
592 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
593 break;
594 case RADEON_SURF_MODE_1D:
595 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
596 break;
597 case RADEON_SURF_MODE_2D:
598 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
599 break;
600 default:
601 assert(0);
602 }
603
604 /* The format must be set correctly for the allocation of compressed
605 * textures to work. In other cases, setting the bpp is sufficient.
606 */
607 if (compressed) {
608 switch (surf->bpe) {
609 case 8:
610 AddrSurfInfoIn.format = ADDR_FMT_BC1;
611 break;
612 case 16:
613 AddrSurfInfoIn.format = ADDR_FMT_BC3;
614 break;
615 default:
616 assert(0);
617 }
618 }
619 else {
620 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
621 }
622
623 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
624 MAX2(1, config->info.samples);
625 AddrSurfInfoIn.tileIndex = -1;
626
627 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
628 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
629 MAX2(1, config->info.storage_samples);
630 }
631
632 /* Set the micro tile type. */
633 if (surf->flags & RADEON_SURF_SCANOUT)
634 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
635 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
636 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
637 else
638 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
639
640 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
641 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
642 AddrSurfInfoIn.flags.cube = config->is_cube;
643 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
644 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
645 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
646
647 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
648 * requested, because TC-compatible HTILE requires 2D tiling.
649 */
650 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
651 !AddrSurfInfoIn.flags.fmask &&
652 config->info.samples <= 1 &&
653 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
654
655 /* DCC notes:
656 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
657 * with samples >= 4.
658 * - Mipmapped array textures have low performance (discovered by a closed
659 * driver team).
660 */
661 AddrSurfInfoIn.flags.dccCompatible =
662 info->chip_class >= GFX8 &&
663 info->has_graphics && /* disable DCC on compute-only chips */
664 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
665 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
666 !compressed &&
667 ((config->info.array_size == 1 && config->info.depth == 1) ||
668 config->info.levels == 1);
669
670 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
671 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
672
673 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
674 * for Z and stencil. This can cause a number of problems which we work
675 * around here:
676 *
677 * - a depth part that is incompatible with mipmapped texturing
678 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
679 * incorrect tiling applied to the stencil part, stencil buffer
680 * memory accesses that go out of bounds) even without mipmapping
681 *
682 * Some piglit tests that are prone to different types of related
683 * failures:
684 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
685 * ./bin/framebuffer-blit-levels {draw,read} stencil
686 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
687 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
688 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
689 */
690 int stencil_tile_idx = -1;
691
692 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
693 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
694 /* Compute stencilTileIdx that is compatible with the (depth)
695 * tileIdx. This degrades the depth surface if necessary to
696 * ensure that a matching stencilTileIdx exists. */
697 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
698
699 /* Keep the depth mip-tail compatible with texturing. */
700 AddrSurfInfoIn.flags.noStencil = 1;
701 }
702
703 /* Set preferred macrotile parameters. This is usually required
704 * for shared resources. This is for 2D tiling only. */
705 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
706 surf->u.legacy.bankw && surf->u.legacy.bankh &&
707 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
708 /* If any of these parameters are incorrect, the calculation
709 * will fail. */
710 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
711 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
712 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
713 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
714 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
715 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
716 AddrSurfInfoIn.flags.opt4Space = 0;
717 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
718
719 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
720 * the tile index, because we are expected to know it if
721 * we know the other parameters.
722 *
723 * This is something that can easily be fixed in Addrlib.
724 * For now, just figure it out here.
725 * Note that only 2D_TILE_THIN1 is handled here.
726 */
727 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
728 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
729
730 if (info->chip_class == GFX6) {
731 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
732 if (surf->bpe == 2)
733 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
734 else
735 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
736 } else {
737 if (surf->bpe == 1)
738 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
739 else if (surf->bpe == 2)
740 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
741 else if (surf->bpe == 4)
742 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
743 else
744 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
745 }
746 } else {
747 /* GFX7 - GFX8 */
748 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
749 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
750 else
751 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
752
753 /* Addrlib doesn't set this if tileIndex is forced like above. */
754 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
755 }
756 }
757
758 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
759 surf->num_dcc_levels = 0;
760 surf->surf_size = 0;
761 surf->dcc_size = 0;
762 surf->dcc_alignment = 1;
763 surf->htile_size = 0;
764 surf->htile_slice_size = 0;
765 surf->htile_alignment = 1;
766
767 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
768 !(surf->flags & RADEON_SURF_ZBUFFER);
769
770 /* Calculate texture layout information. */
771 if (!only_stencil) {
772 for (level = 0; level < config->info.levels; level++) {
773 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
774 &AddrSurfInfoIn, &AddrSurfInfoOut,
775 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
776 if (r)
777 return r;
778
779 if (level > 0)
780 continue;
781
782 /* Check that we actually got a TC-compatible HTILE if
783 * we requested it (only for level 0, since we're not
784 * supporting HTILE on higher mip levels anyway). */
785 assert(AddrSurfInfoOut.tcCompatible ||
786 !AddrSurfInfoIn.flags.tcCompatible ||
787 AddrSurfInfoIn.flags.matchStencilTileCfg);
788
789 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
790 if (!AddrSurfInfoOut.tcCompatible) {
791 AddrSurfInfoIn.flags.tcCompatible = 0;
792 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
793 }
794
795 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
796 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
797 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
798
799 assert(stencil_tile_idx >= 0);
800 }
801
802 r = gfx6_surface_settings(addrlib, info, config,
803 &AddrSurfInfoOut, surf);
804 if (r)
805 return r;
806 }
807 }
808
809 /* Calculate texture layout information for stencil. */
810 if (surf->flags & RADEON_SURF_SBUFFER) {
811 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
812 AddrSurfInfoIn.bpp = 8;
813 AddrSurfInfoIn.flags.depth = 0;
814 AddrSurfInfoIn.flags.stencil = 1;
815 AddrSurfInfoIn.flags.tcCompatible = 0;
816 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
817 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
818
819 for (level = 0; level < config->info.levels; level++) {
820 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
821 &AddrSurfInfoIn, &AddrSurfInfoOut,
822 &AddrDccIn, &AddrDccOut,
823 NULL, NULL);
824 if (r)
825 return r;
826
827 /* DB uses the depth pitch for both stencil and depth. */
828 if (!only_stencil) {
829 if (surf->u.legacy.stencil_level[level].nblk_x !=
830 surf->u.legacy.level[level].nblk_x)
831 surf->u.legacy.stencil_adjusted = true;
832 } else {
833 surf->u.legacy.level[level].nblk_x =
834 surf->u.legacy.stencil_level[level].nblk_x;
835 }
836
837 if (level == 0) {
838 if (only_stencil) {
839 r = gfx6_surface_settings(addrlib, info, config,
840 &AddrSurfInfoOut, surf);
841 if (r)
842 return r;
843 }
844
845 /* For 2D modes only. */
846 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
847 surf->u.legacy.stencil_tile_split =
848 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
849 }
850 }
851 }
852 }
853
854 /* Compute FMASK. */
855 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
856 info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
857 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
858 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
859 ADDR_TILEINFO fmask_tile_info = {};
860
861 fin.size = sizeof(fin);
862 fout.size = sizeof(fout);
863
864 fin.tileMode = AddrSurfInfoOut.tileMode;
865 fin.pitch = AddrSurfInfoOut.pitch;
866 fin.height = config->info.height;
867 fin.numSlices = AddrSurfInfoIn.numSlices;
868 fin.numSamples = AddrSurfInfoIn.numSamples;
869 fin.numFrags = AddrSurfInfoIn.numFrags;
870 fin.tileIndex = -1;
871 fout.pTileInfo = &fmask_tile_info;
872
873 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
874 if (r)
875 return r;
876
877 surf->fmask_size = fout.fmaskBytes;
878 surf->fmask_alignment = fout.baseAlign;
879 surf->fmask_tile_swizzle = 0;
880
881 surf->u.legacy.fmask.slice_tile_max =
882 (fout.pitch * fout.height) / 64;
883 if (surf->u.legacy.fmask.slice_tile_max)
884 surf->u.legacy.fmask.slice_tile_max -= 1;
885
886 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
887 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
888 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
889 surf->u.legacy.fmask.slice_size = fout.sliceSize;
890
891 /* Compute tile swizzle for FMASK. */
892 if (config->info.fmask_surf_index &&
893 !(surf->flags & RADEON_SURF_SHAREABLE)) {
894 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
895 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
896
897 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
898 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
899
900 /* This counter starts from 1 instead of 0. */
901 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
902 xin.tileIndex = fout.tileIndex;
903 xin.macroModeIndex = fout.macroModeIndex;
904 xin.pTileInfo = fout.pTileInfo;
905 xin.tileMode = fin.tileMode;
906
907 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
908 if (r != ADDR_OK)
909 return r;
910
911 assert(xout.tileSwizzle <=
912 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
913 surf->fmask_tile_swizzle = xout.tileSwizzle;
914 }
915 }
916
917 /* Recalculate the whole DCC miptree size including disabled levels.
918 * This is what addrlib does, but calling addrlib would be a lot more
919 * complicated.
920 */
921 if (surf->dcc_size && config->info.levels > 1) {
922 /* The smallest miplevels that are never compressed by DCC
923 * still read the DCC buffer via TC if the base level uses DCC,
924 * and for some reason the DCC buffer needs to be larger if
925 * the miptree uses non-zero tile_swizzle. Otherwise there are
926 * VM faults.
927 *
928 * "dcc_alignment * 4" was determined by trial and error.
929 */
930 surf->dcc_size = align64(surf->surf_size >> 8,
931 surf->dcc_alignment * 4);
932 }
933
934 /* Make sure HTILE covers the whole miptree, because the shader reads
935 * TC-compatible HTILE even for levels where it's disabled by DB.
936 */
937 if (surf->htile_size && config->info.levels > 1 &&
938 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
939 /* MSAA can't occur with levels > 1, so ignore the sample count. */
940 const unsigned total_pixels = surf->surf_size / surf->bpe;
941 const unsigned htile_block_size = 8 * 8;
942 const unsigned htile_element_size = 4;
943
944 surf->htile_size = (total_pixels / htile_block_size) *
945 htile_element_size;
946 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
947 }
948
949 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
950 surf->is_displayable = surf->is_linear ||
951 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
952 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
953
954 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
955 * used at the same time. This case is not currently expected to occur
956 * because we don't use rotated. Enforce this restriction on all chips
957 * to facilitate testing.
958 */
959 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
960 assert(!"rotate micro tile mode is unsupported");
961 return ADDR_ERROR;
962 }
963
964 ac_compute_cmask(info, config, surf);
965 return 0;
966 }
967
968 /* This is only called when expecting a tiled layout. */
969 static int
970 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
971 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
972 bool is_fmask, AddrSwizzleMode *swizzle_mode)
973 {
974 ADDR_E_RETURNCODE ret;
975 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
976 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
977
978 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
979 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
980
981 sin.flags = in->flags;
982 sin.resourceType = in->resourceType;
983 sin.format = in->format;
984 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
985 /* TODO: We could allow some of these: */
986 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
987 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
988 sin.bpp = in->bpp;
989 sin.width = in->width;
990 sin.height = in->height;
991 sin.numSlices = in->numSlices;
992 sin.numMipLevels = in->numMipLevels;
993 sin.numSamples = in->numSamples;
994 sin.numFrags = in->numFrags;
995
996 if (is_fmask) {
997 sin.flags.display = 0;
998 sin.flags.color = 0;
999 sin.flags.fmask = 1;
1000 }
1001
1002 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1003 if (ret != ADDR_OK)
1004 return ret;
1005
1006 *swizzle_mode = sout.swizzleMode;
1007 return 0;
1008 }
1009
1010 static bool gfx9_is_dcc_capable(const struct radeon_info *info, unsigned sw_mode)
1011 {
1012 if (info->chip_class >= GFX10)
1013 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1014
1015 return sw_mode != ADDR_SW_LINEAR;
1016 }
1017
1018 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1019 const struct radeon_info *info,
1020 const struct ac_surf_config *config,
1021 struct radeon_surf *surf, bool compressed,
1022 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1023 {
1024 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1025 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1026 ADDR_E_RETURNCODE ret;
1027
1028 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1029 out.pMipInfo = mip_info;
1030
1031 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1032 if (ret != ADDR_OK)
1033 return ret;
1034
1035 if (in->flags.stencil) {
1036 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1037 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1038 out.mipChainPitch - 1;
1039 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1040 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1041 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1042 return 0;
1043 }
1044
1045 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1046 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1047 out.mipChainPitch - 1;
1048
1049 /* CMASK fast clear uses these even if FMASK isn't allocated.
1050 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1051 */
1052 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1053 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1054
1055 surf->u.gfx9.surf_slice_size = out.sliceSize;
1056 surf->u.gfx9.surf_pitch = out.pitch;
1057 surf->u.gfx9.surf_height = out.height;
1058 surf->surf_size = out.surfSize;
1059 surf->surf_alignment = out.baseAlign;
1060
1061 if (in->swizzleMode == ADDR_SW_LINEAR) {
1062 for (unsigned i = 0; i < in->numMipLevels; i++)
1063 surf->u.gfx9.offset[i] = mip_info[i].offset;
1064 }
1065
1066 if (in->flags.depth) {
1067 assert(in->swizzleMode != ADDR_SW_LINEAR);
1068
1069 if (surf->flags & RADEON_SURF_NO_HTILE)
1070 return 0;
1071
1072 /* HTILE */
1073 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1074 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1075
1076 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1077 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1078
1079 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1080 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1081 hin.depthFlags = in->flags;
1082 hin.swizzleMode = in->swizzleMode;
1083 hin.unalignedWidth = in->width;
1084 hin.unalignedHeight = in->height;
1085 hin.numSlices = in->numSlices;
1086 hin.numMipLevels = in->numMipLevels;
1087 hin.firstMipIdInTail = out.firstMipIdInTail;
1088
1089 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1090 if (ret != ADDR_OK)
1091 return ret;
1092
1093 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1094 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1095 surf->htile_size = hout.htileBytes;
1096 surf->htile_slice_size = hout.sliceSize;
1097 surf->htile_alignment = hout.baseAlign;
1098 return 0;
1099 }
1100
1101 {
1102 /* Compute tile swizzle for the color surface.
1103 * All *_X and *_T modes can use the swizzle.
1104 */
1105 if (config->info.surf_index &&
1106 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1107 !out.mipChainInTail &&
1108 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1109 !in->flags.display) {
1110 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1111 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1112
1113 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1114 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1115
1116 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1117 xin.flags = in->flags;
1118 xin.swizzleMode = in->swizzleMode;
1119 xin.resourceType = in->resourceType;
1120 xin.format = in->format;
1121 xin.numSamples = in->numSamples;
1122 xin.numFrags = in->numFrags;
1123
1124 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1125 if (ret != ADDR_OK)
1126 return ret;
1127
1128 assert(xout.pipeBankXor <=
1129 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1130 surf->tile_swizzle = xout.pipeBankXor;
1131 }
1132
1133 /* DCC */
1134 if (info->has_graphics &&
1135 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1136 !compressed &&
1137 gfx9_is_dcc_capable(info, in->swizzleMode)) {
1138 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1139 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1140 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1141
1142 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1143 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1144 dout.pMipInfo = meta_mip_info;
1145
1146 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1147 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1148 din.colorFlags = in->flags;
1149 din.resourceType = in->resourceType;
1150 din.swizzleMode = in->swizzleMode;
1151 din.bpp = in->bpp;
1152 din.unalignedWidth = in->width;
1153 din.unalignedHeight = in->height;
1154 din.numSlices = in->numSlices;
1155 din.numFrags = in->numFrags;
1156 din.numMipLevels = in->numMipLevels;
1157 din.dataSurfaceSize = out.surfSize;
1158 din.firstMipIdInTail = out.firstMipIdInTail;
1159
1160 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1161 if (ret != ADDR_OK)
1162 return ret;
1163
1164 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1165 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1166 surf->dcc_size = dout.dccRamSize;
1167 surf->dcc_alignment = dout.dccRamBaseAlign;
1168 surf->num_dcc_levels = in->numMipLevels;
1169
1170 /* Disable DCC for levels that are in the mip tail.
1171 *
1172 * There are two issues that this is intended to
1173 * address:
1174 *
1175 * 1. Multiple mip levels may share a cache line. This
1176 * can lead to corruption when switching between
1177 * rendering to different mip levels because the
1178 * RBs don't maintain coherency.
1179 *
1180 * 2. Texturing with metadata after rendering sometimes
1181 * fails with corruption, probably for a similar
1182 * reason.
1183 *
1184 * Working around these issues for all levels in the
1185 * mip tail may be overly conservative, but it's what
1186 * Vulkan does.
1187 *
1188 * Alternative solutions that also work but are worse:
1189 * - Disable DCC entirely.
1190 * - Flush TC L2 after rendering.
1191 */
1192 for (unsigned i = 0; i < in->numMipLevels; i++) {
1193 if (meta_mip_info[i].inMiptail) {
1194 surf->num_dcc_levels = i;
1195 break;
1196 }
1197 }
1198
1199 if (!surf->num_dcc_levels)
1200 surf->dcc_size = 0;
1201
1202 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1203 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1204 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1205
1206 /* Compute displayable DCC. */
1207 if (in->flags.display &&
1208 surf->num_dcc_levels &&
1209 info->use_display_dcc_with_retile_blit) {
1210 /* Compute displayable DCC info. */
1211 din.dccKeyFlags.pipeAligned = 0;
1212 din.dccKeyFlags.rbAligned = 0;
1213
1214 assert(din.numSlices == 1);
1215 assert(din.numMipLevels == 1);
1216 assert(din.numFrags == 1);
1217 assert(surf->tile_swizzle == 0);
1218 assert(surf->u.gfx9.dcc.pipe_aligned ||
1219 surf->u.gfx9.dcc.rb_aligned);
1220
1221 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1222 if (ret != ADDR_OK)
1223 return ret;
1224
1225 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1226 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1227 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1228 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1229
1230 /* Compute address mapping from non-displayable to displayable DCC. */
1231 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1232 addrin.size = sizeof(addrin);
1233 addrin.colorFlags.color = 1;
1234 addrin.swizzleMode = din.swizzleMode;
1235 addrin.resourceType = din.resourceType;
1236 addrin.bpp = din.bpp;
1237 addrin.unalignedWidth = din.unalignedWidth;
1238 addrin.unalignedHeight = din.unalignedHeight;
1239 addrin.numSlices = 1;
1240 addrin.numMipLevels = 1;
1241 addrin.numFrags = 1;
1242
1243 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1244 addrout.size = sizeof(addrout);
1245
1246 surf->u.gfx9.dcc_retile_num_elements =
1247 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1248 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1249 /* Align the size to 4 (for the compute shader). */
1250 surf->u.gfx9.dcc_retile_num_elements =
1251 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1252
1253 surf->u.gfx9.dcc_retile_map =
1254 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1255 if (!surf->u.gfx9.dcc_retile_map)
1256 return ADDR_OUTOFMEMORY;
1257
1258 unsigned index = 0;
1259 surf->u.gfx9.dcc_retile_use_uint16 = true;
1260
1261 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1262 addrin.y = y;
1263
1264 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1265 addrin.x = x;
1266
1267 /* Compute src DCC address */
1268 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1269 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1270 addrout.addr = 0;
1271
1272 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1273 if (ret != ADDR_OK)
1274 return ret;
1275
1276 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1277 if (addrout.addr > UINT16_MAX)
1278 surf->u.gfx9.dcc_retile_use_uint16 = false;
1279
1280 /* Compute dst DCC address */
1281 addrin.dccKeyFlags.pipeAligned = 0;
1282 addrin.dccKeyFlags.rbAligned = 0;
1283 addrout.addr = 0;
1284
1285 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1286 if (ret != ADDR_OK)
1287 return ret;
1288
1289 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1290 if (addrout.addr > UINT16_MAX)
1291 surf->u.gfx9.dcc_retile_use_uint16 = false;
1292
1293 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1294 index++;
1295 }
1296 }
1297 /* Fill the remaining pairs with the last one (for the compute shader). */
1298 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1299 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1300 }
1301 }
1302
1303 /* FMASK */
1304 if (in->numSamples > 1 && info->has_graphics &&
1305 !(surf->flags & RADEON_SURF_NO_FMASK)) {
1306 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1307 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1308
1309 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1310 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1311
1312 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1313 true, &fin.swizzleMode);
1314 if (ret != ADDR_OK)
1315 return ret;
1316
1317 fin.unalignedWidth = in->width;
1318 fin.unalignedHeight = in->height;
1319 fin.numSlices = in->numSlices;
1320 fin.numSamples = in->numSamples;
1321 fin.numFrags = in->numFrags;
1322
1323 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1324 if (ret != ADDR_OK)
1325 return ret;
1326
1327 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1328 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1329 surf->fmask_size = fout.fmaskBytes;
1330 surf->fmask_alignment = fout.baseAlign;
1331
1332 /* Compute tile swizzle for the FMASK surface. */
1333 if (config->info.fmask_surf_index &&
1334 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1335 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1336 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1337 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1338
1339 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1340 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1341
1342 /* This counter starts from 1 instead of 0. */
1343 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1344 xin.flags = in->flags;
1345 xin.swizzleMode = fin.swizzleMode;
1346 xin.resourceType = in->resourceType;
1347 xin.format = in->format;
1348 xin.numSamples = in->numSamples;
1349 xin.numFrags = in->numFrags;
1350
1351 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1352 if (ret != ADDR_OK)
1353 return ret;
1354
1355 assert(xout.pipeBankXor <=
1356 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1357 surf->fmask_tile_swizzle = xout.pipeBankXor;
1358 }
1359 }
1360
1361 /* CMASK -- on GFX10 only for FMASK */
1362 if (in->swizzleMode != ADDR_SW_LINEAR &&
1363 ((info->chip_class <= GFX9 && in->numSamples == 1) ||
1364 (surf->fmask_size && in->numSamples >= 2))) {
1365 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1366 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1367
1368 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1369 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1370
1371 if (in->numSamples > 1) {
1372 /* FMASK is always aligned. */
1373 cin.cMaskFlags.pipeAligned = 1;
1374 cin.cMaskFlags.rbAligned = 1;
1375 } else {
1376 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1377 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1378 }
1379 cin.colorFlags = in->flags;
1380 cin.resourceType = in->resourceType;
1381 cin.unalignedWidth = in->width;
1382 cin.unalignedHeight = in->height;
1383 cin.numSlices = in->numSlices;
1384
1385 if (in->numSamples > 1)
1386 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1387 else
1388 cin.swizzleMode = in->swizzleMode;
1389
1390 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1391 if (ret != ADDR_OK)
1392 return ret;
1393
1394 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1395 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1396 surf->cmask_size = cout.cmaskBytes;
1397 surf->cmask_alignment = cout.baseAlign;
1398 }
1399 }
1400
1401 return 0;
1402 }
1403
1404 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1405 const struct radeon_info *info,
1406 const struct ac_surf_config *config,
1407 enum radeon_surf_mode mode,
1408 struct radeon_surf *surf)
1409 {
1410 bool compressed;
1411 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1412 int r;
1413
1414 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1415
1416 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1417
1418 /* The format must be set correctly for the allocation of compressed
1419 * textures to work. In other cases, setting the bpp is sufficient. */
1420 if (compressed) {
1421 switch (surf->bpe) {
1422 case 8:
1423 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1424 break;
1425 case 16:
1426 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1427 break;
1428 default:
1429 assert(0);
1430 }
1431 } else {
1432 switch (surf->bpe) {
1433 case 1:
1434 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1435 AddrSurfInfoIn.format = ADDR_FMT_8;
1436 break;
1437 case 2:
1438 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1439 !(surf->flags & RADEON_SURF_SBUFFER));
1440 AddrSurfInfoIn.format = ADDR_FMT_16;
1441 break;
1442 case 4:
1443 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1444 !(surf->flags & RADEON_SURF_SBUFFER));
1445 AddrSurfInfoIn.format = ADDR_FMT_32;
1446 break;
1447 case 8:
1448 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1449 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1450 break;
1451 case 12:
1452 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1453 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1454 break;
1455 case 16:
1456 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1457 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1458 break;
1459 default:
1460 assert(0);
1461 }
1462 AddrSurfInfoIn.bpp = surf->bpe * 8;
1463 }
1464
1465 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1466 AddrSurfInfoIn.flags.color = is_color_surface &&
1467 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1468 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1469 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1470 /* flags.texture currently refers to TC-compatible HTILE */
1471 AddrSurfInfoIn.flags.texture = is_color_surface ||
1472 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1473 AddrSurfInfoIn.flags.opt4space = 1;
1474
1475 AddrSurfInfoIn.numMipLevels = config->info.levels;
1476 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1477 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1478
1479 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1480 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1481
1482 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1483 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1484 * must sample 1D textures as 2D. */
1485 if (config->is_3d)
1486 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1487 else if (info->chip_class != GFX9 && config->is_1d)
1488 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
1489 else
1490 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1491
1492 AddrSurfInfoIn.width = config->info.width;
1493 AddrSurfInfoIn.height = config->info.height;
1494
1495 if (config->is_3d)
1496 AddrSurfInfoIn.numSlices = config->info.depth;
1497 else if (config->is_cube)
1498 AddrSurfInfoIn.numSlices = 6;
1499 else
1500 AddrSurfInfoIn.numSlices = config->info.array_size;
1501
1502 /* This is propagated to HTILE/DCC/CMASK. */
1503 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1504 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1505
1506 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1507 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1508 *
1509 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1510 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1511 * after rendering, so PIPE_ALIGNED=1 is recommended.
1512 */
1513 if (info->use_display_dcc_unaligned && is_color_surface &&
1514 AddrSurfInfoIn.flags.display) {
1515 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1516 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1517 }
1518
1519 switch (mode) {
1520 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1521 assert(config->info.samples <= 1);
1522 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1523 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1524 break;
1525
1526 case RADEON_SURF_MODE_1D:
1527 case RADEON_SURF_MODE_2D:
1528 if (surf->flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FORCE_SWIZZLE_MODE)) {
1529 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1530 break;
1531 }
1532
1533 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1534 false, &AddrSurfInfoIn.swizzleMode);
1535 if (r)
1536 return r;
1537 break;
1538
1539 default:
1540 assert(0);
1541 }
1542
1543 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1544 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1545
1546 surf->num_dcc_levels = 0;
1547 surf->surf_size = 0;
1548 surf->fmask_size = 0;
1549 surf->dcc_size = 0;
1550 surf->htile_size = 0;
1551 surf->htile_slice_size = 0;
1552 surf->u.gfx9.surf_offset = 0;
1553 surf->u.gfx9.stencil_offset = 0;
1554 surf->cmask_size = 0;
1555 surf->u.gfx9.dcc_retile_use_uint16 = false;
1556 surf->u.gfx9.dcc_retile_num_elements = 0;
1557 surf->u.gfx9.dcc_retile_map = NULL;
1558
1559 /* Calculate texture layout information. */
1560 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1561 &AddrSurfInfoIn);
1562 if (r)
1563 goto error;
1564
1565 /* Calculate texture layout information for stencil. */
1566 if (surf->flags & RADEON_SURF_SBUFFER) {
1567 AddrSurfInfoIn.flags.stencil = 1;
1568 AddrSurfInfoIn.bpp = 8;
1569 AddrSurfInfoIn.format = ADDR_FMT_8;
1570
1571 if (!AddrSurfInfoIn.flags.depth) {
1572 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1573 false, &AddrSurfInfoIn.swizzleMode);
1574 if (r)
1575 goto error;
1576 } else
1577 AddrSurfInfoIn.flags.depth = 0;
1578
1579 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1580 &AddrSurfInfoIn);
1581 if (r)
1582 goto error;
1583 }
1584
1585 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1586
1587 /* Query whether the surface is displayable. */
1588 bool displayable = false;
1589 if (!config->is_3d && !config->is_cube) {
1590 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1591 surf->bpe * 8, &displayable);
1592 if (r)
1593 goto error;
1594
1595 /* Display needs unaligned DCC. */
1596 if (info->use_display_dcc_unaligned &&
1597 surf->num_dcc_levels &&
1598 (surf->u.gfx9.dcc.pipe_aligned ||
1599 surf->u.gfx9.dcc.rb_aligned))
1600 displayable = false;
1601 }
1602 surf->is_displayable = displayable;
1603
1604 switch (surf->u.gfx9.surf.swizzle_mode) {
1605 /* S = standard. */
1606 case ADDR_SW_256B_S:
1607 case ADDR_SW_4KB_S:
1608 case ADDR_SW_64KB_S:
1609 case ADDR_SW_VAR_S:
1610 case ADDR_SW_64KB_S_T:
1611 case ADDR_SW_4KB_S_X:
1612 case ADDR_SW_64KB_S_X:
1613 case ADDR_SW_VAR_S_X:
1614 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1615 break;
1616
1617 /* D = display. */
1618 case ADDR_SW_LINEAR:
1619 case ADDR_SW_256B_D:
1620 case ADDR_SW_4KB_D:
1621 case ADDR_SW_64KB_D:
1622 case ADDR_SW_VAR_D:
1623 case ADDR_SW_64KB_D_T:
1624 case ADDR_SW_4KB_D_X:
1625 case ADDR_SW_64KB_D_X:
1626 case ADDR_SW_VAR_D_X:
1627 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1628 break;
1629
1630 /* R = rotated (gfx9), render target (gfx10). */
1631 case ADDR_SW_256B_R:
1632 case ADDR_SW_4KB_R:
1633 case ADDR_SW_64KB_R:
1634 case ADDR_SW_VAR_R:
1635 case ADDR_SW_64KB_R_T:
1636 case ADDR_SW_4KB_R_X:
1637 case ADDR_SW_64KB_R_X:
1638 case ADDR_SW_VAR_R_X:
1639 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1640 * used at the same time. We currently do not use rotated
1641 * in gfx9.
1642 */
1643 assert(info->chip_class >= GFX10 ||
1644 !"rotate micro tile mode is unsupported");
1645 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1646 break;
1647
1648 /* Z = depth. */
1649 case ADDR_SW_4KB_Z:
1650 case ADDR_SW_64KB_Z:
1651 case ADDR_SW_VAR_Z:
1652 case ADDR_SW_64KB_Z_T:
1653 case ADDR_SW_4KB_Z_X:
1654 case ADDR_SW_64KB_Z_X:
1655 case ADDR_SW_VAR_Z_X:
1656 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1657 break;
1658
1659 default:
1660 assert(0);
1661 }
1662
1663 return 0;
1664
1665 error:
1666 free(surf->u.gfx9.dcc_retile_map);
1667 surf->u.gfx9.dcc_retile_map = NULL;
1668 return r;
1669 }
1670
1671 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1672 const struct ac_surf_config *config,
1673 enum radeon_surf_mode mode,
1674 struct radeon_surf *surf)
1675 {
1676 int r;
1677
1678 r = surf_config_sanity(config, surf->flags);
1679 if (r)
1680 return r;
1681
1682 if (info->chip_class >= GFX9)
1683 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
1684 else
1685 r = gfx6_compute_surface(addrlib, info, config, mode, surf);
1686
1687 if (r)
1688 return r;
1689
1690 /* Determine the memory layout of multiple allocations in one buffer. */
1691 surf->total_size = surf->surf_size;
1692
1693 if (surf->htile_size) {
1694 surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
1695 surf->total_size = surf->htile_offset + surf->htile_size;
1696 }
1697
1698 if (surf->fmask_size) {
1699 assert(config->info.samples >= 2);
1700 surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
1701 surf->total_size = surf->fmask_offset + surf->fmask_size;
1702 }
1703
1704 /* Single-sample CMASK is in a separate buffer. */
1705 if (surf->cmask_size && config->info.samples >= 2) {
1706 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
1707 surf->total_size = surf->cmask_offset + surf->cmask_size;
1708 }
1709
1710 if (surf->dcc_size &&
1711 (info->use_display_dcc_unaligned ||
1712 info->use_display_dcc_with_retile_blit ||
1713 !(surf->flags & RADEON_SURF_SCANOUT))) {
1714 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
1715 surf->total_size = surf->dcc_offset + surf->dcc_size;
1716
1717 if (info->chip_class >= GFX9 &&
1718 surf->u.gfx9.dcc_retile_num_elements) {
1719 /* Add space for the displayable DCC buffer. */
1720 surf->display_dcc_offset =
1721 align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
1722 surf->total_size = surf->display_dcc_offset +
1723 surf->u.gfx9.display_dcc_size;
1724
1725 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1726 surf->dcc_retile_map_offset =
1727 align64(surf->total_size, info->tcc_cache_line_size);
1728
1729 if (surf->u.gfx9.dcc_retile_use_uint16) {
1730 surf->total_size = surf->dcc_retile_map_offset +
1731 surf->u.gfx9.dcc_retile_num_elements * 2;
1732 } else {
1733 surf->total_size = surf->dcc_retile_map_offset +
1734 surf->u.gfx9.dcc_retile_num_elements * 4;
1735 }
1736 }
1737 }
1738
1739 return 0;
1740 }