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ac/surface: move cmask_size/alignment into radeon_surf
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static unsigned get_first(unsigned x, unsigned y)
53 {
54 return x;
55 }
56
57 static void addrlib_family_rev_id(enum radeon_family family,
58 unsigned *addrlib_family,
59 unsigned *addrlib_revid)
60 {
61 switch (family) {
62 case CHIP_TAHITI:
63 *addrlib_family = FAMILY_SI;
64 *addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
65 break;
66 case CHIP_PITCAIRN:
67 *addrlib_family = FAMILY_SI;
68 *addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
69 break;
70 case CHIP_VERDE:
71 *addrlib_family = FAMILY_SI;
72 *addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
73 break;
74 case CHIP_OLAND:
75 *addrlib_family = FAMILY_SI;
76 *addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
77 break;
78 case CHIP_HAINAN:
79 *addrlib_family = FAMILY_SI;
80 *addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
81 break;
82 case CHIP_BONAIRE:
83 *addrlib_family = FAMILY_CI;
84 *addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
85 break;
86 case CHIP_KAVERI:
87 *addrlib_family = FAMILY_KV;
88 *addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
89 break;
90 case CHIP_KABINI:
91 *addrlib_family = FAMILY_KV;
92 *addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
93 break;
94 case CHIP_HAWAII:
95 *addrlib_family = FAMILY_CI;
96 *addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
97 break;
98 case CHIP_MULLINS:
99 *addrlib_family = FAMILY_KV;
100 *addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE);
101 break;
102 case CHIP_TONGA:
103 *addrlib_family = FAMILY_VI;
104 *addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
105 break;
106 case CHIP_ICELAND:
107 *addrlib_family = FAMILY_VI;
108 *addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
109 break;
110 case CHIP_CARRIZO:
111 *addrlib_family = FAMILY_CZ;
112 *addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
113 break;
114 case CHIP_STONEY:
115 *addrlib_family = FAMILY_CZ;
116 *addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
117 break;
118 case CHIP_FIJI:
119 *addrlib_family = FAMILY_VI;
120 *addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
121 break;
122 case CHIP_POLARIS10:
123 *addrlib_family = FAMILY_VI;
124 *addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
125 break;
126 case CHIP_POLARIS11:
127 *addrlib_family = FAMILY_VI;
128 *addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
129 break;
130 case CHIP_POLARIS12:
131 *addrlib_family = FAMILY_VI;
132 *addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
133 break;
134 case CHIP_VEGAM:
135 *addrlib_family = FAMILY_VI;
136 *addrlib_revid = get_first(AMDGPU_VEGAM_RANGE);
137 break;
138 case CHIP_VEGA10:
139 *addrlib_family = FAMILY_AI;
140 *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
141 break;
142 case CHIP_VEGA12:
143 *addrlib_family = FAMILY_AI;
144 *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
145 break;
146 case CHIP_RAVEN:
147 *addrlib_family = FAMILY_RV;
148 *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
149 break;
150 default:
151 fprintf(stderr, "amdgpu: Unknown family.\n");
152 }
153 }
154
155 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
156 {
157 return malloc(pInput->sizeInBytes);
158 }
159
160 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
161 {
162 free(pInput->pVirtAddr);
163 return ADDR_OK;
164 }
165
166 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
167 const struct amdgpu_gpu_info *amdinfo,
168 uint64_t *max_alignment)
169 {
170 ADDR_CREATE_INPUT addrCreateInput = {0};
171 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
172 ADDR_REGISTER_VALUE regValue = {0};
173 ADDR_CREATE_FLAGS createFlags = {{0}};
174 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
175 ADDR_E_RETURNCODE addrRet;
176
177 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
178 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
179
180 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
181 createFlags.value = 0;
182
183 addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
184 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
185 return NULL;
186
187 if (addrCreateInput.chipFamily >= FAMILY_AI) {
188 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
189 regValue.blockVarSizeLog2 = 0;
190 } else {
191 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
192 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
193
194 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
195 regValue.pTileConfig = amdinfo->gb_tile_mode;
196 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
197 if (addrCreateInput.chipFamily == FAMILY_SI) {
198 regValue.pMacroTileConfig = NULL;
199 regValue.noOfMacroEntries = 0;
200 } else {
201 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
202 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
203 }
204
205 createFlags.useTileIndex = 1;
206 createFlags.useHtileSliceAlign = 1;
207
208 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
209 }
210
211 addrCreateInput.callbacks.allocSysMem = allocSysMem;
212 addrCreateInput.callbacks.freeSysMem = freeSysMem;
213 addrCreateInput.callbacks.debugPrint = 0;
214 addrCreateInput.createFlags = createFlags;
215 addrCreateInput.regValue = regValue;
216
217 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
218 if (addrRet != ADDR_OK)
219 return NULL;
220
221 if (max_alignment) {
222 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
223 if (addrRet == ADDR_OK){
224 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
225 }
226 }
227 return addrCreateOutput.hLib;
228 }
229
230 static int surf_config_sanity(const struct ac_surf_config *config,
231 unsigned flags)
232 {
233 /* FMASK is allocated together with the color surface and can't be
234 * allocated separately.
235 */
236 assert(!(flags & RADEON_SURF_FMASK));
237 if (flags & RADEON_SURF_FMASK)
238 return -EINVAL;
239
240 /* all dimension must be at least 1 ! */
241 if (!config->info.width || !config->info.height || !config->info.depth ||
242 !config->info.array_size || !config->info.levels)
243 return -EINVAL;
244
245 switch (config->info.samples) {
246 case 0:
247 case 1:
248 case 2:
249 case 4:
250 case 8:
251 break;
252 case 16:
253 if (flags & RADEON_SURF_Z_OR_SBUFFER)
254 return -EINVAL;
255 break;
256 default:
257 return -EINVAL;
258 }
259
260 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
261 switch (config->info.color_samples) {
262 case 0:
263 case 1:
264 case 2:
265 case 4:
266 case 8:
267 break;
268 default:
269 return -EINVAL;
270 }
271 }
272
273 if (config->is_3d && config->info.array_size > 1)
274 return -EINVAL;
275 if (config->is_cube && config->info.depth > 1)
276 return -EINVAL;
277
278 return 0;
279 }
280
281 static int gfx6_compute_level(ADDR_HANDLE addrlib,
282 const struct ac_surf_config *config,
283 struct radeon_surf *surf, bool is_stencil,
284 unsigned level, bool compressed,
285 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
286 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
287 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
288 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
289 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
290 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
291 {
292 struct legacy_surf_level *surf_level;
293 ADDR_E_RETURNCODE ret;
294
295 AddrSurfInfoIn->mipLevel = level;
296 AddrSurfInfoIn->width = u_minify(config->info.width, level);
297 AddrSurfInfoIn->height = u_minify(config->info.height, level);
298
299 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
300 * because GFX9 needs linear alignment of 256 bytes.
301 */
302 if (config->info.levels == 1 &&
303 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
304 AddrSurfInfoIn->bpp &&
305 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
306 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
307
308 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
309 }
310
311 if (config->is_3d)
312 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
313 else if (config->is_cube)
314 AddrSurfInfoIn->numSlices = 6;
315 else
316 AddrSurfInfoIn->numSlices = config->info.array_size;
317
318 if (level > 0) {
319 /* Set the base level pitch. This is needed for calculation
320 * of non-zero levels. */
321 if (is_stencil)
322 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
323 else
324 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
325
326 /* Convert blocks to pixels for compressed formats. */
327 if (compressed)
328 AddrSurfInfoIn->basePitch *= surf->blk_w;
329 }
330
331 ret = AddrComputeSurfaceInfo(addrlib,
332 AddrSurfInfoIn,
333 AddrSurfInfoOut);
334 if (ret != ADDR_OK) {
335 return ret;
336 }
337
338 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
339 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
340 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
341 surf_level->nblk_x = AddrSurfInfoOut->pitch;
342 surf_level->nblk_y = AddrSurfInfoOut->height;
343
344 switch (AddrSurfInfoOut->tileMode) {
345 case ADDR_TM_LINEAR_ALIGNED:
346 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
347 break;
348 case ADDR_TM_1D_TILED_THIN1:
349 surf_level->mode = RADEON_SURF_MODE_1D;
350 break;
351 case ADDR_TM_2D_TILED_THIN1:
352 surf_level->mode = RADEON_SURF_MODE_2D;
353 break;
354 default:
355 assert(0);
356 }
357
358 if (is_stencil)
359 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
360 else
361 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
362
363 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
364
365 /* Clear DCC fields at the beginning. */
366 surf_level->dcc_offset = 0;
367
368 /* The previous level's flag tells us if we can use DCC for this level. */
369 if (AddrSurfInfoIn->flags.dccCompatible &&
370 (level == 0 || AddrDccOut->subLvlCompressible)) {
371 bool prev_level_clearable = level == 0 ||
372 AddrDccOut->dccRamSizeAligned;
373
374 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
375 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
376 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
377 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
378 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
379
380 ret = AddrComputeDccInfo(addrlib,
381 AddrDccIn,
382 AddrDccOut);
383
384 if (ret == ADDR_OK) {
385 surf_level->dcc_offset = surf->dcc_size;
386 surf->num_dcc_levels = level + 1;
387 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
388 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
389
390 /* If the DCC size of a subresource (1 mip level or 1 slice)
391 * is not aligned, the DCC memory layout is not contiguous for
392 * that subresource, which means we can't use fast clear.
393 *
394 * We only do fast clears for whole mipmap levels. If we did
395 * per-slice fast clears, the same restriction would apply.
396 * (i.e. only compute the slice size and see if it's aligned)
397 *
398 * The last level can be non-contiguous and still be clearable
399 * if it's interleaved with the next level that doesn't exist.
400 */
401 if (AddrDccOut->dccRamSizeAligned ||
402 (prev_level_clearable && level == config->info.levels - 1))
403 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
404 else
405 surf_level->dcc_fast_clear_size = 0;
406 }
407 }
408
409 /* TC-compatible HTILE. */
410 if (!is_stencil &&
411 AddrSurfInfoIn->flags.depth &&
412 surf_level->mode == RADEON_SURF_MODE_2D &&
413 level == 0) {
414 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
415 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
416 AddrHtileIn->height = AddrSurfInfoOut->height;
417 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
418 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
419 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
420 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
421 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
422 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
423
424 ret = AddrComputeHtileInfo(addrlib,
425 AddrHtileIn,
426 AddrHtileOut);
427
428 if (ret == ADDR_OK) {
429 surf->htile_size = AddrHtileOut->htileBytes;
430 surf->htile_slice_size = AddrHtileOut->sliceSize;
431 surf->htile_alignment = AddrHtileOut->baseAlign;
432 }
433 }
434
435 return 0;
436 }
437
438 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
439 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
440 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
441
442 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
443 const struct radeon_info *info)
444 {
445 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
446
447 if (info->chip_class >= CIK)
448 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
449 else
450 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
451 }
452
453 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
454 {
455 unsigned index, tileb;
456
457 tileb = 8 * 8 * surf->bpe;
458 tileb = MIN2(surf->u.legacy.tile_split, tileb);
459
460 for (index = 0; tileb > 64; index++)
461 tileb >>= 1;
462
463 assert(index < 16);
464 return index;
465 }
466
467 static bool get_display_flag(const struct ac_surf_config *config,
468 const struct radeon_surf *surf)
469 {
470 unsigned num_channels = config->info.num_channels;
471 unsigned bpe = surf->bpe;
472
473 if (surf->flags & RADEON_SURF_SCANOUT &&
474 config->info.samples <= 1 &&
475 surf->blk_w <= 2 && surf->blk_h == 1) {
476 /* subsampled */
477 if (surf->blk_w == 2 && surf->blk_h == 1)
478 return true;
479
480 if (/* RGBA8 or RGBA16F */
481 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
482 /* R5G6B5 or R5G5B5A1 */
483 (bpe == 2 && num_channels >= 3) ||
484 /* C8 palette */
485 (bpe == 1 && num_channels == 1))
486 return true;
487 }
488 return false;
489 }
490
491 /**
492 * This must be called after the first level is computed.
493 *
494 * Copy surface-global settings like pipe/bank config from level 0 surface
495 * computation, and compute tile swizzle.
496 */
497 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
498 const struct radeon_info *info,
499 const struct ac_surf_config *config,
500 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
501 struct radeon_surf *surf)
502 {
503 surf->surf_alignment = csio->baseAlign;
504 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
505 gfx6_set_micro_tile_mode(surf, info);
506
507 /* For 2D modes only. */
508 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
509 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
510 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
511 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
512 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
513 surf->u.legacy.num_banks = csio->pTileInfo->banks;
514 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
515 } else {
516 surf->u.legacy.macro_tile_index = 0;
517 }
518
519 /* Compute tile swizzle. */
520 /* TODO: fix tile swizzle with mipmapping for SI */
521 if ((info->chip_class >= CIK || config->info.levels == 1) &&
522 config->info.surf_index &&
523 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
524 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
525 !get_display_flag(config, surf)) {
526 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
527 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
528
529 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
530 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
531
532 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
533 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
534 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
535 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
536 AddrBaseSwizzleIn.tileMode = csio->tileMode;
537
538 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
539 &AddrBaseSwizzleOut);
540 if (r != ADDR_OK)
541 return r;
542
543 assert(AddrBaseSwizzleOut.tileSwizzle <=
544 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
545 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
546 }
547 return 0;
548 }
549
550 /**
551 * Fill in the tiling information in \p surf based on the given surface config.
552 *
553 * The following fields of \p surf must be initialized by the caller:
554 * blk_w, blk_h, bpe, flags.
555 */
556 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
557 const struct radeon_info *info,
558 const struct ac_surf_config *config,
559 enum radeon_surf_mode mode,
560 struct radeon_surf *surf)
561 {
562 unsigned level;
563 bool compressed;
564 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
565 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
566 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
567 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
568 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
569 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
570 ADDR_TILEINFO AddrTileInfoIn = {0};
571 ADDR_TILEINFO AddrTileInfoOut = {0};
572 int r;
573
574 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
575 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
576 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
577 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
578 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
579 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
580 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
581
582 compressed = surf->blk_w == 4 && surf->blk_h == 4;
583
584 /* MSAA requires 2D tiling. */
585 if (config->info.samples > 1)
586 mode = RADEON_SURF_MODE_2D;
587
588 /* DB doesn't support linear layouts. */
589 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
590 mode < RADEON_SURF_MODE_1D)
591 mode = RADEON_SURF_MODE_1D;
592
593 /* Set the requested tiling mode. */
594 switch (mode) {
595 case RADEON_SURF_MODE_LINEAR_ALIGNED:
596 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
597 break;
598 case RADEON_SURF_MODE_1D:
599 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
600 break;
601 case RADEON_SURF_MODE_2D:
602 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
603 break;
604 default:
605 assert(0);
606 }
607
608 /* The format must be set correctly for the allocation of compressed
609 * textures to work. In other cases, setting the bpp is sufficient.
610 */
611 if (compressed) {
612 switch (surf->bpe) {
613 case 8:
614 AddrSurfInfoIn.format = ADDR_FMT_BC1;
615 break;
616 case 16:
617 AddrSurfInfoIn.format = ADDR_FMT_BC3;
618 break;
619 default:
620 assert(0);
621 }
622 }
623 else {
624 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
625 }
626
627 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
628 MAX2(1, config->info.samples);
629 AddrSurfInfoIn.tileIndex = -1;
630
631 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
632 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
633 MAX2(1, config->info.color_samples);
634 }
635
636 /* Set the micro tile type. */
637 if (surf->flags & RADEON_SURF_SCANOUT)
638 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
639 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
640 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
641 else
642 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
643
644 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
645 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
646 AddrSurfInfoIn.flags.cube = config->is_cube;
647 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
648 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
649 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
650
651 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
652 * requested, because TC-compatible HTILE requires 2D tiling.
653 */
654 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
655 !AddrSurfInfoIn.flags.fmask &&
656 config->info.samples <= 1 &&
657 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
658
659 /* DCC notes:
660 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
661 * with samples >= 4.
662 * - Mipmapped array textures have low performance (discovered by a closed
663 * driver team).
664 */
665 AddrSurfInfoIn.flags.dccCompatible =
666 info->chip_class >= VI &&
667 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
668 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
669 !compressed &&
670 ((config->info.array_size == 1 && config->info.depth == 1) ||
671 config->info.levels == 1);
672
673 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
674 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
675
676 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
677 * for Z and stencil. This can cause a number of problems which we work
678 * around here:
679 *
680 * - a depth part that is incompatible with mipmapped texturing
681 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
682 * incorrect tiling applied to the stencil part, stencil buffer
683 * memory accesses that go out of bounds) even without mipmapping
684 *
685 * Some piglit tests that are prone to different types of related
686 * failures:
687 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
688 * ./bin/framebuffer-blit-levels {draw,read} stencil
689 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
690 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
691 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
692 */
693 int stencil_tile_idx = -1;
694
695 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
696 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
697 /* Compute stencilTileIdx that is compatible with the (depth)
698 * tileIdx. This degrades the depth surface if necessary to
699 * ensure that a matching stencilTileIdx exists. */
700 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
701
702 /* Keep the depth mip-tail compatible with texturing. */
703 AddrSurfInfoIn.flags.noStencil = 1;
704 }
705
706 /* Set preferred macrotile parameters. This is usually required
707 * for shared resources. This is for 2D tiling only. */
708 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
709 surf->u.legacy.bankw && surf->u.legacy.bankh &&
710 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
711 /* If any of these parameters are incorrect, the calculation
712 * will fail. */
713 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
714 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
715 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
716 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
717 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
718 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
719 AddrSurfInfoIn.flags.opt4Space = 0;
720 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
721
722 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
723 * the tile index, because we are expected to know it if
724 * we know the other parameters.
725 *
726 * This is something that can easily be fixed in Addrlib.
727 * For now, just figure it out here.
728 * Note that only 2D_TILE_THIN1 is handled here.
729 */
730 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
731 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
732
733 if (info->chip_class == SI) {
734 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
735 if (surf->bpe == 2)
736 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
737 else
738 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
739 } else {
740 if (surf->bpe == 1)
741 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
742 else if (surf->bpe == 2)
743 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
744 else if (surf->bpe == 4)
745 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
746 else
747 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
748 }
749 } else {
750 /* CIK - VI */
751 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
752 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
753 else
754 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
755
756 /* Addrlib doesn't set this if tileIndex is forced like above. */
757 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
758 }
759 }
760
761 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
762 surf->num_dcc_levels = 0;
763 surf->surf_size = 0;
764 surf->dcc_size = 0;
765 surf->dcc_alignment = 1;
766 surf->htile_size = 0;
767 surf->htile_slice_size = 0;
768 surf->htile_alignment = 1;
769
770 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
771 !(surf->flags & RADEON_SURF_ZBUFFER);
772
773 /* Calculate texture layout information. */
774 if (!only_stencil) {
775 for (level = 0; level < config->info.levels; level++) {
776 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
777 &AddrSurfInfoIn, &AddrSurfInfoOut,
778 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
779 if (r)
780 return r;
781
782 if (level > 0)
783 continue;
784
785 /* Check that we actually got a TC-compatible HTILE if
786 * we requested it (only for level 0, since we're not
787 * supporting HTILE on higher mip levels anyway). */
788 assert(AddrSurfInfoOut.tcCompatible ||
789 !AddrSurfInfoIn.flags.tcCompatible ||
790 AddrSurfInfoIn.flags.matchStencilTileCfg);
791
792 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
793 if (!AddrSurfInfoOut.tcCompatible) {
794 AddrSurfInfoIn.flags.tcCompatible = 0;
795 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
796 }
797
798 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
799 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
800 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
801
802 assert(stencil_tile_idx >= 0);
803 }
804
805 r = gfx6_surface_settings(addrlib, info, config,
806 &AddrSurfInfoOut, surf);
807 if (r)
808 return r;
809 }
810 }
811
812 /* Calculate texture layout information for stencil. */
813 if (surf->flags & RADEON_SURF_SBUFFER) {
814 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
815 AddrSurfInfoIn.bpp = 8;
816 AddrSurfInfoIn.flags.depth = 0;
817 AddrSurfInfoIn.flags.stencil = 1;
818 AddrSurfInfoIn.flags.tcCompatible = 0;
819 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
820 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
821
822 for (level = 0; level < config->info.levels; level++) {
823 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
824 &AddrSurfInfoIn, &AddrSurfInfoOut,
825 &AddrDccIn, &AddrDccOut,
826 NULL, NULL);
827 if (r)
828 return r;
829
830 /* DB uses the depth pitch for both stencil and depth. */
831 if (!only_stencil) {
832 if (surf->u.legacy.stencil_level[level].nblk_x !=
833 surf->u.legacy.level[level].nblk_x)
834 surf->u.legacy.stencil_adjusted = true;
835 } else {
836 surf->u.legacy.level[level].nblk_x =
837 surf->u.legacy.stencil_level[level].nblk_x;
838 }
839
840 if (level == 0) {
841 if (only_stencil) {
842 r = gfx6_surface_settings(addrlib, info, config,
843 &AddrSurfInfoOut, surf);
844 if (r)
845 return r;
846 }
847
848 /* For 2D modes only. */
849 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
850 surf->u.legacy.stencil_tile_split =
851 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
852 }
853 }
854 }
855 }
856
857 /* Compute FMASK. */
858 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
859 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
860 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
861 ADDR_TILEINFO fmask_tile_info = {};
862
863 fin.size = sizeof(fin);
864 fout.size = sizeof(fout);
865
866 fin.tileMode = AddrSurfInfoOut.tileMode;
867 fin.pitch = AddrSurfInfoOut.pitch;
868 fin.height = config->info.height;
869 fin.numSlices = AddrSurfInfoIn.numSlices;
870 fin.numSamples = AddrSurfInfoIn.numSamples;
871 fin.numFrags = AddrSurfInfoIn.numFrags;
872 fin.tileIndex = -1;
873 fout.pTileInfo = &fmask_tile_info;
874
875 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
876 if (r)
877 return r;
878
879 surf->fmask_size = fout.fmaskBytes;
880 surf->fmask_alignment = fout.baseAlign;
881 surf->fmask_tile_swizzle = 0;
882
883 surf->u.legacy.fmask.slice_tile_max =
884 (fout.pitch * fout.height) / 64;
885 if (surf->u.legacy.fmask.slice_tile_max)
886 surf->u.legacy.fmask.slice_tile_max -= 1;
887
888 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
889 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
890 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
891
892 /* Compute tile swizzle for FMASK. */
893 if (config->info.fmask_surf_index &&
894 !(surf->flags & RADEON_SURF_SHAREABLE)) {
895 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
896 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
897
898 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
899 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
900
901 /* This counter starts from 1 instead of 0. */
902 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
903 xin.tileIndex = fout.tileIndex;
904 xin.macroModeIndex = fout.macroModeIndex;
905 xin.pTileInfo = fout.pTileInfo;
906 xin.tileMode = fin.tileMode;
907
908 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
909 if (r != ADDR_OK)
910 return r;
911
912 assert(xout.tileSwizzle <=
913 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
914 surf->fmask_tile_swizzle = xout.tileSwizzle;
915 }
916 }
917
918 /* Recalculate the whole DCC miptree size including disabled levels.
919 * This is what addrlib does, but calling addrlib would be a lot more
920 * complicated.
921 */
922 if (surf->dcc_size && config->info.levels > 1) {
923 /* The smallest miplevels that are never compressed by DCC
924 * still read the DCC buffer via TC if the base level uses DCC,
925 * and for some reason the DCC buffer needs to be larger if
926 * the miptree uses non-zero tile_swizzle. Otherwise there are
927 * VM faults.
928 *
929 * "dcc_alignment * 4" was determined by trial and error.
930 */
931 surf->dcc_size = align64(surf->surf_size >> 8,
932 surf->dcc_alignment * 4);
933 }
934
935 /* Make sure HTILE covers the whole miptree, because the shader reads
936 * TC-compatible HTILE even for levels where it's disabled by DB.
937 */
938 if (surf->htile_size && config->info.levels > 1 &&
939 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
940 /* MSAA can't occur with levels > 1, so ignore the sample count. */
941 const unsigned total_pixels = surf->surf_size / surf->bpe;
942 const unsigned htile_block_size = 8 * 8;
943 const unsigned htile_element_size = 4;
944
945 surf->htile_size = (total_pixels / htile_block_size) *
946 htile_element_size;
947 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
948 }
949
950 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
951 surf->is_displayable = surf->is_linear ||
952 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
953 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
954
955 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
956 * used at the same time. This case is not currently expected to occur
957 * because we don't use rotated. Enforce this restriction on all chips
958 * to facilitate testing.
959 */
960 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
961 assert(!"rotate micro tile mode is unsupported");
962 return ADDR_ERROR;
963 }
964
965 return 0;
966 }
967
968 /* This is only called when expecting a tiled layout. */
969 static int
970 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
971 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
972 bool is_fmask, unsigned flags,
973 AddrSwizzleMode *swizzle_mode)
974 {
975 ADDR_E_RETURNCODE ret;
976 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
977 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
978
979 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
980 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
981
982 sin.flags = in->flags;
983 sin.resourceType = in->resourceType;
984 sin.format = in->format;
985 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
986 /* TODO: We could allow some of these: */
987 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
988 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
989 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
990 sin.bpp = in->bpp;
991 sin.width = in->width;
992 sin.height = in->height;
993 sin.numSlices = in->numSlices;
994 sin.numMipLevels = in->numMipLevels;
995 sin.numSamples = in->numSamples;
996 sin.numFrags = in->numFrags;
997
998 if (flags & RADEON_SURF_SCANOUT) {
999 sin.preferredSwSet.sw_D = 1;
1000 /* Raven only allows S for displayable surfaces with < 64 bpp, so
1001 * allow it as fallback */
1002 sin.preferredSwSet.sw_S = 1;
1003 } else if (in->flags.depth || in->flags.stencil || is_fmask)
1004 sin.preferredSwSet.sw_Z = 1;
1005 else
1006 sin.preferredSwSet.sw_S = 1;
1007
1008 if (is_fmask) {
1009 sin.flags.display = 0;
1010 sin.flags.color = 0;
1011 sin.flags.fmask = 1;
1012 }
1013
1014 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1015 if (ret != ADDR_OK)
1016 return ret;
1017
1018 *swizzle_mode = sout.swizzleMode;
1019 return 0;
1020 }
1021
1022 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1023 const struct ac_surf_config *config,
1024 struct radeon_surf *surf, bool compressed,
1025 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1026 {
1027 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1028 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1029 ADDR_E_RETURNCODE ret;
1030
1031 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1032 out.pMipInfo = mip_info;
1033
1034 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1035 if (ret != ADDR_OK)
1036 return ret;
1037
1038 if (in->flags.stencil) {
1039 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1040 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1041 out.mipChainPitch - 1;
1042 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1043 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1044 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1045 return 0;
1046 }
1047
1048 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1049 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1050 out.mipChainPitch - 1;
1051
1052 /* CMASK fast clear uses these even if FMASK isn't allocated.
1053 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1054 */
1055 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1056 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1057
1058 surf->u.gfx9.surf_slice_size = out.sliceSize;
1059 surf->u.gfx9.surf_pitch = out.pitch;
1060 surf->u.gfx9.surf_height = out.height;
1061 surf->surf_size = out.surfSize;
1062 surf->surf_alignment = out.baseAlign;
1063
1064 if (in->swizzleMode == ADDR_SW_LINEAR) {
1065 for (unsigned i = 0; i < in->numMipLevels; i++)
1066 surf->u.gfx9.offset[i] = mip_info[i].offset;
1067 }
1068
1069 if (in->flags.depth) {
1070 assert(in->swizzleMode != ADDR_SW_LINEAR);
1071
1072 /* HTILE */
1073 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1074 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1075
1076 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1077 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1078
1079 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1080 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1081 hin.depthFlags = in->flags;
1082 hin.swizzleMode = in->swizzleMode;
1083 hin.unalignedWidth = in->width;
1084 hin.unalignedHeight = in->height;
1085 hin.numSlices = in->numSlices;
1086 hin.numMipLevels = in->numMipLevels;
1087
1088 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1089 if (ret != ADDR_OK)
1090 return ret;
1091
1092 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1093 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1094 surf->htile_size = hout.htileBytes;
1095 surf->htile_slice_size = hout.sliceSize;
1096 surf->htile_alignment = hout.baseAlign;
1097 } else {
1098 /* Compute tile swizzle for the color surface.
1099 * All *_X and *_T modes can use the swizzle.
1100 */
1101 if (config->info.surf_index &&
1102 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1103 !out.mipChainInTail &&
1104 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1105 !in->flags.display) {
1106 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1107 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1108
1109 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1110 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1111
1112 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1113 xin.flags = in->flags;
1114 xin.swizzleMode = in->swizzleMode;
1115 xin.resourceType = in->resourceType;
1116 xin.format = in->format;
1117 xin.numSamples = in->numSamples;
1118 xin.numFrags = in->numFrags;
1119
1120 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1121 if (ret != ADDR_OK)
1122 return ret;
1123
1124 assert(xout.pipeBankXor <=
1125 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1126 surf->tile_swizzle = xout.pipeBankXor;
1127 }
1128
1129 /* DCC */
1130 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1131 !compressed &&
1132 in->swizzleMode != ADDR_SW_LINEAR) {
1133 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1134 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1135 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1136
1137 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1138 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1139 dout.pMipInfo = meta_mip_info;
1140
1141 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1142 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1143 din.colorFlags = in->flags;
1144 din.resourceType = in->resourceType;
1145 din.swizzleMode = in->swizzleMode;
1146 din.bpp = in->bpp;
1147 din.unalignedWidth = in->width;
1148 din.unalignedHeight = in->height;
1149 din.numSlices = in->numSlices;
1150 din.numFrags = in->numFrags;
1151 din.numMipLevels = in->numMipLevels;
1152 din.dataSurfaceSize = out.surfSize;
1153
1154 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1155 if (ret != ADDR_OK)
1156 return ret;
1157
1158 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1159 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1160 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
1161 surf->dcc_size = dout.dccRamSize;
1162 surf->dcc_alignment = dout.dccRamBaseAlign;
1163 surf->num_dcc_levels = in->numMipLevels;
1164
1165 /* Disable DCC for levels that are in the mip tail.
1166 *
1167 * There are two issues that this is intended to
1168 * address:
1169 *
1170 * 1. Multiple mip levels may share a cache line. This
1171 * can lead to corruption when switching between
1172 * rendering to different mip levels because the
1173 * RBs don't maintain coherency.
1174 *
1175 * 2. Texturing with metadata after rendering sometimes
1176 * fails with corruption, probably for a similar
1177 * reason.
1178 *
1179 * Working around these issues for all levels in the
1180 * mip tail may be overly conservative, but it's what
1181 * Vulkan does.
1182 *
1183 * Alternative solutions that also work but are worse:
1184 * - Disable DCC entirely.
1185 * - Flush TC L2 after rendering.
1186 */
1187 for (unsigned i = 0; i < in->numMipLevels; i++) {
1188 if (meta_mip_info[i].inMiptail) {
1189 surf->num_dcc_levels = i;
1190 break;
1191 }
1192 }
1193
1194 if (!surf->num_dcc_levels)
1195 surf->dcc_size = 0;
1196 }
1197
1198 /* FMASK */
1199 if (in->numSamples > 1) {
1200 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1201 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1202
1203 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1204 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1205
1206 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1207 true, surf->flags,
1208 &fin.swizzleMode);
1209 if (ret != ADDR_OK)
1210 return ret;
1211
1212 fin.unalignedWidth = in->width;
1213 fin.unalignedHeight = in->height;
1214 fin.numSlices = in->numSlices;
1215 fin.numSamples = in->numSamples;
1216 fin.numFrags = in->numFrags;
1217
1218 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1219 if (ret != ADDR_OK)
1220 return ret;
1221
1222 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1223 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1224 surf->fmask_size = fout.fmaskBytes;
1225 surf->fmask_alignment = fout.baseAlign;
1226
1227 /* Compute tile swizzle for the FMASK surface. */
1228 if (config->info.fmask_surf_index &&
1229 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1230 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1231 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1232 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1233
1234 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1235 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1236
1237 /* This counter starts from 1 instead of 0. */
1238 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1239 xin.flags = in->flags;
1240 xin.swizzleMode = in->swizzleMode;
1241 xin.resourceType = in->resourceType;
1242 xin.format = in->format;
1243 xin.numSamples = in->numSamples;
1244 xin.numFrags = in->numFrags;
1245
1246 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1247 if (ret != ADDR_OK)
1248 return ret;
1249
1250 assert(xout.pipeBankXor <=
1251 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1252 surf->fmask_tile_swizzle = xout.pipeBankXor;
1253 }
1254 }
1255
1256 /* CMASK */
1257 if (in->swizzleMode != ADDR_SW_LINEAR) {
1258 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1259 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1260
1261 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1262 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1263
1264 if (in->numSamples > 1) {
1265 /* FMASK is always aligned. */
1266 cin.cMaskFlags.pipeAligned = 1;
1267 cin.cMaskFlags.rbAligned = 1;
1268 } else {
1269 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1270 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1271 }
1272 cin.colorFlags = in->flags;
1273 cin.resourceType = in->resourceType;
1274 cin.unalignedWidth = in->width;
1275 cin.unalignedHeight = in->height;
1276 cin.numSlices = in->numSlices;
1277
1278 if (in->numSamples > 1)
1279 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1280 else
1281 cin.swizzleMode = in->swizzleMode;
1282
1283 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1284 if (ret != ADDR_OK)
1285 return ret;
1286
1287 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1288 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1289 surf->cmask_size = cout.cmaskBytes;
1290 surf->cmask_alignment = cout.baseAlign;
1291 }
1292 }
1293
1294 return 0;
1295 }
1296
1297 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1298 const struct radeon_info *info,
1299 const struct ac_surf_config *config,
1300 enum radeon_surf_mode mode,
1301 struct radeon_surf *surf)
1302 {
1303 bool compressed;
1304 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1305 int r;
1306
1307 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1308
1309 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1310
1311 /* The format must be set correctly for the allocation of compressed
1312 * textures to work. In other cases, setting the bpp is sufficient. */
1313 if (compressed) {
1314 switch (surf->bpe) {
1315 case 8:
1316 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1317 break;
1318 case 16:
1319 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1320 break;
1321 default:
1322 assert(0);
1323 }
1324 } else {
1325 switch (surf->bpe) {
1326 case 1:
1327 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1328 AddrSurfInfoIn.format = ADDR_FMT_8;
1329 break;
1330 case 2:
1331 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1332 !(surf->flags & RADEON_SURF_SBUFFER));
1333 AddrSurfInfoIn.format = ADDR_FMT_16;
1334 break;
1335 case 4:
1336 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1337 !(surf->flags & RADEON_SURF_SBUFFER));
1338 AddrSurfInfoIn.format = ADDR_FMT_32;
1339 break;
1340 case 8:
1341 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1342 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1343 break;
1344 case 12:
1345 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1346 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1347 break;
1348 case 16:
1349 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1350 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1351 break;
1352 default:
1353 assert(0);
1354 }
1355 AddrSurfInfoIn.bpp = surf->bpe * 8;
1356 }
1357
1358 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1359 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1360 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1361 /* flags.texture currently refers to TC-compatible HTILE */
1362 AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1363 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1364 AddrSurfInfoIn.flags.opt4space = 1;
1365
1366 AddrSurfInfoIn.numMipLevels = config->info.levels;
1367 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1368 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1369
1370 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1371 AddrSurfInfoIn.numFrags = MAX2(1, config->info.color_samples);
1372
1373 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1374 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1375 * must sample 1D textures as 2D. */
1376 if (config->is_3d)
1377 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1378 else
1379 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1380
1381 AddrSurfInfoIn.width = config->info.width;
1382 AddrSurfInfoIn.height = config->info.height;
1383
1384 if (config->is_3d)
1385 AddrSurfInfoIn.numSlices = config->info.depth;
1386 else if (config->is_cube)
1387 AddrSurfInfoIn.numSlices = 6;
1388 else
1389 AddrSurfInfoIn.numSlices = config->info.array_size;
1390
1391 /* This is propagated to HTILE/DCC/CMASK. */
1392 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1393 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1394
1395 switch (mode) {
1396 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1397 assert(config->info.samples <= 1);
1398 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1399 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1400 break;
1401
1402 case RADEON_SURF_MODE_1D:
1403 case RADEON_SURF_MODE_2D:
1404 if (surf->flags & RADEON_SURF_IMPORTED) {
1405 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1406 break;
1407 }
1408
1409 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1410 false, surf->flags,
1411 &AddrSurfInfoIn.swizzleMode);
1412 if (r)
1413 return r;
1414 break;
1415
1416 default:
1417 assert(0);
1418 }
1419
1420 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1421 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1422
1423 surf->num_dcc_levels = 0;
1424 surf->surf_size = 0;
1425 surf->fmask_size = 0;
1426 surf->dcc_size = 0;
1427 surf->htile_size = 0;
1428 surf->htile_slice_size = 0;
1429 surf->u.gfx9.surf_offset = 0;
1430 surf->u.gfx9.stencil_offset = 0;
1431 surf->cmask_size = 0;
1432
1433 /* Calculate texture layout information. */
1434 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1435 &AddrSurfInfoIn);
1436 if (r)
1437 return r;
1438
1439 /* Calculate texture layout information for stencil. */
1440 if (surf->flags & RADEON_SURF_SBUFFER) {
1441 AddrSurfInfoIn.flags.stencil = 1;
1442 AddrSurfInfoIn.bpp = 8;
1443 AddrSurfInfoIn.format = ADDR_FMT_8;
1444
1445 if (!AddrSurfInfoIn.flags.depth) {
1446 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1447 false, surf->flags,
1448 &AddrSurfInfoIn.swizzleMode);
1449 if (r)
1450 return r;
1451 } else
1452 AddrSurfInfoIn.flags.depth = 0;
1453
1454 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1455 &AddrSurfInfoIn);
1456 if (r)
1457 return r;
1458 }
1459
1460 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1461
1462 /* Query whether the surface is displayable. */
1463 bool displayable = false;
1464 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1465 surf->bpe * 8, &displayable);
1466 if (r)
1467 return r;
1468 surf->is_displayable = displayable;
1469
1470 switch (surf->u.gfx9.surf.swizzle_mode) {
1471 /* S = standard. */
1472 case ADDR_SW_256B_S:
1473 case ADDR_SW_4KB_S:
1474 case ADDR_SW_64KB_S:
1475 case ADDR_SW_VAR_S:
1476 case ADDR_SW_64KB_S_T:
1477 case ADDR_SW_4KB_S_X:
1478 case ADDR_SW_64KB_S_X:
1479 case ADDR_SW_VAR_S_X:
1480 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1481 break;
1482
1483 /* D = display. */
1484 case ADDR_SW_LINEAR:
1485 case ADDR_SW_256B_D:
1486 case ADDR_SW_4KB_D:
1487 case ADDR_SW_64KB_D:
1488 case ADDR_SW_VAR_D:
1489 case ADDR_SW_64KB_D_T:
1490 case ADDR_SW_4KB_D_X:
1491 case ADDR_SW_64KB_D_X:
1492 case ADDR_SW_VAR_D_X:
1493 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1494 break;
1495
1496 /* R = rotated. */
1497 case ADDR_SW_256B_R:
1498 case ADDR_SW_4KB_R:
1499 case ADDR_SW_64KB_R:
1500 case ADDR_SW_VAR_R:
1501 case ADDR_SW_64KB_R_T:
1502 case ADDR_SW_4KB_R_X:
1503 case ADDR_SW_64KB_R_X:
1504 case ADDR_SW_VAR_R_X:
1505 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1506 * used at the same time. This case is not currently expected to occur
1507 * because we don't use rotated. Enforce this restriction on all chips
1508 * to facilitate testing.
1509 */
1510 assert(!"rotate micro tile mode is unsupported");
1511 return ADDR_ERROR;
1512
1513 /* Z = depth. */
1514 case ADDR_SW_4KB_Z:
1515 case ADDR_SW_64KB_Z:
1516 case ADDR_SW_VAR_Z:
1517 case ADDR_SW_64KB_Z_T:
1518 case ADDR_SW_4KB_Z_X:
1519 case ADDR_SW_64KB_Z_X:
1520 case ADDR_SW_VAR_Z_X:
1521 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1522 break;
1523
1524 default:
1525 assert(0);
1526 }
1527
1528 /* Temporary workaround to prevent VM faults and hangs. */
1529 if (info->family == CHIP_VEGA12)
1530 surf->fmask_size *= 8;
1531
1532 return 0;
1533 }
1534
1535 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1536 const struct ac_surf_config *config,
1537 enum radeon_surf_mode mode,
1538 struct radeon_surf *surf)
1539 {
1540 int r;
1541
1542 r = surf_config_sanity(config, surf->flags);
1543 if (r)
1544 return r;
1545
1546 if (info->chip_class >= GFX9)
1547 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1548 else
1549 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1550 }