projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
drm-uapi,radv,radeonsi: Add amdgpu_drm.h header.
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include "drm-uapi/amdgpu_drm.h"
41
42 #include "addrlib/inc/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
53 {
54 return malloc(pInput->sizeInBytes);
55 }
56
57 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
58 {
59 free(pInput->pVirtAddr);
60 return ADDR_OK;
61 }
62
63 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
64 const struct amdgpu_gpu_info *amdinfo,
65 uint64_t *max_alignment)
66 {
67 ADDR_CREATE_INPUT addrCreateInput = {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
69 ADDR_REGISTER_VALUE regValue = {0};
70 ADDR_CREATE_FLAGS createFlags = {{0}};
71 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
72 ADDR_E_RETURNCODE addrRet;
73
74 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
75 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
76
77 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
78 createFlags.value = 0;
79
80 addrCreateInput.chipFamily = info->family_id;
81 addrCreateInput.chipRevision = info->chip_external_rev;
82
83 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
84 return NULL;
85
86 if (addrCreateInput.chipFamily >= FAMILY_AI) {
87 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
88 } else {
89 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
90 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
91
92 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
93 regValue.pTileConfig = amdinfo->gb_tile_mode;
94 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
95 if (addrCreateInput.chipFamily == FAMILY_SI) {
96 regValue.pMacroTileConfig = NULL;
97 regValue.noOfMacroEntries = 0;
98 } else {
99 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
100 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
101 }
102
103 createFlags.useTileIndex = 1;
104 createFlags.useHtileSliceAlign = 1;
105
106 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
107 }
108
109 addrCreateInput.callbacks.allocSysMem = allocSysMem;
110 addrCreateInput.callbacks.freeSysMem = freeSysMem;
111 addrCreateInput.callbacks.debugPrint = 0;
112 addrCreateInput.createFlags = createFlags;
113 addrCreateInput.regValue = regValue;
114
115 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
116 if (addrRet != ADDR_OK)
117 return NULL;
118
119 if (max_alignment) {
120 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
121 if (addrRet == ADDR_OK){
122 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
123 }
124 }
125 return addrCreateOutput.hLib;
126 }
127
128 static int surf_config_sanity(const struct ac_surf_config *config,
129 unsigned flags)
130 {
131 /* FMASK is allocated together with the color surface and can't be
132 * allocated separately.
133 */
134 assert(!(flags & RADEON_SURF_FMASK));
135 if (flags & RADEON_SURF_FMASK)
136 return -EINVAL;
137
138 /* all dimension must be at least 1 ! */
139 if (!config->info.width || !config->info.height || !config->info.depth ||
140 !config->info.array_size || !config->info.levels)
141 return -EINVAL;
142
143 switch (config->info.samples) {
144 case 0:
145 case 1:
146 case 2:
147 case 4:
148 case 8:
149 break;
150 case 16:
151 if (flags & RADEON_SURF_Z_OR_SBUFFER)
152 return -EINVAL;
153 break;
154 default:
155 return -EINVAL;
156 }
157
158 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
159 switch (config->info.storage_samples) {
160 case 0:
161 case 1:
162 case 2:
163 case 4:
164 case 8:
165 break;
166 default:
167 return -EINVAL;
168 }
169 }
170
171 if (config->is_3d && config->info.array_size > 1)
172 return -EINVAL;
173 if (config->is_cube && config->info.depth > 1)
174 return -EINVAL;
175
176 return 0;
177 }
178
179 static int gfx6_compute_level(ADDR_HANDLE addrlib,
180 const struct ac_surf_config *config,
181 struct radeon_surf *surf, bool is_stencil,
182 unsigned level, bool compressed,
183 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
184 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
185 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
186 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
187 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
188 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
189 {
190 struct legacy_surf_level *surf_level;
191 ADDR_E_RETURNCODE ret;
192
193 AddrSurfInfoIn->mipLevel = level;
194 AddrSurfInfoIn->width = u_minify(config->info.width, level);
195 AddrSurfInfoIn->height = u_minify(config->info.height, level);
196
197 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
198 * because GFX9 needs linear alignment of 256 bytes.
199 */
200 if (config->info.levels == 1 &&
201 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
202 AddrSurfInfoIn->bpp &&
203 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
204 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
205
206 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
207 }
208
209 /* addrlib assumes the bytes/pixel is a divisor of 64, which is not
210 * true for r32g32b32 formats. */
211 if (AddrSurfInfoIn->bpp == 96) {
212 assert(config->info.levels == 1);
213 assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
214
215 /* The least common multiple of 64 bytes and 12 bytes/pixel is
216 * 192 bytes, or 16 pixels. */
217 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
218 }
219
220 if (config->is_3d)
221 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
222 else if (config->is_cube)
223 AddrSurfInfoIn->numSlices = 6;
224 else
225 AddrSurfInfoIn->numSlices = config->info.array_size;
226
227 if (level > 0) {
228 /* Set the base level pitch. This is needed for calculation
229 * of non-zero levels. */
230 if (is_stencil)
231 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
232 else
233 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
234
235 /* Convert blocks to pixels for compressed formats. */
236 if (compressed)
237 AddrSurfInfoIn->basePitch *= surf->blk_w;
238 }
239
240 ret = AddrComputeSurfaceInfo(addrlib,
241 AddrSurfInfoIn,
242 AddrSurfInfoOut);
243 if (ret != ADDR_OK) {
244 return ret;
245 }
246
247 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
248 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
249 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
250 surf_level->nblk_x = AddrSurfInfoOut->pitch;
251 surf_level->nblk_y = AddrSurfInfoOut->height;
252
253 switch (AddrSurfInfoOut->tileMode) {
254 case ADDR_TM_LINEAR_ALIGNED:
255 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
256 break;
257 case ADDR_TM_1D_TILED_THIN1:
258 surf_level->mode = RADEON_SURF_MODE_1D;
259 break;
260 case ADDR_TM_2D_TILED_THIN1:
261 surf_level->mode = RADEON_SURF_MODE_2D;
262 break;
263 default:
264 assert(0);
265 }
266
267 if (is_stencil)
268 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
269 else
270 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
271
272 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
273
274 /* Clear DCC fields at the beginning. */
275 surf_level->dcc_offset = 0;
276
277 /* The previous level's flag tells us if we can use DCC for this level. */
278 if (AddrSurfInfoIn->flags.dccCompatible &&
279 (level == 0 || AddrDccOut->subLvlCompressible)) {
280 bool prev_level_clearable = level == 0 ||
281 AddrDccOut->dccRamSizeAligned;
282
283 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
284 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
285 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
286 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
287 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
288
289 ret = AddrComputeDccInfo(addrlib,
290 AddrDccIn,
291 AddrDccOut);
292
293 if (ret == ADDR_OK) {
294 surf_level->dcc_offset = surf->dcc_size;
295 surf->num_dcc_levels = level + 1;
296 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
297 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
298
299 /* If the DCC size of a subresource (1 mip level or 1 slice)
300 * is not aligned, the DCC memory layout is not contiguous for
301 * that subresource, which means we can't use fast clear.
302 *
303 * We only do fast clears for whole mipmap levels. If we did
304 * per-slice fast clears, the same restriction would apply.
305 * (i.e. only compute the slice size and see if it's aligned)
306 *
307 * The last level can be non-contiguous and still be clearable
308 * if it's interleaved with the next level that doesn't exist.
309 */
310 if (AddrDccOut->dccRamSizeAligned ||
311 (prev_level_clearable && level == config->info.levels - 1))
312 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
313 else
314 surf_level->dcc_fast_clear_size = 0;
315
316 /* Compute the DCC slice size because addrlib doesn't
317 * provide this info. As DCC memory is linear (each
318 * slice is the same size) it's easy to compute.
319 */
320 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
321
322 /* For arrays, we have to compute the DCC info again
323 * with one slice size to get a correct fast clear
324 * size.
325 */
326 if (config->info.array_size > 1) {
327 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
328 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
329 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
330 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
331 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
332
333 ret = AddrComputeDccInfo(addrlib,
334 AddrDccIn, AddrDccOut);
335 if (ret == ADDR_OK) {
336 /* If the DCC memory isn't properly
337 * aligned, the data are interleaved
338 * accross slices.
339 */
340 if (AddrDccOut->dccRamSizeAligned)
341 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
342 else
343 surf_level->dcc_slice_fast_clear_size = 0;
344 }
345 } else {
346 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
347 }
348 }
349 }
350
351 /* HTILE. */
352 if (!is_stencil &&
353 AddrSurfInfoIn->flags.depth &&
354 surf_level->mode == RADEON_SURF_MODE_2D &&
355 level == 0 &&
356 !(surf->flags & RADEON_SURF_NO_HTILE)) {
357 AddrHtileIn->flags.tcCompatible = AddrSurfInfoOut->tcCompatible;
358 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
359 AddrHtileIn->height = AddrSurfInfoOut->height;
360 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
361 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
362 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
363 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
364 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
365 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
366
367 ret = AddrComputeHtileInfo(addrlib,
368 AddrHtileIn,
369 AddrHtileOut);
370
371 if (ret == ADDR_OK) {
372 surf->htile_size = AddrHtileOut->htileBytes;
373 surf->htile_slice_size = AddrHtileOut->sliceSize;
374 surf->htile_alignment = AddrHtileOut->baseAlign;
375 }
376 }
377
378 return 0;
379 }
380
381 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
382 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
383 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
384
385 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
386 const struct radeon_info *info)
387 {
388 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
389
390 if (info->chip_class >= GFX7)
391 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
392 else
393 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
394 }
395
396 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
397 {
398 unsigned index, tileb;
399
400 tileb = 8 * 8 * surf->bpe;
401 tileb = MIN2(surf->u.legacy.tile_split, tileb);
402
403 for (index = 0; tileb > 64; index++)
404 tileb >>= 1;
405
406 assert(index < 16);
407 return index;
408 }
409
410 static bool get_display_flag(const struct ac_surf_config *config,
411 const struct radeon_surf *surf)
412 {
413 unsigned num_channels = config->info.num_channels;
414 unsigned bpe = surf->bpe;
415
416 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
417 surf->flags & RADEON_SURF_SCANOUT &&
418 config->info.samples <= 1 &&
419 surf->blk_w <= 2 && surf->blk_h == 1) {
420 /* subsampled */
421 if (surf->blk_w == 2 && surf->blk_h == 1)
422 return true;
423
424 if (/* RGBA8 or RGBA16F */
425 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
426 /* R5G6B5 or R5G5B5A1 */
427 (bpe == 2 && num_channels >= 3) ||
428 /* C8 palette */
429 (bpe == 1 && num_channels == 1))
430 return true;
431 }
432 return false;
433 }
434
435 /**
436 * This must be called after the first level is computed.
437 *
438 * Copy surface-global settings like pipe/bank config from level 0 surface
439 * computation, and compute tile swizzle.
440 */
441 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
442 const struct radeon_info *info,
443 const struct ac_surf_config *config,
444 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
445 struct radeon_surf *surf)
446 {
447 surf->surf_alignment = csio->baseAlign;
448 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
449 gfx6_set_micro_tile_mode(surf, info);
450
451 /* For 2D modes only. */
452 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
453 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
454 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
455 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
456 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
457 surf->u.legacy.num_banks = csio->pTileInfo->banks;
458 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
459 } else {
460 surf->u.legacy.macro_tile_index = 0;
461 }
462
463 /* Compute tile swizzle. */
464 /* TODO: fix tile swizzle with mipmapping for GFX6 */
465 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
466 config->info.surf_index &&
467 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
468 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
469 !get_display_flag(config, surf)) {
470 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
471 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
472
473 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
474 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
475
476 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
477 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
478 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
479 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
480 AddrBaseSwizzleIn.tileMode = csio->tileMode;
481
482 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
483 &AddrBaseSwizzleOut);
484 if (r != ADDR_OK)
485 return r;
486
487 assert(AddrBaseSwizzleOut.tileSwizzle <=
488 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
489 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
490 }
491 return 0;
492 }
493
494 static void ac_compute_cmask(const struct radeon_info *info,
495 const struct ac_surf_config *config,
496 struct radeon_surf *surf)
497 {
498 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
499 unsigned num_pipes = info->num_tile_pipes;
500 unsigned cl_width, cl_height;
501
502 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
503 (config->info.samples >= 2 && !surf->fmask_size))
504 return;
505
506 assert(info->chip_class <= GFX8);
507
508 switch (num_pipes) {
509 case 2:
510 cl_width = 32;
511 cl_height = 16;
512 break;
513 case 4:
514 cl_width = 32;
515 cl_height = 32;
516 break;
517 case 8:
518 cl_width = 64;
519 cl_height = 32;
520 break;
521 case 16: /* Hawaii */
522 cl_width = 64;
523 cl_height = 64;
524 break;
525 default:
526 assert(0);
527 return;
528 }
529
530 unsigned base_align = num_pipes * pipe_interleave_bytes;
531
532 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
533 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
534 unsigned slice_elements = (width * height) / (8*8);
535
536 /* Each element of CMASK is a nibble. */
537 unsigned slice_bytes = slice_elements / 2;
538
539 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
540 if (surf->u.legacy.cmask_slice_tile_max)
541 surf->u.legacy.cmask_slice_tile_max -= 1;
542
543 unsigned num_layers;
544 if (config->is_3d)
545 num_layers = config->info.depth;
546 else if (config->is_cube)
547 num_layers = 6;
548 else
549 num_layers = config->info.array_size;
550
551 surf->cmask_alignment = MAX2(256, base_align);
552 surf->cmask_slice_size = align(slice_bytes, base_align);
553 surf->cmask_size = surf->cmask_slice_size * num_layers;
554 }
555
556 /**
557 * Fill in the tiling information in \p surf based on the given surface config.
558 *
559 * The following fields of \p surf must be initialized by the caller:
560 * blk_w, blk_h, bpe, flags.
561 */
562 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
563 const struct radeon_info *info,
564 const struct ac_surf_config *config,
565 enum radeon_surf_mode mode,
566 struct radeon_surf *surf)
567 {
568 unsigned level;
569 bool compressed;
570 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
571 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
572 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
573 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
574 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
575 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
576 ADDR_TILEINFO AddrTileInfoIn = {0};
577 ADDR_TILEINFO AddrTileInfoOut = {0};
578 int r;
579
580 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
581 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
582 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
583 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
584 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
585 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
586 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
587
588 compressed = surf->blk_w == 4 && surf->blk_h == 4;
589
590 /* MSAA requires 2D tiling. */
591 if (config->info.samples > 1)
592 mode = RADEON_SURF_MODE_2D;
593
594 /* DB doesn't support linear layouts. */
595 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
596 mode < RADEON_SURF_MODE_1D)
597 mode = RADEON_SURF_MODE_1D;
598
599 /* Set the requested tiling mode. */
600 switch (mode) {
601 case RADEON_SURF_MODE_LINEAR_ALIGNED:
602 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
603 break;
604 case RADEON_SURF_MODE_1D:
605 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
606 break;
607 case RADEON_SURF_MODE_2D:
608 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
609 break;
610 default:
611 assert(0);
612 }
613
614 /* The format must be set correctly for the allocation of compressed
615 * textures to work. In other cases, setting the bpp is sufficient.
616 */
617 if (compressed) {
618 switch (surf->bpe) {
619 case 8:
620 AddrSurfInfoIn.format = ADDR_FMT_BC1;
621 break;
622 case 16:
623 AddrSurfInfoIn.format = ADDR_FMT_BC3;
624 break;
625 default:
626 assert(0);
627 }
628 }
629 else {
630 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
631 }
632
633 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
634 MAX2(1, config->info.samples);
635 AddrSurfInfoIn.tileIndex = -1;
636
637 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
638 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
639 MAX2(1, config->info.storage_samples);
640 }
641
642 /* Set the micro tile type. */
643 if (surf->flags & RADEON_SURF_SCANOUT)
644 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
645 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
646 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
647 else
648 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
649
650 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
651 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
652 AddrSurfInfoIn.flags.cube = config->is_cube;
653 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
654 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
655 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
656
657 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
658 * requested, because TC-compatible HTILE requires 2D tiling.
659 */
660 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
661 !AddrSurfInfoIn.flags.fmask &&
662 config->info.samples <= 1 &&
663 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
664
665 /* DCC notes:
666 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
667 * with samples >= 4.
668 * - Mipmapped array textures have low performance (discovered by a closed
669 * driver team).
670 */
671 AddrSurfInfoIn.flags.dccCompatible =
672 info->chip_class >= GFX8 &&
673 info->has_graphics && /* disable DCC on compute-only chips */
674 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
675 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
676 !compressed &&
677 ((config->info.array_size == 1 && config->info.depth == 1) ||
678 config->info.levels == 1);
679
680 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
681 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
682
683 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
684 * for Z and stencil. This can cause a number of problems which we work
685 * around here:
686 *
687 * - a depth part that is incompatible with mipmapped texturing
688 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
689 * incorrect tiling applied to the stencil part, stencil buffer
690 * memory accesses that go out of bounds) even without mipmapping
691 *
692 * Some piglit tests that are prone to different types of related
693 * failures:
694 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
695 * ./bin/framebuffer-blit-levels {draw,read} stencil
696 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
697 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
698 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
699 */
700 int stencil_tile_idx = -1;
701
702 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
703 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
704 /* Compute stencilTileIdx that is compatible with the (depth)
705 * tileIdx. This degrades the depth surface if necessary to
706 * ensure that a matching stencilTileIdx exists. */
707 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
708
709 /* Keep the depth mip-tail compatible with texturing. */
710 AddrSurfInfoIn.flags.noStencil = 1;
711 }
712
713 /* Set preferred macrotile parameters. This is usually required
714 * for shared resources. This is for 2D tiling only. */
715 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
716 surf->u.legacy.bankw && surf->u.legacy.bankh &&
717 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
718 /* If any of these parameters are incorrect, the calculation
719 * will fail. */
720 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
721 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
722 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
723 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
724 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
725 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
726 AddrSurfInfoIn.flags.opt4Space = 0;
727 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
728
729 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
730 * the tile index, because we are expected to know it if
731 * we know the other parameters.
732 *
733 * This is something that can easily be fixed in Addrlib.
734 * For now, just figure it out here.
735 * Note that only 2D_TILE_THIN1 is handled here.
736 */
737 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
738 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
739
740 if (info->chip_class == GFX6) {
741 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
742 if (surf->bpe == 2)
743 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
744 else
745 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
746 } else {
747 if (surf->bpe == 1)
748 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
749 else if (surf->bpe == 2)
750 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
751 else if (surf->bpe == 4)
752 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
753 else
754 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
755 }
756 } else {
757 /* GFX7 - GFX8 */
758 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
759 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
760 else
761 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
762
763 /* Addrlib doesn't set this if tileIndex is forced like above. */
764 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
765 }
766 }
767
768 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
769 surf->num_dcc_levels = 0;
770 surf->surf_size = 0;
771 surf->dcc_size = 0;
772 surf->dcc_alignment = 1;
773 surf->htile_size = 0;
774 surf->htile_slice_size = 0;
775 surf->htile_alignment = 1;
776
777 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
778 !(surf->flags & RADEON_SURF_ZBUFFER);
779
780 /* Calculate texture layout information. */
781 if (!only_stencil) {
782 for (level = 0; level < config->info.levels; level++) {
783 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
784 &AddrSurfInfoIn, &AddrSurfInfoOut,
785 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
786 if (r)
787 return r;
788
789 if (level > 0)
790 continue;
791
792 if (!AddrSurfInfoOut.tcCompatible) {
793 AddrSurfInfoIn.flags.tcCompatible = 0;
794 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
795 }
796
797 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
798 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
799 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
800 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
801
802 assert(stencil_tile_idx >= 0);
803 }
804
805 r = gfx6_surface_settings(addrlib, info, config,
806 &AddrSurfInfoOut, surf);
807 if (r)
808 return r;
809 }
810 }
811
812 /* Calculate texture layout information for stencil. */
813 if (surf->flags & RADEON_SURF_SBUFFER) {
814 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
815 AddrSurfInfoIn.bpp = 8;
816 AddrSurfInfoIn.flags.depth = 0;
817 AddrSurfInfoIn.flags.stencil = 1;
818 AddrSurfInfoIn.flags.tcCompatible = 0;
819 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
820 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
821
822 for (level = 0; level < config->info.levels; level++) {
823 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
824 &AddrSurfInfoIn, &AddrSurfInfoOut,
825 &AddrDccIn, &AddrDccOut,
826 NULL, NULL);
827 if (r)
828 return r;
829
830 /* DB uses the depth pitch for both stencil and depth. */
831 if (!only_stencil) {
832 if (surf->u.legacy.stencil_level[level].nblk_x !=
833 surf->u.legacy.level[level].nblk_x)
834 surf->u.legacy.stencil_adjusted = true;
835 } else {
836 surf->u.legacy.level[level].nblk_x =
837 surf->u.legacy.stencil_level[level].nblk_x;
838 }
839
840 if (level == 0) {
841 if (only_stencil) {
842 r = gfx6_surface_settings(addrlib, info, config,
843 &AddrSurfInfoOut, surf);
844 if (r)
845 return r;
846 }
847
848 /* For 2D modes only. */
849 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
850 surf->u.legacy.stencil_tile_split =
851 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
852 }
853 }
854 }
855 }
856
857 /* Compute FMASK. */
858 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
859 info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
860 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
861 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
862 ADDR_TILEINFO fmask_tile_info = {};
863
864 fin.size = sizeof(fin);
865 fout.size = sizeof(fout);
866
867 fin.tileMode = AddrSurfInfoOut.tileMode;
868 fin.pitch = AddrSurfInfoOut.pitch;
869 fin.height = config->info.height;
870 fin.numSlices = AddrSurfInfoIn.numSlices;
871 fin.numSamples = AddrSurfInfoIn.numSamples;
872 fin.numFrags = AddrSurfInfoIn.numFrags;
873 fin.tileIndex = -1;
874 fout.pTileInfo = &fmask_tile_info;
875
876 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
877 if (r)
878 return r;
879
880 surf->fmask_size = fout.fmaskBytes;
881 surf->fmask_alignment = fout.baseAlign;
882 surf->fmask_tile_swizzle = 0;
883
884 surf->u.legacy.fmask.slice_tile_max =
885 (fout.pitch * fout.height) / 64;
886 if (surf->u.legacy.fmask.slice_tile_max)
887 surf->u.legacy.fmask.slice_tile_max -= 1;
888
889 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
890 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
891 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
892 surf->u.legacy.fmask.slice_size = fout.sliceSize;
893
894 /* Compute tile swizzle for FMASK. */
895 if (config->info.fmask_surf_index &&
896 !(surf->flags & RADEON_SURF_SHAREABLE)) {
897 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
898 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
899
900 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
901 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
902
903 /* This counter starts from 1 instead of 0. */
904 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
905 xin.tileIndex = fout.tileIndex;
906 xin.macroModeIndex = fout.macroModeIndex;
907 xin.pTileInfo = fout.pTileInfo;
908 xin.tileMode = fin.tileMode;
909
910 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
911 if (r != ADDR_OK)
912 return r;
913
914 assert(xout.tileSwizzle <=
915 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
916 surf->fmask_tile_swizzle = xout.tileSwizzle;
917 }
918 }
919
920 /* Recalculate the whole DCC miptree size including disabled levels.
921 * This is what addrlib does, but calling addrlib would be a lot more
922 * complicated.
923 */
924 if (surf->dcc_size && config->info.levels > 1) {
925 /* The smallest miplevels that are never compressed by DCC
926 * still read the DCC buffer via TC if the base level uses DCC,
927 * and for some reason the DCC buffer needs to be larger if
928 * the miptree uses non-zero tile_swizzle. Otherwise there are
929 * VM faults.
930 *
931 * "dcc_alignment * 4" was determined by trial and error.
932 */
933 surf->dcc_size = align64(surf->surf_size >> 8,
934 surf->dcc_alignment * 4);
935 }
936
937 /* Make sure HTILE covers the whole miptree, because the shader reads
938 * TC-compatible HTILE even for levels where it's disabled by DB.
939 */
940 if (surf->htile_size && config->info.levels > 1 &&
941 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
942 /* MSAA can't occur with levels > 1, so ignore the sample count. */
943 const unsigned total_pixels = surf->surf_size / surf->bpe;
944 const unsigned htile_block_size = 8 * 8;
945 const unsigned htile_element_size = 4;
946
947 surf->htile_size = (total_pixels / htile_block_size) *
948 htile_element_size;
949 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
950 }
951
952 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
953 surf->is_displayable = surf->is_linear ||
954 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
955 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
956
957 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
958 * used at the same time. This case is not currently expected to occur
959 * because we don't use rotated. Enforce this restriction on all chips
960 * to facilitate testing.
961 */
962 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
963 assert(!"rotate micro tile mode is unsupported");
964 return ADDR_ERROR;
965 }
966
967 ac_compute_cmask(info, config, surf);
968 return 0;
969 }
970
971 /* This is only called when expecting a tiled layout. */
972 static int
973 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
974 struct radeon_surf *surf,
975 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
976 bool is_fmask, AddrSwizzleMode *swizzle_mode)
977 {
978 ADDR_E_RETURNCODE ret;
979 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
980 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
981
982 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
983 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
984
985 sin.flags = in->flags;
986 sin.resourceType = in->resourceType;
987 sin.format = in->format;
988 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
989 /* TODO: We could allow some of these: */
990 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
991 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
992 sin.bpp = in->bpp;
993 sin.width = in->width;
994 sin.height = in->height;
995 sin.numSlices = in->numSlices;
996 sin.numMipLevels = in->numMipLevels;
997 sin.numSamples = in->numSamples;
998 sin.numFrags = in->numFrags;
999
1000 if (is_fmask) {
1001 sin.flags.display = 0;
1002 sin.flags.color = 0;
1003 sin.flags.fmask = 1;
1004 }
1005
1006 if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
1007 sin.forbiddenBlock.linear = 1;
1008
1009 if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1010 sin.preferredSwSet.sw_D = 1;
1011 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_THIN)
1012 sin.preferredSwSet.sw_S = 1;
1013 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
1014 sin.preferredSwSet.sw_Z = 1;
1015 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED)
1016 sin.preferredSwSet.sw_R = 1;
1017 }
1018
1019 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1020 if (ret != ADDR_OK)
1021 return ret;
1022
1023 *swizzle_mode = sout.swizzleMode;
1024 return 0;
1025 }
1026
1027 static bool gfx9_is_dcc_capable(const struct radeon_info *info, unsigned sw_mode)
1028 {
1029 if (info->chip_class >= GFX10)
1030 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1031
1032 return sw_mode != ADDR_SW_LINEAR;
1033 }
1034
1035 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1036 const struct radeon_info *info,
1037 const struct ac_surf_config *config,
1038 struct radeon_surf *surf, bool compressed,
1039 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1040 {
1041 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1042 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1043 ADDR_E_RETURNCODE ret;
1044
1045 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1046 out.pMipInfo = mip_info;
1047
1048 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1049 if (ret != ADDR_OK)
1050 return ret;
1051
1052 if (in->flags.stencil) {
1053 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1054 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1055 out.mipChainPitch - 1;
1056 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1057 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1058 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1059 return 0;
1060 }
1061
1062 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1063 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1064 out.mipChainPitch - 1;
1065
1066 /* CMASK fast clear uses these even if FMASK isn't allocated.
1067 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1068 */
1069 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1070 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1071
1072 surf->u.gfx9.surf_slice_size = out.sliceSize;
1073 surf->u.gfx9.surf_pitch = out.pitch;
1074 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch) {
1075 /* Adjust surf_pitch to be in elements units,
1076 * not in pixels */
1077 surf->u.gfx9.surf_pitch /= surf->blk_w;
1078 }
1079 surf->u.gfx9.surf_height = out.height;
1080 surf->surf_size = out.surfSize;
1081 surf->surf_alignment = out.baseAlign;
1082
1083 if (in->swizzleMode == ADDR_SW_LINEAR) {
1084 for (unsigned i = 0; i < in->numMipLevels; i++) {
1085 surf->u.gfx9.offset[i] = mip_info[i].offset;
1086 surf->u.gfx9.pitch[i] = mip_info[i].pitch;
1087 }
1088 }
1089
1090 if (in->flags.depth) {
1091 assert(in->swizzleMode != ADDR_SW_LINEAR);
1092
1093 if (surf->flags & RADEON_SURF_NO_HTILE)
1094 return 0;
1095
1096 /* HTILE */
1097 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1098 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1099
1100 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1101 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1102
1103 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1104 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1105 hin.depthFlags = in->flags;
1106 hin.swizzleMode = in->swizzleMode;
1107 hin.unalignedWidth = in->width;
1108 hin.unalignedHeight = in->height;
1109 hin.numSlices = in->numSlices;
1110 hin.numMipLevels = in->numMipLevels;
1111 hin.firstMipIdInTail = out.firstMipIdInTail;
1112
1113 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1114 if (ret != ADDR_OK)
1115 return ret;
1116
1117 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1118 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1119 surf->htile_size = hout.htileBytes;
1120 surf->htile_slice_size = hout.sliceSize;
1121 surf->htile_alignment = hout.baseAlign;
1122 return 0;
1123 }
1124
1125 {
1126 /* Compute tile swizzle for the color surface.
1127 * All *_X and *_T modes can use the swizzle.
1128 */
1129 if (config->info.surf_index &&
1130 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1131 !out.mipChainInTail &&
1132 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1133 !in->flags.display) {
1134 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1135 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1136
1137 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1138 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1139
1140 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1141 xin.flags = in->flags;
1142 xin.swizzleMode = in->swizzleMode;
1143 xin.resourceType = in->resourceType;
1144 xin.format = in->format;
1145 xin.numSamples = in->numSamples;
1146 xin.numFrags = in->numFrags;
1147
1148 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1149 if (ret != ADDR_OK)
1150 return ret;
1151
1152 assert(xout.pipeBankXor <=
1153 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1154 surf->tile_swizzle = xout.pipeBankXor;
1155 }
1156
1157 /* DCC */
1158 if (info->has_graphics &&
1159 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1160 !compressed &&
1161 gfx9_is_dcc_capable(info, in->swizzleMode)) {
1162 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1163 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1164 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1165
1166 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1167 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1168 dout.pMipInfo = meta_mip_info;
1169
1170 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1171 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1172 din.colorFlags = in->flags;
1173 din.resourceType = in->resourceType;
1174 din.swizzleMode = in->swizzleMode;
1175 din.bpp = in->bpp;
1176 din.unalignedWidth = in->width;
1177 din.unalignedHeight = in->height;
1178 din.numSlices = in->numSlices;
1179 din.numFrags = in->numFrags;
1180 din.numMipLevels = in->numMipLevels;
1181 din.dataSurfaceSize = out.surfSize;
1182 din.firstMipIdInTail = out.firstMipIdInTail;
1183
1184 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1185 if (ret != ADDR_OK)
1186 return ret;
1187
1188 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1189 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1190 surf->dcc_size = dout.dccRamSize;
1191 surf->dcc_alignment = dout.dccRamBaseAlign;
1192 surf->num_dcc_levels = in->numMipLevels;
1193
1194 /* Disable DCC for levels that are in the mip tail.
1195 *
1196 * There are two issues that this is intended to
1197 * address:
1198 *
1199 * 1. Multiple mip levels may share a cache line. This
1200 * can lead to corruption when switching between
1201 * rendering to different mip levels because the
1202 * RBs don't maintain coherency.
1203 *
1204 * 2. Texturing with metadata after rendering sometimes
1205 * fails with corruption, probably for a similar
1206 * reason.
1207 *
1208 * Working around these issues for all levels in the
1209 * mip tail may be overly conservative, but it's what
1210 * Vulkan does.
1211 *
1212 * Alternative solutions that also work but are worse:
1213 * - Disable DCC entirely.
1214 * - Flush TC L2 after rendering.
1215 */
1216 for (unsigned i = 0; i < in->numMipLevels; i++) {
1217 if (meta_mip_info[i].inMiptail) {
1218 surf->num_dcc_levels = i;
1219 break;
1220 }
1221 }
1222
1223 if (!surf->num_dcc_levels)
1224 surf->dcc_size = 0;
1225
1226 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1227 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1228 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1229
1230 /* Compute displayable DCC. */
1231 if (in->flags.display &&
1232 surf->num_dcc_levels &&
1233 info->use_display_dcc_with_retile_blit) {
1234 /* Compute displayable DCC info. */
1235 din.dccKeyFlags.pipeAligned = 0;
1236 din.dccKeyFlags.rbAligned = 0;
1237
1238 assert(din.numSlices == 1);
1239 assert(din.numMipLevels == 1);
1240 assert(din.numFrags == 1);
1241 assert(surf->tile_swizzle == 0);
1242 assert(surf->u.gfx9.dcc.pipe_aligned ||
1243 surf->u.gfx9.dcc.rb_aligned);
1244
1245 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1246 if (ret != ADDR_OK)
1247 return ret;
1248
1249 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1250 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1251 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1252 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1253
1254 /* Compute address mapping from non-displayable to displayable DCC. */
1255 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1256 addrin.size = sizeof(addrin);
1257 addrin.colorFlags.color = 1;
1258 addrin.swizzleMode = din.swizzleMode;
1259 addrin.resourceType = din.resourceType;
1260 addrin.bpp = din.bpp;
1261 addrin.unalignedWidth = din.unalignedWidth;
1262 addrin.unalignedHeight = din.unalignedHeight;
1263 addrin.numSlices = 1;
1264 addrin.numMipLevels = 1;
1265 addrin.numFrags = 1;
1266
1267 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1268 addrout.size = sizeof(addrout);
1269
1270 surf->u.gfx9.dcc_retile_num_elements =
1271 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1272 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1273 /* Align the size to 4 (for the compute shader). */
1274 surf->u.gfx9.dcc_retile_num_elements =
1275 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1276
1277 surf->u.gfx9.dcc_retile_map =
1278 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1279 if (!surf->u.gfx9.dcc_retile_map)
1280 return ADDR_OUTOFMEMORY;
1281
1282 unsigned index = 0;
1283 surf->u.gfx9.dcc_retile_use_uint16 = true;
1284
1285 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1286 addrin.y = y;
1287
1288 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1289 addrin.x = x;
1290
1291 /* Compute src DCC address */
1292 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1293 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1294 addrout.addr = 0;
1295
1296 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1297 if (ret != ADDR_OK)
1298 return ret;
1299
1300 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1301 if (addrout.addr > UINT16_MAX)
1302 surf->u.gfx9.dcc_retile_use_uint16 = false;
1303
1304 /* Compute dst DCC address */
1305 addrin.dccKeyFlags.pipeAligned = 0;
1306 addrin.dccKeyFlags.rbAligned = 0;
1307 addrout.addr = 0;
1308
1309 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1310 if (ret != ADDR_OK)
1311 return ret;
1312
1313 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1314 if (addrout.addr > UINT16_MAX)
1315 surf->u.gfx9.dcc_retile_use_uint16 = false;
1316
1317 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1318 index++;
1319 }
1320 }
1321 /* Fill the remaining pairs with the last one (for the compute shader). */
1322 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1323 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1324 }
1325 }
1326
1327 /* FMASK */
1328 if (in->numSamples > 1 && info->has_graphics &&
1329 !(surf->flags & RADEON_SURF_NO_FMASK)) {
1330 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1331 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1332
1333 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1334 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1335
1336 ret = gfx9_get_preferred_swizzle_mode(addrlib, surf, in,
1337 true, &fin.swizzleMode);
1338 if (ret != ADDR_OK)
1339 return ret;
1340
1341 fin.unalignedWidth = in->width;
1342 fin.unalignedHeight = in->height;
1343 fin.numSlices = in->numSlices;
1344 fin.numSamples = in->numSamples;
1345 fin.numFrags = in->numFrags;
1346
1347 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1348 if (ret != ADDR_OK)
1349 return ret;
1350
1351 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1352 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1353 surf->fmask_size = fout.fmaskBytes;
1354 surf->fmask_alignment = fout.baseAlign;
1355
1356 /* Compute tile swizzle for the FMASK surface. */
1357 if (config->info.fmask_surf_index &&
1358 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1359 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1360 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1361 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1362
1363 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1364 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1365
1366 /* This counter starts from 1 instead of 0. */
1367 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1368 xin.flags = in->flags;
1369 xin.swizzleMode = fin.swizzleMode;
1370 xin.resourceType = in->resourceType;
1371 xin.format = in->format;
1372 xin.numSamples = in->numSamples;
1373 xin.numFrags = in->numFrags;
1374
1375 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1376 if (ret != ADDR_OK)
1377 return ret;
1378
1379 assert(xout.pipeBankXor <=
1380 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1381 surf->fmask_tile_swizzle = xout.pipeBankXor;
1382 }
1383 }
1384
1385 /* CMASK -- on GFX10 only for FMASK */
1386 if (in->swizzleMode != ADDR_SW_LINEAR &&
1387 in->resourceType == ADDR_RSRC_TEX_2D &&
1388 ((info->chip_class <= GFX9 && in->numSamples == 1) ||
1389 (surf->fmask_size && in->numSamples >= 2))) {
1390 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1391 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1392
1393 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1394 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1395
1396 if (in->numSamples > 1) {
1397 /* FMASK is always aligned. */
1398 cin.cMaskFlags.pipeAligned = 1;
1399 cin.cMaskFlags.rbAligned = 1;
1400 } else {
1401 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1402 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1403 }
1404 cin.colorFlags = in->flags;
1405 cin.resourceType = in->resourceType;
1406 cin.unalignedWidth = in->width;
1407 cin.unalignedHeight = in->height;
1408 cin.numSlices = in->numSlices;
1409
1410 if (in->numSamples > 1)
1411 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1412 else
1413 cin.swizzleMode = in->swizzleMode;
1414
1415 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1416 if (ret != ADDR_OK)
1417 return ret;
1418
1419 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1420 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1421 surf->cmask_size = cout.cmaskBytes;
1422 surf->cmask_alignment = cout.baseAlign;
1423 }
1424 }
1425
1426 return 0;
1427 }
1428
1429 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1430 const struct radeon_info *info,
1431 const struct ac_surf_config *config,
1432 enum radeon_surf_mode mode,
1433 struct radeon_surf *surf)
1434 {
1435 bool compressed;
1436 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1437 int r;
1438
1439 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1440
1441 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1442
1443 /* The format must be set correctly for the allocation of compressed
1444 * textures to work. In other cases, setting the bpp is sufficient. */
1445 if (compressed) {
1446 switch (surf->bpe) {
1447 case 8:
1448 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1449 break;
1450 case 16:
1451 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1452 break;
1453 default:
1454 assert(0);
1455 }
1456 } else {
1457 switch (surf->bpe) {
1458 case 1:
1459 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1460 AddrSurfInfoIn.format = ADDR_FMT_8;
1461 break;
1462 case 2:
1463 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1464 !(surf->flags & RADEON_SURF_SBUFFER));
1465 AddrSurfInfoIn.format = ADDR_FMT_16;
1466 break;
1467 case 4:
1468 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1469 !(surf->flags & RADEON_SURF_SBUFFER));
1470 AddrSurfInfoIn.format = ADDR_FMT_32;
1471 break;
1472 case 8:
1473 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1474 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1475 break;
1476 case 12:
1477 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1478 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1479 break;
1480 case 16:
1481 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1482 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1483 break;
1484 default:
1485 assert(0);
1486 }
1487 AddrSurfInfoIn.bpp = surf->bpe * 8;
1488 }
1489
1490 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1491 AddrSurfInfoIn.flags.color = is_color_surface &&
1492 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1493 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1494 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1495 /* flags.texture currently refers to TC-compatible HTILE */
1496 AddrSurfInfoIn.flags.texture = is_color_surface ||
1497 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1498 AddrSurfInfoIn.flags.opt4space = 1;
1499
1500 AddrSurfInfoIn.numMipLevels = config->info.levels;
1501 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1502 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1503
1504 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1505 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1506
1507 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1508 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1509 * must sample 1D textures as 2D. */
1510 if (config->is_3d)
1511 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1512 else if (info->chip_class != GFX9 && config->is_1d)
1513 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
1514 else
1515 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1516
1517 AddrSurfInfoIn.width = config->info.width;
1518 AddrSurfInfoIn.height = config->info.height;
1519
1520 if (config->is_3d)
1521 AddrSurfInfoIn.numSlices = config->info.depth;
1522 else if (config->is_cube)
1523 AddrSurfInfoIn.numSlices = 6;
1524 else
1525 AddrSurfInfoIn.numSlices = config->info.array_size;
1526
1527 /* This is propagated to HTILE/DCC/CMASK. */
1528 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1529 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1530
1531 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1532 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1533 *
1534 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1535 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1536 * after rendering, so PIPE_ALIGNED=1 is recommended.
1537 */
1538 if (info->use_display_dcc_unaligned && is_color_surface &&
1539 AddrSurfInfoIn.flags.display) {
1540 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1541 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1542 }
1543
1544 switch (mode) {
1545 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1546 assert(config->info.samples <= 1);
1547 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1548 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1549 break;
1550
1551 case RADEON_SURF_MODE_1D:
1552 case RADEON_SURF_MODE_2D:
1553 if (surf->flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FORCE_SWIZZLE_MODE)) {
1554 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1555 break;
1556 }
1557
1558 r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
1559 false, &AddrSurfInfoIn.swizzleMode);
1560 if (r)
1561 return r;
1562 break;
1563
1564 default:
1565 assert(0);
1566 }
1567
1568 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1569 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1570
1571 surf->num_dcc_levels = 0;
1572 surf->surf_size = 0;
1573 surf->fmask_size = 0;
1574 surf->dcc_size = 0;
1575 surf->htile_size = 0;
1576 surf->htile_slice_size = 0;
1577 surf->u.gfx9.surf_offset = 0;
1578 surf->u.gfx9.stencil_offset = 0;
1579 surf->cmask_size = 0;
1580 surf->u.gfx9.dcc_retile_use_uint16 = false;
1581 surf->u.gfx9.dcc_retile_num_elements = 0;
1582 surf->u.gfx9.dcc_retile_map = NULL;
1583
1584 /* Calculate texture layout information. */
1585 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1586 &AddrSurfInfoIn);
1587 if (r)
1588 goto error;
1589
1590 /* Calculate texture layout information for stencil. */
1591 if (surf->flags & RADEON_SURF_SBUFFER) {
1592 AddrSurfInfoIn.flags.stencil = 1;
1593 AddrSurfInfoIn.bpp = 8;
1594 AddrSurfInfoIn.format = ADDR_FMT_8;
1595
1596 if (!AddrSurfInfoIn.flags.depth) {
1597 r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
1598 false, &AddrSurfInfoIn.swizzleMode);
1599 if (r)
1600 goto error;
1601 } else
1602 AddrSurfInfoIn.flags.depth = 0;
1603
1604 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1605 &AddrSurfInfoIn);
1606 if (r)
1607 goto error;
1608 }
1609
1610 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1611
1612 /* Query whether the surface is displayable. */
1613 bool displayable = false;
1614 if (!config->is_3d && !config->is_cube) {
1615 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1616 surf->bpe * 8, &displayable);
1617 if (r)
1618 goto error;
1619
1620 /* Display needs unaligned DCC. */
1621 if (info->use_display_dcc_unaligned &&
1622 surf->num_dcc_levels &&
1623 (surf->u.gfx9.dcc.pipe_aligned ||
1624 surf->u.gfx9.dcc.rb_aligned))
1625 displayable = false;
1626 }
1627 surf->is_displayable = displayable;
1628
1629 switch (surf->u.gfx9.surf.swizzle_mode) {
1630 /* S = standard. */
1631 case ADDR_SW_256B_S:
1632 case ADDR_SW_4KB_S:
1633 case ADDR_SW_64KB_S:
1634 case ADDR_SW_64KB_S_T:
1635 case ADDR_SW_4KB_S_X:
1636 case ADDR_SW_64KB_S_X:
1637 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1638 break;
1639
1640 /* D = display. */
1641 case ADDR_SW_LINEAR:
1642 case ADDR_SW_256B_D:
1643 case ADDR_SW_4KB_D:
1644 case ADDR_SW_64KB_D:
1645 case ADDR_SW_64KB_D_T:
1646 case ADDR_SW_4KB_D_X:
1647 case ADDR_SW_64KB_D_X:
1648 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1649 break;
1650
1651 /* R = rotated (gfx9), render target (gfx10). */
1652 case ADDR_SW_256B_R:
1653 case ADDR_SW_4KB_R:
1654 case ADDR_SW_64KB_R:
1655 case ADDR_SW_64KB_R_T:
1656 case ADDR_SW_4KB_R_X:
1657 case ADDR_SW_64KB_R_X:
1658 case ADDR_SW_VAR_R_X:
1659 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1660 * used at the same time. We currently do not use rotated
1661 * in gfx9.
1662 */
1663 assert(info->chip_class >= GFX10 ||
1664 !"rotate micro tile mode is unsupported");
1665 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1666 break;
1667
1668 /* Z = depth. */
1669 case ADDR_SW_4KB_Z:
1670 case ADDR_SW_64KB_Z:
1671 case ADDR_SW_64KB_Z_T:
1672 case ADDR_SW_4KB_Z_X:
1673 case ADDR_SW_64KB_Z_X:
1674 case ADDR_SW_VAR_Z_X:
1675 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1676 break;
1677
1678 default:
1679 assert(0);
1680 }
1681
1682 return 0;
1683
1684 error:
1685 free(surf->u.gfx9.dcc_retile_map);
1686 surf->u.gfx9.dcc_retile_map = NULL;
1687 return r;
1688 }
1689
1690 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1691 const struct ac_surf_config *config,
1692 enum radeon_surf_mode mode,
1693 struct radeon_surf *surf)
1694 {
1695 int r;
1696
1697 r = surf_config_sanity(config, surf->flags);
1698 if (r)
1699 return r;
1700
1701 if (info->chip_class >= GFX9)
1702 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
1703 else
1704 r = gfx6_compute_surface(addrlib, info, config, mode, surf);
1705
1706 if (r)
1707 return r;
1708
1709 /* Determine the memory layout of multiple allocations in one buffer. */
1710 surf->total_size = surf->surf_size;
1711
1712 if (surf->htile_size) {
1713 surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
1714 surf->total_size = surf->htile_offset + surf->htile_size;
1715 }
1716
1717 if (surf->fmask_size) {
1718 assert(config->info.samples >= 2);
1719 surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
1720 surf->total_size = surf->fmask_offset + surf->fmask_size;
1721 }
1722
1723 /* Single-sample CMASK is in a separate buffer. */
1724 if (surf->cmask_size && config->info.samples >= 2) {
1725 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
1726 surf->total_size = surf->cmask_offset + surf->cmask_size;
1727 }
1728
1729 if (surf->dcc_size &&
1730 (info->use_display_dcc_unaligned ||
1731 info->use_display_dcc_with_retile_blit ||
1732 !(surf->flags & RADEON_SURF_SCANOUT))) {
1733 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
1734 surf->total_size = surf->dcc_offset + surf->dcc_size;
1735
1736 if (info->chip_class >= GFX9 &&
1737 surf->u.gfx9.dcc_retile_num_elements) {
1738 /* Add space for the displayable DCC buffer. */
1739 surf->display_dcc_offset =
1740 align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
1741 surf->total_size = surf->display_dcc_offset +
1742 surf->u.gfx9.display_dcc_size;
1743
1744 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1745 surf->dcc_retile_map_offset =
1746 align64(surf->total_size, info->tcc_cache_line_size);
1747
1748 if (surf->u.gfx9.dcc_retile_use_uint16) {
1749 surf->total_size = surf->dcc_retile_map_offset +
1750 surf->u.gfx9.dcc_retile_num_elements * 2;
1751 } else {
1752 surf->total_size = surf->dcc_retile_map_offset +
1753 surf->u.gfx9.dcc_retile_num_elements * 4;
1754 }
1755 }
1756 }
1757
1758 return 0;
1759 }