2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
40 #include <amdgpu_drm.h>
42 #include "addrlib/inc/addrinterface.h"
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
52 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
54 return malloc(pInput
->sizeInBytes
);
57 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
59 free(pInput
->pVirtAddr
);
63 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
64 const struct amdgpu_gpu_info
*amdinfo
,
65 uint64_t *max_alignment
)
67 ADDR_CREATE_INPUT addrCreateInput
= {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
69 ADDR_REGISTER_VALUE regValue
= {0};
70 ADDR_CREATE_FLAGS createFlags
= {{0}};
71 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput
= {0};
72 ADDR_E_RETURNCODE addrRet
;
74 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
75 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
77 regValue
.gbAddrConfig
= amdinfo
->gb_addr_cfg
;
78 createFlags
.value
= 0;
80 addrCreateInput
.chipFamily
= info
->family_id
;
81 addrCreateInput
.chipRevision
= info
->chip_external_rev
;
83 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
86 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
87 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
88 regValue
.blockVarSizeLog2
= 0;
90 regValue
.noOfBanks
= amdinfo
->mc_arb_ramcfg
& 0x3;
91 regValue
.noOfRanks
= (amdinfo
->mc_arb_ramcfg
& 0x4) >> 2;
93 regValue
.backendDisables
= amdinfo
->enabled_rb_pipes_mask
;
94 regValue
.pTileConfig
= amdinfo
->gb_tile_mode
;
95 regValue
.noOfEntries
= ARRAY_SIZE(amdinfo
->gb_tile_mode
);
96 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
97 regValue
.pMacroTileConfig
= NULL
;
98 regValue
.noOfMacroEntries
= 0;
100 regValue
.pMacroTileConfig
= amdinfo
->gb_macro_tile_mode
;
101 regValue
.noOfMacroEntries
= ARRAY_SIZE(amdinfo
->gb_macro_tile_mode
);
104 createFlags
.useTileIndex
= 1;
105 createFlags
.useHtileSliceAlign
= 1;
107 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
110 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
111 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
112 addrCreateInput
.callbacks
.debugPrint
= 0;
113 addrCreateInput
.createFlags
= createFlags
;
114 addrCreateInput
.regValue
= regValue
;
116 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
117 if (addrRet
!= ADDR_OK
)
121 addrRet
= AddrGetMaxAlignments(addrCreateOutput
.hLib
, &addrGetMaxAlignmentsOutput
);
122 if (addrRet
== ADDR_OK
){
123 *max_alignment
= addrGetMaxAlignmentsOutput
.baseAlign
;
126 return addrCreateOutput
.hLib
;
129 static int surf_config_sanity(const struct ac_surf_config
*config
,
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
135 assert(!(flags
& RADEON_SURF_FMASK
));
136 if (flags
& RADEON_SURF_FMASK
)
139 /* all dimension must be at least 1 ! */
140 if (!config
->info
.width
|| !config
->info
.height
|| !config
->info
.depth
||
141 !config
->info
.array_size
|| !config
->info
.levels
)
144 switch (config
->info
.samples
) {
152 if (flags
& RADEON_SURF_Z_OR_SBUFFER
)
159 if (!(flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
160 switch (config
->info
.storage_samples
) {
172 if (config
->is_3d
&& config
->info
.array_size
> 1)
174 if (config
->is_cube
&& config
->info
.depth
> 1)
180 static int gfx6_compute_level(ADDR_HANDLE addrlib
,
181 const struct ac_surf_config
*config
,
182 struct radeon_surf
*surf
, bool is_stencil
,
183 unsigned level
, bool compressed
,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT
*AddrSurfInfoIn
,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut
,
186 ADDR_COMPUTE_DCCINFO_INPUT
*AddrDccIn
,
187 ADDR_COMPUTE_DCCINFO_OUTPUT
*AddrDccOut
,
188 ADDR_COMPUTE_HTILE_INFO_INPUT
*AddrHtileIn
,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT
*AddrHtileOut
)
191 struct legacy_surf_level
*surf_level
;
192 ADDR_E_RETURNCODE ret
;
194 AddrSurfInfoIn
->mipLevel
= level
;
195 AddrSurfInfoIn
->width
= u_minify(config
->info
.width
, level
);
196 AddrSurfInfoIn
->height
= u_minify(config
->info
.height
, level
);
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
201 if (config
->info
.levels
== 1 &&
202 AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
&&
203 AddrSurfInfoIn
->bpp
&&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn
->bpp
)) {
205 unsigned alignment
= 256 / (AddrSurfInfoIn
->bpp
/ 8);
207 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, alignment
);
211 AddrSurfInfoIn
->numSlices
= u_minify(config
->info
.depth
, level
);
212 else if (config
->is_cube
)
213 AddrSurfInfoIn
->numSlices
= 6;
215 AddrSurfInfoIn
->numSlices
= config
->info
.array_size
;
218 /* Set the base level pitch. This is needed for calculation
219 * of non-zero levels. */
221 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.stencil_level
[0].nblk_x
;
223 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.level
[0].nblk_x
;
225 /* Convert blocks to pixels for compressed formats. */
227 AddrSurfInfoIn
->basePitch
*= surf
->blk_w
;
230 ret
= AddrComputeSurfaceInfo(addrlib
,
233 if (ret
!= ADDR_OK
) {
237 surf_level
= is_stencil
? &surf
->u
.legacy
.stencil_level
[level
] : &surf
->u
.legacy
.level
[level
];
238 surf_level
->offset
= align64(surf
->surf_size
, AddrSurfInfoOut
->baseAlign
);
239 surf_level
->slice_size_dw
= AddrSurfInfoOut
->sliceSize
/ 4;
240 surf_level
->nblk_x
= AddrSurfInfoOut
->pitch
;
241 surf_level
->nblk_y
= AddrSurfInfoOut
->height
;
243 switch (AddrSurfInfoOut
->tileMode
) {
244 case ADDR_TM_LINEAR_ALIGNED
:
245 surf_level
->mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
247 case ADDR_TM_1D_TILED_THIN1
:
248 surf_level
->mode
= RADEON_SURF_MODE_1D
;
250 case ADDR_TM_2D_TILED_THIN1
:
251 surf_level
->mode
= RADEON_SURF_MODE_2D
;
258 surf
->u
.legacy
.stencil_tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
260 surf
->u
.legacy
.tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
262 surf
->surf_size
= surf_level
->offset
+ AddrSurfInfoOut
->surfSize
;
264 /* Clear DCC fields at the beginning. */
265 surf_level
->dcc_offset
= 0;
267 /* The previous level's flag tells us if we can use DCC for this level. */
268 if (AddrSurfInfoIn
->flags
.dccCompatible
&&
269 (level
== 0 || AddrDccOut
->subLvlCompressible
)) {
270 bool prev_level_clearable
= level
== 0 ||
271 AddrDccOut
->dccRamSizeAligned
;
273 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->surfSize
;
274 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
275 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
276 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
277 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
279 ret
= AddrComputeDccInfo(addrlib
,
283 if (ret
== ADDR_OK
) {
284 surf_level
->dcc_offset
= surf
->dcc_size
;
285 surf
->num_dcc_levels
= level
+ 1;
286 surf
->dcc_size
= surf_level
->dcc_offset
+ AddrDccOut
->dccRamSize
;
287 surf
->dcc_alignment
= MAX2(surf
->dcc_alignment
, AddrDccOut
->dccRamBaseAlign
);
289 /* If the DCC size of a subresource (1 mip level or 1 slice)
290 * is not aligned, the DCC memory layout is not contiguous for
291 * that subresource, which means we can't use fast clear.
293 * We only do fast clears for whole mipmap levels. If we did
294 * per-slice fast clears, the same restriction would apply.
295 * (i.e. only compute the slice size and see if it's aligned)
297 * The last level can be non-contiguous and still be clearable
298 * if it's interleaved with the next level that doesn't exist.
300 if (AddrDccOut
->dccRamSizeAligned
||
301 (prev_level_clearable
&& level
== config
->info
.levels
- 1))
302 surf_level
->dcc_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
304 surf_level
->dcc_fast_clear_size
= 0;
306 /* Compute the DCC slice size because addrlib doesn't
307 * provide this info. As DCC memory is linear (each
308 * slice is the same size) it's easy to compute.
310 surf
->dcc_slice_size
= AddrDccOut
->dccRamSize
/ config
->info
.array_size
;
312 /* For arrays, we have to compute the DCC info again
313 * with one slice size to get a correct fast clear
316 if (config
->info
.array_size
> 1) {
317 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->sliceSize
;
318 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
319 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
320 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
321 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
323 ret
= AddrComputeDccInfo(addrlib
,
324 AddrDccIn
, AddrDccOut
);
325 if (ret
== ADDR_OK
) {
326 /* If the DCC memory isn't properly
327 * aligned, the data are interleaved
330 if (AddrDccOut
->dccRamSizeAligned
)
331 surf_level
->dcc_slice_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
333 surf_level
->dcc_slice_fast_clear_size
= 0;
336 surf_level
->dcc_slice_fast_clear_size
= surf_level
->dcc_fast_clear_size
;
343 AddrSurfInfoIn
->flags
.depth
&&
344 surf_level
->mode
== RADEON_SURF_MODE_2D
&&
346 !(surf
->flags
& RADEON_SURF_NO_HTILE
)) {
347 AddrHtileIn
->flags
.tcCompatible
= AddrSurfInfoIn
->flags
.tcCompatible
;
348 AddrHtileIn
->pitch
= AddrSurfInfoOut
->pitch
;
349 AddrHtileIn
->height
= AddrSurfInfoOut
->height
;
350 AddrHtileIn
->numSlices
= AddrSurfInfoOut
->depth
;
351 AddrHtileIn
->blockWidth
= ADDR_HTILE_BLOCKSIZE_8
;
352 AddrHtileIn
->blockHeight
= ADDR_HTILE_BLOCKSIZE_8
;
353 AddrHtileIn
->pTileInfo
= AddrSurfInfoOut
->pTileInfo
;
354 AddrHtileIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
355 AddrHtileIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
357 ret
= AddrComputeHtileInfo(addrlib
,
361 if (ret
== ADDR_OK
) {
362 surf
->htile_size
= AddrHtileOut
->htileBytes
;
363 surf
->htile_slice_size
= AddrHtileOut
->sliceSize
;
364 surf
->htile_alignment
= AddrHtileOut
->baseAlign
;
371 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
372 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
373 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
375 static void gfx6_set_micro_tile_mode(struct radeon_surf
*surf
,
376 const struct radeon_info
*info
)
378 uint32_t tile_mode
= info
->si_tile_mode_array
[surf
->u
.legacy
.tiling_index
[0]];
380 if (info
->chip_class
>= GFX7
)
381 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE_NEW(tile_mode
);
383 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE(tile_mode
);
386 static unsigned cik_get_macro_tile_index(struct radeon_surf
*surf
)
388 unsigned index
, tileb
;
390 tileb
= 8 * 8 * surf
->bpe
;
391 tileb
= MIN2(surf
->u
.legacy
.tile_split
, tileb
);
393 for (index
= 0; tileb
> 64; index
++)
400 static bool get_display_flag(const struct ac_surf_config
*config
,
401 const struct radeon_surf
*surf
)
403 unsigned num_channels
= config
->info
.num_channels
;
404 unsigned bpe
= surf
->bpe
;
406 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
407 surf
->flags
& RADEON_SURF_SCANOUT
&&
408 config
->info
.samples
<= 1 &&
409 surf
->blk_w
<= 2 && surf
->blk_h
== 1) {
411 if (surf
->blk_w
== 2 && surf
->blk_h
== 1)
414 if (/* RGBA8 or RGBA16F */
415 (bpe
>= 4 && bpe
<= 8 && num_channels
== 4) ||
416 /* R5G6B5 or R5G5B5A1 */
417 (bpe
== 2 && num_channels
>= 3) ||
419 (bpe
== 1 && num_channels
== 1))
426 * This must be called after the first level is computed.
428 * Copy surface-global settings like pipe/bank config from level 0 surface
429 * computation, and compute tile swizzle.
431 static int gfx6_surface_settings(ADDR_HANDLE addrlib
,
432 const struct radeon_info
*info
,
433 const struct ac_surf_config
*config
,
434 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* csio
,
435 struct radeon_surf
*surf
)
437 surf
->surf_alignment
= csio
->baseAlign
;
438 surf
->u
.legacy
.pipe_config
= csio
->pTileInfo
->pipeConfig
- 1;
439 gfx6_set_micro_tile_mode(surf
, info
);
441 /* For 2D modes only. */
442 if (csio
->tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
443 surf
->u
.legacy
.bankw
= csio
->pTileInfo
->bankWidth
;
444 surf
->u
.legacy
.bankh
= csio
->pTileInfo
->bankHeight
;
445 surf
->u
.legacy
.mtilea
= csio
->pTileInfo
->macroAspectRatio
;
446 surf
->u
.legacy
.tile_split
= csio
->pTileInfo
->tileSplitBytes
;
447 surf
->u
.legacy
.num_banks
= csio
->pTileInfo
->banks
;
448 surf
->u
.legacy
.macro_tile_index
= csio
->macroModeIndex
;
450 surf
->u
.legacy
.macro_tile_index
= 0;
453 /* Compute tile swizzle. */
454 /* TODO: fix tile swizzle with mipmapping for GFX6 */
455 if ((info
->chip_class
>= GFX7
|| config
->info
.levels
== 1) &&
456 config
->info
.surf_index
&&
457 surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
&&
458 !(surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_SHAREABLE
)) &&
459 !get_display_flag(config
, surf
)) {
460 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn
= {0};
461 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut
= {0};
463 AddrBaseSwizzleIn
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
464 AddrBaseSwizzleOut
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
466 AddrBaseSwizzleIn
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
467 AddrBaseSwizzleIn
.tileIndex
= csio
->tileIndex
;
468 AddrBaseSwizzleIn
.macroModeIndex
= csio
->macroModeIndex
;
469 AddrBaseSwizzleIn
.pTileInfo
= csio
->pTileInfo
;
470 AddrBaseSwizzleIn
.tileMode
= csio
->tileMode
;
472 int r
= AddrComputeBaseSwizzle(addrlib
, &AddrBaseSwizzleIn
,
473 &AddrBaseSwizzleOut
);
477 assert(AddrBaseSwizzleOut
.tileSwizzle
<=
478 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
479 surf
->tile_swizzle
= AddrBaseSwizzleOut
.tileSwizzle
;
484 static void ac_compute_cmask(const struct radeon_info
*info
,
485 const struct ac_surf_config
*config
,
486 struct radeon_surf
*surf
)
488 unsigned pipe_interleave_bytes
= info
->pipe_interleave_bytes
;
489 unsigned num_pipes
= info
->num_tile_pipes
;
490 unsigned cl_width
, cl_height
;
492 if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
||
493 (config
->info
.samples
>= 2 && !surf
->fmask_size
))
496 assert(info
->chip_class
<= GFX8
);
511 case 16: /* Hawaii */
520 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
522 unsigned width
= align(surf
->u
.legacy
.level
[0].nblk_x
, cl_width
*8);
523 unsigned height
= align(surf
->u
.legacy
.level
[0].nblk_y
, cl_height
*8);
524 unsigned slice_elements
= (width
* height
) / (8*8);
526 /* Each element of CMASK is a nibble. */
527 unsigned slice_bytes
= slice_elements
/ 2;
529 surf
->u
.legacy
.cmask_slice_tile_max
= (width
* height
) / (128*128);
530 if (surf
->u
.legacy
.cmask_slice_tile_max
)
531 surf
->u
.legacy
.cmask_slice_tile_max
-= 1;
535 num_layers
= config
->info
.depth
;
536 else if (config
->is_cube
)
539 num_layers
= config
->info
.array_size
;
541 surf
->cmask_alignment
= MAX2(256, base_align
);
542 surf
->cmask_slice_size
= align(slice_bytes
, base_align
);
543 surf
->cmask_size
= surf
->cmask_slice_size
* num_layers
;
547 * Fill in the tiling information in \p surf based on the given surface config.
549 * The following fields of \p surf must be initialized by the caller:
550 * blk_w, blk_h, bpe, flags.
552 static int gfx6_compute_surface(ADDR_HANDLE addrlib
,
553 const struct radeon_info
*info
,
554 const struct ac_surf_config
*config
,
555 enum radeon_surf_mode mode
,
556 struct radeon_surf
*surf
)
560 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
561 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut
= {0};
562 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn
= {0};
563 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut
= {0};
564 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn
= {0};
565 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut
= {0};
566 ADDR_TILEINFO AddrTileInfoIn
= {0};
567 ADDR_TILEINFO AddrTileInfoOut
= {0};
570 AddrSurfInfoIn
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT
);
571 AddrSurfInfoOut
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT
);
572 AddrDccIn
.size
= sizeof(ADDR_COMPUTE_DCCINFO_INPUT
);
573 AddrDccOut
.size
= sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT
);
574 AddrHtileIn
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT
);
575 AddrHtileOut
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT
);
576 AddrSurfInfoOut
.pTileInfo
= &AddrTileInfoOut
;
578 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
580 /* MSAA requires 2D tiling. */
581 if (config
->info
.samples
> 1)
582 mode
= RADEON_SURF_MODE_2D
;
584 /* DB doesn't support linear layouts. */
585 if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
) &&
586 mode
< RADEON_SURF_MODE_1D
)
587 mode
= RADEON_SURF_MODE_1D
;
589 /* Set the requested tiling mode. */
591 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
592 AddrSurfInfoIn
.tileMode
= ADDR_TM_LINEAR_ALIGNED
;
594 case RADEON_SURF_MODE_1D
:
595 AddrSurfInfoIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
597 case RADEON_SURF_MODE_2D
:
598 AddrSurfInfoIn
.tileMode
= ADDR_TM_2D_TILED_THIN1
;
604 /* The format must be set correctly for the allocation of compressed
605 * textures to work. In other cases, setting the bpp is sufficient.
610 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
613 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
620 AddrDccIn
.bpp
= AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
623 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numSamples
=
624 MAX2(1, config
->info
.samples
);
625 AddrSurfInfoIn
.tileIndex
= -1;
627 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
628 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numFrags
=
629 MAX2(1, config
->info
.storage_samples
);
632 /* Set the micro tile type. */
633 if (surf
->flags
& RADEON_SURF_SCANOUT
)
634 AddrSurfInfoIn
.tileType
= ADDR_DISPLAYABLE
;
635 else if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)
636 AddrSurfInfoIn
.tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
638 AddrSurfInfoIn
.tileType
= ADDR_NON_DISPLAYABLE
;
640 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
641 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
642 AddrSurfInfoIn
.flags
.cube
= config
->is_cube
;
643 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
644 AddrSurfInfoIn
.flags
.pow2Pad
= config
->info
.levels
> 1;
645 AddrSurfInfoIn
.flags
.tcCompatible
= (surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) != 0;
647 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
648 * requested, because TC-compatible HTILE requires 2D tiling.
650 AddrSurfInfoIn
.flags
.opt4Space
= !AddrSurfInfoIn
.flags
.tcCompatible
&&
651 !AddrSurfInfoIn
.flags
.fmask
&&
652 config
->info
.samples
<= 1 &&
653 (surf
->flags
& RADEON_SURF_OPTIMIZE_FOR_SPACE
);
656 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
658 * - Mipmapped array textures have low performance (discovered by a closed
661 AddrSurfInfoIn
.flags
.dccCompatible
=
662 info
->chip_class
>= GFX8
&&
663 info
->has_graphics
&& /* disable DCC on compute-only chips */
664 !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
665 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
667 ((config
->info
.array_size
== 1 && config
->info
.depth
== 1) ||
668 config
->info
.levels
== 1);
670 AddrSurfInfoIn
.flags
.noStencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) == 0;
671 AddrSurfInfoIn
.flags
.compressZ
= !!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
673 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
674 * for Z and stencil. This can cause a number of problems which we work
677 * - a depth part that is incompatible with mipmapped texturing
678 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
679 * incorrect tiling applied to the stencil part, stencil buffer
680 * memory accesses that go out of bounds) even without mipmapping
682 * Some piglit tests that are prone to different types of related
684 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
685 * ./bin/framebuffer-blit-levels {draw,read} stencil
686 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
687 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
688 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
690 int stencil_tile_idx
= -1;
692 if (AddrSurfInfoIn
.flags
.depth
&& !AddrSurfInfoIn
.flags
.noStencil
&&
693 (config
->info
.levels
> 1 || info
->family
== CHIP_STONEY
)) {
694 /* Compute stencilTileIdx that is compatible with the (depth)
695 * tileIdx. This degrades the depth surface if necessary to
696 * ensure that a matching stencilTileIdx exists. */
697 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 1;
699 /* Keep the depth mip-tail compatible with texturing. */
700 AddrSurfInfoIn
.flags
.noStencil
= 1;
703 /* Set preferred macrotile parameters. This is usually required
704 * for shared resources. This is for 2D tiling only. */
705 if (AddrSurfInfoIn
.tileMode
>= ADDR_TM_2D_TILED_THIN1
&&
706 surf
->u
.legacy
.bankw
&& surf
->u
.legacy
.bankh
&&
707 surf
->u
.legacy
.mtilea
&& surf
->u
.legacy
.tile_split
) {
708 /* If any of these parameters are incorrect, the calculation
710 AddrTileInfoIn
.banks
= surf
->u
.legacy
.num_banks
;
711 AddrTileInfoIn
.bankWidth
= surf
->u
.legacy
.bankw
;
712 AddrTileInfoIn
.bankHeight
= surf
->u
.legacy
.bankh
;
713 AddrTileInfoIn
.macroAspectRatio
= surf
->u
.legacy
.mtilea
;
714 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.tile_split
;
715 AddrTileInfoIn
.pipeConfig
= surf
->u
.legacy
.pipe_config
+ 1; /* +1 compared to GB_TILE_MODE */
716 AddrSurfInfoIn
.flags
.opt4Space
= 0;
717 AddrSurfInfoIn
.pTileInfo
= &AddrTileInfoIn
;
719 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
720 * the tile index, because we are expected to know it if
721 * we know the other parameters.
723 * This is something that can easily be fixed in Addrlib.
724 * For now, just figure it out here.
725 * Note that only 2D_TILE_THIN1 is handled here.
727 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
728 assert(AddrSurfInfoIn
.tileMode
== ADDR_TM_2D_TILED_THIN1
);
730 if (info
->chip_class
== GFX6
) {
731 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
) {
733 AddrSurfInfoIn
.tileIndex
= 11; /* 16bpp */
735 AddrSurfInfoIn
.tileIndex
= 12; /* 32bpp */
738 AddrSurfInfoIn
.tileIndex
= 14; /* 8bpp */
739 else if (surf
->bpe
== 2)
740 AddrSurfInfoIn
.tileIndex
= 15; /* 16bpp */
741 else if (surf
->bpe
== 4)
742 AddrSurfInfoIn
.tileIndex
= 16; /* 32bpp */
744 AddrSurfInfoIn
.tileIndex
= 17; /* 64bpp (and 128bpp) */
748 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
)
749 AddrSurfInfoIn
.tileIndex
= 10; /* 2D displayable */
751 AddrSurfInfoIn
.tileIndex
= 14; /* 2D non-displayable */
753 /* Addrlib doesn't set this if tileIndex is forced like above. */
754 AddrSurfInfoOut
.macroModeIndex
= cik_get_macro_tile_index(surf
);
758 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
759 surf
->num_dcc_levels
= 0;
762 surf
->dcc_alignment
= 1;
763 surf
->htile_size
= 0;
764 surf
->htile_slice_size
= 0;
765 surf
->htile_alignment
= 1;
767 const bool only_stencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) &&
768 !(surf
->flags
& RADEON_SURF_ZBUFFER
);
770 /* Calculate texture layout information. */
772 for (level
= 0; level
< config
->info
.levels
; level
++) {
773 r
= gfx6_compute_level(addrlib
, config
, surf
, false, level
, compressed
,
774 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
775 &AddrDccIn
, &AddrDccOut
, &AddrHtileIn
, &AddrHtileOut
);
782 /* Check that we actually got a TC-compatible HTILE if
783 * we requested it (only for level 0, since we're not
784 * supporting HTILE on higher mip levels anyway). */
785 assert(AddrSurfInfoOut
.tcCompatible
||
786 !AddrSurfInfoIn
.flags
.tcCompatible
||
787 AddrSurfInfoIn
.flags
.matchStencilTileCfg
);
789 if (AddrSurfInfoIn
.flags
.matchStencilTileCfg
) {
790 if (!AddrSurfInfoOut
.tcCompatible
) {
791 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
792 surf
->flags
&= ~RADEON_SURF_TC_COMPATIBLE_HTILE
;
795 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 0;
796 AddrSurfInfoIn
.tileIndex
= AddrSurfInfoOut
.tileIndex
;
797 stencil_tile_idx
= AddrSurfInfoOut
.stencilTileIdx
;
799 assert(stencil_tile_idx
>= 0);
802 r
= gfx6_surface_settings(addrlib
, info
, config
,
803 &AddrSurfInfoOut
, surf
);
809 /* Calculate texture layout information for stencil. */
810 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
811 AddrSurfInfoIn
.tileIndex
= stencil_tile_idx
;
812 AddrSurfInfoIn
.bpp
= 8;
813 AddrSurfInfoIn
.flags
.depth
= 0;
814 AddrSurfInfoIn
.flags
.stencil
= 1;
815 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
816 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
817 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.stencil_tile_split
;
819 for (level
= 0; level
< config
->info
.levels
; level
++) {
820 r
= gfx6_compute_level(addrlib
, config
, surf
, true, level
, compressed
,
821 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
822 &AddrDccIn
, &AddrDccOut
,
827 /* DB uses the depth pitch for both stencil and depth. */
829 if (surf
->u
.legacy
.stencil_level
[level
].nblk_x
!=
830 surf
->u
.legacy
.level
[level
].nblk_x
)
831 surf
->u
.legacy
.stencil_adjusted
= true;
833 surf
->u
.legacy
.level
[level
].nblk_x
=
834 surf
->u
.legacy
.stencil_level
[level
].nblk_x
;
839 r
= gfx6_surface_settings(addrlib
, info
, config
,
840 &AddrSurfInfoOut
, surf
);
845 /* For 2D modes only. */
846 if (AddrSurfInfoOut
.tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
847 surf
->u
.legacy
.stencil_tile_split
=
848 AddrSurfInfoOut
.pTileInfo
->tileSplitBytes
;
855 if (config
->info
.samples
>= 2 && AddrSurfInfoIn
.flags
.color
&&
856 !(surf
->flags
& RADEON_SURF_NO_FMASK
)) {
857 ADDR_COMPUTE_FMASK_INFO_INPUT fin
= {0};
858 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
859 ADDR_TILEINFO fmask_tile_info
= {};
861 fin
.size
= sizeof(fin
);
862 fout
.size
= sizeof(fout
);
864 fin
.tileMode
= AddrSurfInfoOut
.tileMode
;
865 fin
.pitch
= AddrSurfInfoOut
.pitch
;
866 fin
.height
= config
->info
.height
;
867 fin
.numSlices
= AddrSurfInfoIn
.numSlices
;
868 fin
.numSamples
= AddrSurfInfoIn
.numSamples
;
869 fin
.numFrags
= AddrSurfInfoIn
.numFrags
;
871 fout
.pTileInfo
= &fmask_tile_info
;
873 r
= AddrComputeFmaskInfo(addrlib
, &fin
, &fout
);
877 surf
->fmask_size
= fout
.fmaskBytes
;
878 surf
->fmask_alignment
= fout
.baseAlign
;
879 surf
->fmask_tile_swizzle
= 0;
881 surf
->u
.legacy
.fmask
.slice_tile_max
=
882 (fout
.pitch
* fout
.height
) / 64;
883 if (surf
->u
.legacy
.fmask
.slice_tile_max
)
884 surf
->u
.legacy
.fmask
.slice_tile_max
-= 1;
886 surf
->u
.legacy
.fmask
.tiling_index
= fout
.tileIndex
;
887 surf
->u
.legacy
.fmask
.bankh
= fout
.pTileInfo
->bankHeight
;
888 surf
->u
.legacy
.fmask
.pitch_in_pixels
= fout
.pitch
;
889 surf
->u
.legacy
.fmask
.slice_size
= fout
.sliceSize
;
891 /* Compute tile swizzle for FMASK. */
892 if (config
->info
.fmask_surf_index
&&
893 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
894 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin
= {0};
895 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout
= {0};
897 xin
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
898 xout
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
900 /* This counter starts from 1 instead of 0. */
901 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
902 xin
.tileIndex
= fout
.tileIndex
;
903 xin
.macroModeIndex
= fout
.macroModeIndex
;
904 xin
.pTileInfo
= fout
.pTileInfo
;
905 xin
.tileMode
= fin
.tileMode
;
907 int r
= AddrComputeBaseSwizzle(addrlib
, &xin
, &xout
);
911 assert(xout
.tileSwizzle
<=
912 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
913 surf
->fmask_tile_swizzle
= xout
.tileSwizzle
;
917 /* Recalculate the whole DCC miptree size including disabled levels.
918 * This is what addrlib does, but calling addrlib would be a lot more
921 if (surf
->dcc_size
&& config
->info
.levels
> 1) {
922 /* The smallest miplevels that are never compressed by DCC
923 * still read the DCC buffer via TC if the base level uses DCC,
924 * and for some reason the DCC buffer needs to be larger if
925 * the miptree uses non-zero tile_swizzle. Otherwise there are
928 * "dcc_alignment * 4" was determined by trial and error.
930 surf
->dcc_size
= align64(surf
->surf_size
>> 8,
931 surf
->dcc_alignment
* 4);
934 /* Make sure HTILE covers the whole miptree, because the shader reads
935 * TC-compatible HTILE even for levels where it's disabled by DB.
937 if (surf
->htile_size
&& config
->info
.levels
> 1 &&
938 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) {
939 /* MSAA can't occur with levels > 1, so ignore the sample count. */
940 const unsigned total_pixels
= surf
->surf_size
/ surf
->bpe
;
941 const unsigned htile_block_size
= 8 * 8;
942 const unsigned htile_element_size
= 4;
944 surf
->htile_size
= (total_pixels
/ htile_block_size
) *
946 surf
->htile_size
= align(surf
->htile_size
, surf
->htile_alignment
);
949 surf
->is_linear
= surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
;
950 surf
->is_displayable
= surf
->is_linear
||
951 surf
->micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
||
952 surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
;
954 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
955 * used at the same time. This case is not currently expected to occur
956 * because we don't use rotated. Enforce this restriction on all chips
957 * to facilitate testing.
959 if (surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
) {
960 assert(!"rotate micro tile mode is unsupported");
964 ac_compute_cmask(info
, config
, surf
);
968 /* This is only called when expecting a tiled layout. */
970 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib
,
971 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
,
972 bool is_fmask
, AddrSwizzleMode
*swizzle_mode
)
974 ADDR_E_RETURNCODE ret
;
975 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin
= {0};
976 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout
= {0};
978 sin
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
);
979 sout
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
);
981 sin
.flags
= in
->flags
;
982 sin
.resourceType
= in
->resourceType
;
983 sin
.format
= in
->format
;
984 sin
.resourceLoction
= ADDR_RSRC_LOC_INVIS
;
985 /* TODO: We could allow some of these: */
986 sin
.forbiddenBlock
.micro
= 1; /* don't allow the 256B swizzle modes */
987 sin
.forbiddenBlock
.var
= 1; /* don't allow the variable-sized swizzle modes */
989 sin
.width
= in
->width
;
990 sin
.height
= in
->height
;
991 sin
.numSlices
= in
->numSlices
;
992 sin
.numMipLevels
= in
->numMipLevels
;
993 sin
.numSamples
= in
->numSamples
;
994 sin
.numFrags
= in
->numFrags
;
997 sin
.flags
.display
= 0;
1002 ret
= Addr2GetPreferredSurfaceSetting(addrlib
, &sin
, &sout
);
1006 *swizzle_mode
= sout
.swizzleMode
;
1010 static bool gfx9_is_dcc_capable(const struct radeon_info
*info
, unsigned sw_mode
)
1012 if (info
->chip_class
>= GFX10
)
1013 return sw_mode
== ADDR_SW_64KB_Z_X
|| sw_mode
== ADDR_SW_64KB_R_X
;
1015 return sw_mode
!= ADDR_SW_LINEAR
;
1018 static int gfx9_compute_miptree(ADDR_HANDLE addrlib
,
1019 const struct radeon_info
*info
,
1020 const struct ac_surf_config
*config
,
1021 struct radeon_surf
*surf
, bool compressed
,
1022 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
)
1024 ADDR2_MIP_INFO mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1025 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out
= {0};
1026 ADDR_E_RETURNCODE ret
;
1028 out
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
);
1029 out
.pMipInfo
= mip_info
;
1031 ret
= Addr2ComputeSurfaceInfo(addrlib
, in
, &out
);
1035 if (in
->flags
.stencil
) {
1036 surf
->u
.gfx9
.stencil
.swizzle_mode
= in
->swizzleMode
;
1037 surf
->u
.gfx9
.stencil
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1038 out
.mipChainPitch
- 1;
1039 surf
->surf_alignment
= MAX2(surf
->surf_alignment
, out
.baseAlign
);
1040 surf
->u
.gfx9
.stencil_offset
= align(surf
->surf_size
, out
.baseAlign
);
1041 surf
->surf_size
= surf
->u
.gfx9
.stencil_offset
+ out
.surfSize
;
1045 surf
->u
.gfx9
.surf
.swizzle_mode
= in
->swizzleMode
;
1046 surf
->u
.gfx9
.surf
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1047 out
.mipChainPitch
- 1;
1049 /* CMASK fast clear uses these even if FMASK isn't allocated.
1050 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1052 surf
->u
.gfx9
.fmask
.swizzle_mode
= surf
->u
.gfx9
.surf
.swizzle_mode
& ~0x3;
1053 surf
->u
.gfx9
.fmask
.epitch
= surf
->u
.gfx9
.surf
.epitch
;
1055 surf
->u
.gfx9
.surf_slice_size
= out
.sliceSize
;
1056 surf
->u
.gfx9
.surf_pitch
= out
.pitch
;
1057 surf
->u
.gfx9
.surf_height
= out
.height
;
1058 surf
->surf_size
= out
.surfSize
;
1059 surf
->surf_alignment
= out
.baseAlign
;
1061 if (in
->swizzleMode
== ADDR_SW_LINEAR
) {
1062 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++)
1063 surf
->u
.gfx9
.offset
[i
] = mip_info
[i
].offset
;
1066 if (in
->flags
.depth
) {
1067 assert(in
->swizzleMode
!= ADDR_SW_LINEAR
);
1069 if (surf
->flags
& RADEON_SURF_NO_HTILE
)
1073 ADDR2_COMPUTE_HTILE_INFO_INPUT hin
= {0};
1074 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout
= {0};
1076 hin
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT
);
1077 hout
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT
);
1079 hin
.hTileFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1080 hin
.hTileFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1081 hin
.depthFlags
= in
->flags
;
1082 hin
.swizzleMode
= in
->swizzleMode
;
1083 hin
.unalignedWidth
= in
->width
;
1084 hin
.unalignedHeight
= in
->height
;
1085 hin
.numSlices
= in
->numSlices
;
1086 hin
.numMipLevels
= in
->numMipLevels
;
1087 hin
.firstMipIdInTail
= out
.firstMipIdInTail
;
1089 ret
= Addr2ComputeHtileInfo(addrlib
, &hin
, &hout
);
1093 surf
->u
.gfx9
.htile
.rb_aligned
= hin
.hTileFlags
.rbAligned
;
1094 surf
->u
.gfx9
.htile
.pipe_aligned
= hin
.hTileFlags
.pipeAligned
;
1095 surf
->htile_size
= hout
.htileBytes
;
1096 surf
->htile_slice_size
= hout
.sliceSize
;
1097 surf
->htile_alignment
= hout
.baseAlign
;
1102 /* Compute tile swizzle for the color surface.
1103 * All *_X and *_T modes can use the swizzle.
1105 if (config
->info
.surf_index
&&
1106 in
->swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1107 !out
.mipChainInTail
&&
1108 !(surf
->flags
& RADEON_SURF_SHAREABLE
) &&
1109 !in
->flags
.display
) {
1110 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1111 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1113 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1114 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1116 xin
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
1117 xin
.flags
= in
->flags
;
1118 xin
.swizzleMode
= in
->swizzleMode
;
1119 xin
.resourceType
= in
->resourceType
;
1120 xin
.format
= in
->format
;
1121 xin
.numSamples
= in
->numSamples
;
1122 xin
.numFrags
= in
->numFrags
;
1124 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1128 assert(xout
.pipeBankXor
<=
1129 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
1130 surf
->tile_swizzle
= xout
.pipeBankXor
;
1134 if (info
->has_graphics
&&
1135 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
1137 gfx9_is_dcc_capable(info
, in
->swizzleMode
)) {
1138 ADDR2_COMPUTE_DCCINFO_INPUT din
= {0};
1139 ADDR2_COMPUTE_DCCINFO_OUTPUT dout
= {0};
1140 ADDR2_META_MIP_INFO meta_mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1142 din
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_INPUT
);
1143 dout
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT
);
1144 dout
.pMipInfo
= meta_mip_info
;
1146 din
.dccKeyFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1147 din
.dccKeyFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1148 din
.colorFlags
= in
->flags
;
1149 din
.resourceType
= in
->resourceType
;
1150 din
.swizzleMode
= in
->swizzleMode
;
1152 din
.unalignedWidth
= in
->width
;
1153 din
.unalignedHeight
= in
->height
;
1154 din
.numSlices
= in
->numSlices
;
1155 din
.numFrags
= in
->numFrags
;
1156 din
.numMipLevels
= in
->numMipLevels
;
1157 din
.dataSurfaceSize
= out
.surfSize
;
1158 din
.firstMipIdInTail
= out
.firstMipIdInTail
;
1160 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1164 surf
->u
.gfx9
.dcc
.rb_aligned
= din
.dccKeyFlags
.rbAligned
;
1165 surf
->u
.gfx9
.dcc
.pipe_aligned
= din
.dccKeyFlags
.pipeAligned
;
1166 surf
->dcc_size
= dout
.dccRamSize
;
1167 surf
->dcc_alignment
= dout
.dccRamBaseAlign
;
1168 surf
->num_dcc_levels
= in
->numMipLevels
;
1170 /* Disable DCC for levels that are in the mip tail.
1172 * There are two issues that this is intended to
1175 * 1. Multiple mip levels may share a cache line. This
1176 * can lead to corruption when switching between
1177 * rendering to different mip levels because the
1178 * RBs don't maintain coherency.
1180 * 2. Texturing with metadata after rendering sometimes
1181 * fails with corruption, probably for a similar
1184 * Working around these issues for all levels in the
1185 * mip tail may be overly conservative, but it's what
1188 * Alternative solutions that also work but are worse:
1189 * - Disable DCC entirely.
1190 * - Flush TC L2 after rendering.
1192 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++) {
1193 if (meta_mip_info
[i
].inMiptail
) {
1194 surf
->num_dcc_levels
= i
;
1199 if (!surf
->num_dcc_levels
)
1202 surf
->u
.gfx9
.display_dcc_size
= surf
->dcc_size
;
1203 surf
->u
.gfx9
.display_dcc_alignment
= surf
->dcc_alignment
;
1204 surf
->u
.gfx9
.display_dcc_pitch_max
= dout
.pitch
- 1;
1206 /* Compute displayable DCC. */
1207 if (in
->flags
.display
&&
1208 surf
->num_dcc_levels
&&
1209 info
->use_display_dcc_with_retile_blit
) {
1210 /* Compute displayable DCC info. */
1211 din
.dccKeyFlags
.pipeAligned
= 0;
1212 din
.dccKeyFlags
.rbAligned
= 0;
1214 assert(din
.numSlices
== 1);
1215 assert(din
.numMipLevels
== 1);
1216 assert(din
.numFrags
== 1);
1217 assert(surf
->tile_swizzle
== 0);
1218 assert(surf
->u
.gfx9
.dcc
.pipe_aligned
||
1219 surf
->u
.gfx9
.dcc
.rb_aligned
);
1221 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1225 surf
->u
.gfx9
.display_dcc_size
= dout
.dccRamSize
;
1226 surf
->u
.gfx9
.display_dcc_alignment
= dout
.dccRamBaseAlign
;
1227 surf
->u
.gfx9
.display_dcc_pitch_max
= dout
.pitch
- 1;
1228 assert(surf
->u
.gfx9
.display_dcc_size
<= surf
->dcc_size
);
1230 /* Compute address mapping from non-displayable to displayable DCC. */
1231 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin
= {};
1232 addrin
.size
= sizeof(addrin
);
1233 addrin
.colorFlags
.color
= 1;
1234 addrin
.swizzleMode
= din
.swizzleMode
;
1235 addrin
.resourceType
= din
.resourceType
;
1236 addrin
.bpp
= din
.bpp
;
1237 addrin
.unalignedWidth
= din
.unalignedWidth
;
1238 addrin
.unalignedHeight
= din
.unalignedHeight
;
1239 addrin
.numSlices
= 1;
1240 addrin
.numMipLevels
= 1;
1241 addrin
.numFrags
= 1;
1243 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout
= {};
1244 addrout
.size
= sizeof(addrout
);
1246 surf
->u
.gfx9
.dcc_retile_num_elements
=
1247 DIV_ROUND_UP(in
->width
, dout
.compressBlkWidth
) *
1248 DIV_ROUND_UP(in
->height
, dout
.compressBlkHeight
) * 2;
1249 /* Align the size to 4 (for the compute shader). */
1250 surf
->u
.gfx9
.dcc_retile_num_elements
=
1251 align(surf
->u
.gfx9
.dcc_retile_num_elements
, 4);
1253 surf
->u
.gfx9
.dcc_retile_map
=
1254 malloc(surf
->u
.gfx9
.dcc_retile_num_elements
* 4);
1255 if (!surf
->u
.gfx9
.dcc_retile_map
)
1256 return ADDR_OUTOFMEMORY
;
1259 surf
->u
.gfx9
.dcc_retile_use_uint16
= true;
1261 for (unsigned y
= 0; y
< in
->height
; y
+= dout
.compressBlkHeight
) {
1264 for (unsigned x
= 0; x
< in
->width
; x
+= dout
.compressBlkWidth
) {
1267 /* Compute src DCC address */
1268 addrin
.dccKeyFlags
.pipeAligned
= surf
->u
.gfx9
.dcc
.pipe_aligned
;
1269 addrin
.dccKeyFlags
.rbAligned
= surf
->u
.gfx9
.dcc
.rb_aligned
;
1272 ret
= Addr2ComputeDccAddrFromCoord(addrlib
, &addrin
, &addrout
);
1276 surf
->u
.gfx9
.dcc_retile_map
[index
* 2] = addrout
.addr
;
1277 if (addrout
.addr
> UINT16_MAX
)
1278 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1280 /* Compute dst DCC address */
1281 addrin
.dccKeyFlags
.pipeAligned
= 0;
1282 addrin
.dccKeyFlags
.rbAligned
= 0;
1285 ret
= Addr2ComputeDccAddrFromCoord(addrlib
, &addrin
, &addrout
);
1289 surf
->u
.gfx9
.dcc_retile_map
[index
* 2 + 1] = addrout
.addr
;
1290 if (addrout
.addr
> UINT16_MAX
)
1291 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1293 assert(index
* 2 + 1 < surf
->u
.gfx9
.dcc_retile_num_elements
);
1297 /* Fill the remaining pairs with the last one (for the compute shader). */
1298 for (unsigned i
= index
* 2; i
< surf
->u
.gfx9
.dcc_retile_num_elements
; i
++)
1299 surf
->u
.gfx9
.dcc_retile_map
[i
] = surf
->u
.gfx9
.dcc_retile_map
[i
- 2];
1304 if (in
->numSamples
> 1 && !(surf
->flags
& RADEON_SURF_NO_FMASK
)) {
1305 ADDR2_COMPUTE_FMASK_INFO_INPUT fin
= {0};
1306 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
1308 fin
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT
);
1309 fout
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT
);
1311 ret
= gfx9_get_preferred_swizzle_mode(addrlib
, in
,
1312 true, &fin
.swizzleMode
);
1316 fin
.unalignedWidth
= in
->width
;
1317 fin
.unalignedHeight
= in
->height
;
1318 fin
.numSlices
= in
->numSlices
;
1319 fin
.numSamples
= in
->numSamples
;
1320 fin
.numFrags
= in
->numFrags
;
1322 ret
= Addr2ComputeFmaskInfo(addrlib
, &fin
, &fout
);
1326 surf
->u
.gfx9
.fmask
.swizzle_mode
= fin
.swizzleMode
;
1327 surf
->u
.gfx9
.fmask
.epitch
= fout
.pitch
- 1;
1328 surf
->fmask_size
= fout
.fmaskBytes
;
1329 surf
->fmask_alignment
= fout
.baseAlign
;
1331 /* Compute tile swizzle for the FMASK surface. */
1332 if (config
->info
.fmask_surf_index
&&
1333 fin
.swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1334 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
1335 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1336 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1338 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1339 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1341 /* This counter starts from 1 instead of 0. */
1342 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
1343 xin
.flags
= in
->flags
;
1344 xin
.swizzleMode
= fin
.swizzleMode
;
1345 xin
.resourceType
= in
->resourceType
;
1346 xin
.format
= in
->format
;
1347 xin
.numSamples
= in
->numSamples
;
1348 xin
.numFrags
= in
->numFrags
;
1350 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1354 assert(xout
.pipeBankXor
<=
1355 u_bit_consecutive(0, sizeof(surf
->fmask_tile_swizzle
) * 8));
1356 surf
->fmask_tile_swizzle
= xout
.pipeBankXor
;
1360 /* CMASK -- on GFX10 only for FMASK */
1361 if (in
->swizzleMode
!= ADDR_SW_LINEAR
&&
1362 ((info
->chip_class
<= GFX9
&& in
->numSamples
== 1) ||
1363 (surf
->fmask_size
&& in
->numSamples
>= 2))) {
1364 ADDR2_COMPUTE_CMASK_INFO_INPUT cin
= {0};
1365 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout
= {0};
1367 cin
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT
);
1368 cout
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT
);
1370 if (in
->numSamples
> 1) {
1371 /* FMASK is always aligned. */
1372 cin
.cMaskFlags
.pipeAligned
= 1;
1373 cin
.cMaskFlags
.rbAligned
= 1;
1375 cin
.cMaskFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1376 cin
.cMaskFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1378 cin
.colorFlags
= in
->flags
;
1379 cin
.resourceType
= in
->resourceType
;
1380 cin
.unalignedWidth
= in
->width
;
1381 cin
.unalignedHeight
= in
->height
;
1382 cin
.numSlices
= in
->numSlices
;
1384 if (in
->numSamples
> 1)
1385 cin
.swizzleMode
= surf
->u
.gfx9
.fmask
.swizzle_mode
;
1387 cin
.swizzleMode
= in
->swizzleMode
;
1389 ret
= Addr2ComputeCmaskInfo(addrlib
, &cin
, &cout
);
1393 surf
->u
.gfx9
.cmask
.rb_aligned
= cin
.cMaskFlags
.rbAligned
;
1394 surf
->u
.gfx9
.cmask
.pipe_aligned
= cin
.cMaskFlags
.pipeAligned
;
1395 surf
->cmask_size
= cout
.cmaskBytes
;
1396 surf
->cmask_alignment
= cout
.baseAlign
;
1403 static int gfx9_compute_surface(ADDR_HANDLE addrlib
,
1404 const struct radeon_info
*info
,
1405 const struct ac_surf_config
*config
,
1406 enum radeon_surf_mode mode
,
1407 struct radeon_surf
*surf
)
1410 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
1413 AddrSurfInfoIn
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT
);
1415 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
1417 /* The format must be set correctly for the allocation of compressed
1418 * textures to work. In other cases, setting the bpp is sufficient. */
1420 switch (surf
->bpe
) {
1422 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
1425 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
1431 switch (surf
->bpe
) {
1433 assert(!(surf
->flags
& RADEON_SURF_ZBUFFER
));
1434 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1437 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1438 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1439 AddrSurfInfoIn
.format
= ADDR_FMT_16
;
1442 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1443 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1444 AddrSurfInfoIn
.format
= ADDR_FMT_32
;
1447 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1448 AddrSurfInfoIn
.format
= ADDR_FMT_32_32
;
1451 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1452 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32
;
1455 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1456 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32_32
;
1461 AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
1464 bool is_color_surface
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
1465 AddrSurfInfoIn
.flags
.color
= is_color_surface
&&
1466 !(surf
->flags
& RADEON_SURF_NO_RENDER_TARGET
);
1467 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
1468 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
1469 /* flags.texture currently refers to TC-compatible HTILE */
1470 AddrSurfInfoIn
.flags
.texture
= is_color_surface
||
1471 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1472 AddrSurfInfoIn
.flags
.opt4space
= 1;
1474 AddrSurfInfoIn
.numMipLevels
= config
->info
.levels
;
1475 AddrSurfInfoIn
.numSamples
= MAX2(1, config
->info
.samples
);
1476 AddrSurfInfoIn
.numFrags
= AddrSurfInfoIn
.numSamples
;
1478 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
))
1479 AddrSurfInfoIn
.numFrags
= MAX2(1, config
->info
.storage_samples
);
1481 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1482 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1483 * must sample 1D textures as 2D. */
1485 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_3D
;
1486 else if (info
->chip_class
!= GFX9
&& config
->is_1d
)
1487 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_1D
;
1489 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_2D
;
1491 AddrSurfInfoIn
.width
= config
->info
.width
;
1492 AddrSurfInfoIn
.height
= config
->info
.height
;
1495 AddrSurfInfoIn
.numSlices
= config
->info
.depth
;
1496 else if (config
->is_cube
)
1497 AddrSurfInfoIn
.numSlices
= 6;
1499 AddrSurfInfoIn
.numSlices
= config
->info
.array_size
;
1501 /* This is propagated to HTILE/DCC/CMASK. */
1502 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 0;
1503 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 0;
1505 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1506 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1508 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1509 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1510 * after rendering, so PIPE_ALIGNED=1 is recommended.
1512 if (info
->use_display_dcc_unaligned
&& is_color_surface
&&
1513 AddrSurfInfoIn
.flags
.display
) {
1514 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 1;
1515 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 1;
1519 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1520 assert(config
->info
.samples
<= 1);
1521 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1522 AddrSurfInfoIn
.swizzleMode
= ADDR_SW_LINEAR
;
1525 case RADEON_SURF_MODE_1D
:
1526 case RADEON_SURF_MODE_2D
:
1527 if (surf
->flags
& (RADEON_SURF_IMPORTED
| RADEON_SURF_FORCE_SWIZZLE_MODE
)) {
1528 AddrSurfInfoIn
.swizzleMode
= surf
->u
.gfx9
.surf
.swizzle_mode
;
1532 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1533 false, &AddrSurfInfoIn
.swizzleMode
);
1542 surf
->u
.gfx9
.resource_type
= AddrSurfInfoIn
.resourceType
;
1543 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
1545 surf
->num_dcc_levels
= 0;
1546 surf
->surf_size
= 0;
1547 surf
->fmask_size
= 0;
1549 surf
->htile_size
= 0;
1550 surf
->htile_slice_size
= 0;
1551 surf
->u
.gfx9
.surf_offset
= 0;
1552 surf
->u
.gfx9
.stencil_offset
= 0;
1553 surf
->cmask_size
= 0;
1554 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1555 surf
->u
.gfx9
.dcc_retile_num_elements
= 0;
1556 surf
->u
.gfx9
.dcc_retile_map
= NULL
;
1558 /* Calculate texture layout information. */
1559 r
= gfx9_compute_miptree(addrlib
, info
, config
, surf
, compressed
,
1564 /* Calculate texture layout information for stencil. */
1565 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
1566 AddrSurfInfoIn
.flags
.stencil
= 1;
1567 AddrSurfInfoIn
.bpp
= 8;
1568 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1570 if (!AddrSurfInfoIn
.flags
.depth
) {
1571 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1572 false, &AddrSurfInfoIn
.swizzleMode
);
1576 AddrSurfInfoIn
.flags
.depth
= 0;
1578 r
= gfx9_compute_miptree(addrlib
, info
, config
, surf
, compressed
,
1584 surf
->is_linear
= surf
->u
.gfx9
.surf
.swizzle_mode
== ADDR_SW_LINEAR
;
1586 /* Query whether the surface is displayable. */
1587 bool displayable
= false;
1588 if (!config
->is_3d
&& !config
->is_cube
) {
1589 r
= Addr2IsValidDisplaySwizzleMode(addrlib
, surf
->u
.gfx9
.surf
.swizzle_mode
,
1590 surf
->bpe
* 8, &displayable
);
1594 /* Display needs unaligned DCC. */
1595 if (info
->use_display_dcc_unaligned
&&
1596 surf
->num_dcc_levels
&&
1597 (surf
->u
.gfx9
.dcc
.pipe_aligned
||
1598 surf
->u
.gfx9
.dcc
.rb_aligned
))
1599 displayable
= false;
1601 surf
->is_displayable
= displayable
;
1603 switch (surf
->u
.gfx9
.surf
.swizzle_mode
) {
1605 case ADDR_SW_256B_S
:
1607 case ADDR_SW_64KB_S
:
1609 case ADDR_SW_64KB_S_T
:
1610 case ADDR_SW_4KB_S_X
:
1611 case ADDR_SW_64KB_S_X
:
1612 case ADDR_SW_VAR_S_X
:
1613 surf
->micro_tile_mode
= RADEON_MICRO_MODE_THIN
;
1617 case ADDR_SW_LINEAR
:
1618 case ADDR_SW_256B_D
:
1620 case ADDR_SW_64KB_D
:
1622 case ADDR_SW_64KB_D_T
:
1623 case ADDR_SW_4KB_D_X
:
1624 case ADDR_SW_64KB_D_X
:
1625 case ADDR_SW_VAR_D_X
:
1626 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DISPLAY
;
1629 /* R = rotated (gfx9), render target (gfx10). */
1630 case ADDR_SW_256B_R
:
1632 case ADDR_SW_64KB_R
:
1634 case ADDR_SW_64KB_R_T
:
1635 case ADDR_SW_4KB_R_X
:
1636 case ADDR_SW_64KB_R_X
:
1637 case ADDR_SW_VAR_R_X
:
1638 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1639 * used at the same time. We currently do not use rotated
1642 assert(info
->chip_class
>= GFX10
||
1643 !"rotate micro tile mode is unsupported");
1644 surf
->micro_tile_mode
= RADEON_MICRO_MODE_ROTATED
;
1649 case ADDR_SW_64KB_Z
:
1651 case ADDR_SW_64KB_Z_T
:
1652 case ADDR_SW_4KB_Z_X
:
1653 case ADDR_SW_64KB_Z_X
:
1654 case ADDR_SW_VAR_Z_X
:
1655 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DEPTH
;
1665 free(surf
->u
.gfx9
.dcc_retile_map
);
1666 surf
->u
.gfx9
.dcc_retile_map
= NULL
;
1670 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
1671 const struct ac_surf_config
*config
,
1672 enum radeon_surf_mode mode
,
1673 struct radeon_surf
*surf
)
1677 r
= surf_config_sanity(config
, surf
->flags
);
1681 if (info
->chip_class
>= GFX9
)
1682 return gfx9_compute_surface(addrlib
, info
, config
, mode
, surf
);
1684 return gfx6_compute_surface(addrlib
, info
, config
, mode
, surf
);