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ac/surface: add RADEON_SURF_NO_FMASK
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/inc/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
53 {
54 return malloc(pInput->sizeInBytes);
55 }
56
57 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
58 {
59 free(pInput->pVirtAddr);
60 return ADDR_OK;
61 }
62
63 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
64 const struct amdgpu_gpu_info *amdinfo,
65 uint64_t *max_alignment)
66 {
67 ADDR_CREATE_INPUT addrCreateInput = {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
69 ADDR_REGISTER_VALUE regValue = {0};
70 ADDR_CREATE_FLAGS createFlags = {{0}};
71 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
72 ADDR_E_RETURNCODE addrRet;
73
74 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
75 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
76
77 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
78 createFlags.value = 0;
79
80 addrCreateInput.chipFamily = info->family_id;
81 addrCreateInput.chipRevision = info->chip_external_rev;
82
83 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
84 return NULL;
85
86 if (addrCreateInput.chipFamily >= FAMILY_AI) {
87 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
88 regValue.blockVarSizeLog2 = 0;
89 } else {
90 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
91 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
92
93 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
94 regValue.pTileConfig = amdinfo->gb_tile_mode;
95 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
96 if (addrCreateInput.chipFamily == FAMILY_SI) {
97 regValue.pMacroTileConfig = NULL;
98 regValue.noOfMacroEntries = 0;
99 } else {
100 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
101 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
102 }
103
104 createFlags.useTileIndex = 1;
105 createFlags.useHtileSliceAlign = 1;
106
107 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
108 }
109
110 addrCreateInput.callbacks.allocSysMem = allocSysMem;
111 addrCreateInput.callbacks.freeSysMem = freeSysMem;
112 addrCreateInput.callbacks.debugPrint = 0;
113 addrCreateInput.createFlags = createFlags;
114 addrCreateInput.regValue = regValue;
115
116 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
117 if (addrRet != ADDR_OK)
118 return NULL;
119
120 if (max_alignment) {
121 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
122 if (addrRet == ADDR_OK){
123 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
124 }
125 }
126 return addrCreateOutput.hLib;
127 }
128
129 static int surf_config_sanity(const struct ac_surf_config *config,
130 unsigned flags)
131 {
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
134 */
135 assert(!(flags & RADEON_SURF_FMASK));
136 if (flags & RADEON_SURF_FMASK)
137 return -EINVAL;
138
139 /* all dimension must be at least 1 ! */
140 if (!config->info.width || !config->info.height || !config->info.depth ||
141 !config->info.array_size || !config->info.levels)
142 return -EINVAL;
143
144 switch (config->info.samples) {
145 case 0:
146 case 1:
147 case 2:
148 case 4:
149 case 8:
150 break;
151 case 16:
152 if (flags & RADEON_SURF_Z_OR_SBUFFER)
153 return -EINVAL;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
160 switch (config->info.storage_samples) {
161 case 0:
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 break;
167 default:
168 return -EINVAL;
169 }
170 }
171
172 if (config->is_3d && config->info.array_size > 1)
173 return -EINVAL;
174 if (config->is_cube && config->info.depth > 1)
175 return -EINVAL;
176
177 return 0;
178 }
179
180 static int gfx6_compute_level(ADDR_HANDLE addrlib,
181 const struct ac_surf_config *config,
182 struct radeon_surf *surf, bool is_stencil,
183 unsigned level, bool compressed,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
186 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
187 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
188 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
190 {
191 struct legacy_surf_level *surf_level;
192 ADDR_E_RETURNCODE ret;
193
194 AddrSurfInfoIn->mipLevel = level;
195 AddrSurfInfoIn->width = u_minify(config->info.width, level);
196 AddrSurfInfoIn->height = u_minify(config->info.height, level);
197
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
200 */
201 if (config->info.levels == 1 &&
202 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
203 AddrSurfInfoIn->bpp &&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
205 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
206
207 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
208 }
209
210 if (config->is_3d)
211 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
212 else if (config->is_cube)
213 AddrSurfInfoIn->numSlices = 6;
214 else
215 AddrSurfInfoIn->numSlices = config->info.array_size;
216
217 if (level > 0) {
218 /* Set the base level pitch. This is needed for calculation
219 * of non-zero levels. */
220 if (is_stencil)
221 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
222 else
223 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
224
225 /* Convert blocks to pixels for compressed formats. */
226 if (compressed)
227 AddrSurfInfoIn->basePitch *= surf->blk_w;
228 }
229
230 ret = AddrComputeSurfaceInfo(addrlib,
231 AddrSurfInfoIn,
232 AddrSurfInfoOut);
233 if (ret != ADDR_OK) {
234 return ret;
235 }
236
237 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
238 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
239 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
240 surf_level->nblk_x = AddrSurfInfoOut->pitch;
241 surf_level->nblk_y = AddrSurfInfoOut->height;
242
243 switch (AddrSurfInfoOut->tileMode) {
244 case ADDR_TM_LINEAR_ALIGNED:
245 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
246 break;
247 case ADDR_TM_1D_TILED_THIN1:
248 surf_level->mode = RADEON_SURF_MODE_1D;
249 break;
250 case ADDR_TM_2D_TILED_THIN1:
251 surf_level->mode = RADEON_SURF_MODE_2D;
252 break;
253 default:
254 assert(0);
255 }
256
257 if (is_stencil)
258 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
259 else
260 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
261
262 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
263
264 /* Clear DCC fields at the beginning. */
265 surf_level->dcc_offset = 0;
266
267 /* The previous level's flag tells us if we can use DCC for this level. */
268 if (AddrSurfInfoIn->flags.dccCompatible &&
269 (level == 0 || AddrDccOut->subLvlCompressible)) {
270 bool prev_level_clearable = level == 0 ||
271 AddrDccOut->dccRamSizeAligned;
272
273 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
274 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
275 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
276 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
277 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
278
279 ret = AddrComputeDccInfo(addrlib,
280 AddrDccIn,
281 AddrDccOut);
282
283 if (ret == ADDR_OK) {
284 surf_level->dcc_offset = surf->dcc_size;
285 surf->num_dcc_levels = level + 1;
286 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
287 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
288
289 /* If the DCC size of a subresource (1 mip level or 1 slice)
290 * is not aligned, the DCC memory layout is not contiguous for
291 * that subresource, which means we can't use fast clear.
292 *
293 * We only do fast clears for whole mipmap levels. If we did
294 * per-slice fast clears, the same restriction would apply.
295 * (i.e. only compute the slice size and see if it's aligned)
296 *
297 * The last level can be non-contiguous and still be clearable
298 * if it's interleaved with the next level that doesn't exist.
299 */
300 if (AddrDccOut->dccRamSizeAligned ||
301 (prev_level_clearable && level == config->info.levels - 1))
302 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
303 else
304 surf_level->dcc_fast_clear_size = 0;
305
306 /* Compute the DCC slice size because addrlib doesn't
307 * provide this info. As DCC memory is linear (each
308 * slice is the same size) it's easy to compute.
309 */
310 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
311
312 /* For arrays, we have to compute the DCC info again
313 * with one slice size to get a correct fast clear
314 * size.
315 */
316 if (config->info.array_size > 1) {
317 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
318 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
319 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
320 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
321 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
322
323 ret = AddrComputeDccInfo(addrlib,
324 AddrDccIn, AddrDccOut);
325 if (ret == ADDR_OK) {
326 /* If the DCC memory isn't properly
327 * aligned, the data are interleaved
328 * accross slices.
329 */
330 if (AddrDccOut->dccRamSizeAligned)
331 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
332 else
333 surf_level->dcc_slice_fast_clear_size = 0;
334 }
335 } else {
336 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
337 }
338 }
339 }
340
341 /* TC-compatible HTILE. */
342 if (!is_stencil &&
343 AddrSurfInfoIn->flags.depth &&
344 surf_level->mode == RADEON_SURF_MODE_2D &&
345 level == 0) {
346 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
347 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
348 AddrHtileIn->height = AddrSurfInfoOut->height;
349 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
350 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
351 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
352 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
353 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
354 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
355
356 ret = AddrComputeHtileInfo(addrlib,
357 AddrHtileIn,
358 AddrHtileOut);
359
360 if (ret == ADDR_OK) {
361 surf->htile_size = AddrHtileOut->htileBytes;
362 surf->htile_slice_size = AddrHtileOut->sliceSize;
363 surf->htile_alignment = AddrHtileOut->baseAlign;
364 }
365 }
366
367 return 0;
368 }
369
370 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
371 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
372 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
373
374 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
375 const struct radeon_info *info)
376 {
377 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
378
379 if (info->chip_class >= GFX7)
380 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
381 else
382 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
383 }
384
385 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
386 {
387 unsigned index, tileb;
388
389 tileb = 8 * 8 * surf->bpe;
390 tileb = MIN2(surf->u.legacy.tile_split, tileb);
391
392 for (index = 0; tileb > 64; index++)
393 tileb >>= 1;
394
395 assert(index < 16);
396 return index;
397 }
398
399 static bool get_display_flag(const struct ac_surf_config *config,
400 const struct radeon_surf *surf)
401 {
402 unsigned num_channels = config->info.num_channels;
403 unsigned bpe = surf->bpe;
404
405 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
406 surf->flags & RADEON_SURF_SCANOUT &&
407 config->info.samples <= 1 &&
408 surf->blk_w <= 2 && surf->blk_h == 1) {
409 /* subsampled */
410 if (surf->blk_w == 2 && surf->blk_h == 1)
411 return true;
412
413 if (/* RGBA8 or RGBA16F */
414 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
415 /* R5G6B5 or R5G5B5A1 */
416 (bpe == 2 && num_channels >= 3) ||
417 /* C8 palette */
418 (bpe == 1 && num_channels == 1))
419 return true;
420 }
421 return false;
422 }
423
424 /**
425 * This must be called after the first level is computed.
426 *
427 * Copy surface-global settings like pipe/bank config from level 0 surface
428 * computation, and compute tile swizzle.
429 */
430 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
431 const struct radeon_info *info,
432 const struct ac_surf_config *config,
433 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
434 struct radeon_surf *surf)
435 {
436 surf->surf_alignment = csio->baseAlign;
437 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
438 gfx6_set_micro_tile_mode(surf, info);
439
440 /* For 2D modes only. */
441 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
442 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
443 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
444 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
445 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
446 surf->u.legacy.num_banks = csio->pTileInfo->banks;
447 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
448 } else {
449 surf->u.legacy.macro_tile_index = 0;
450 }
451
452 /* Compute tile swizzle. */
453 /* TODO: fix tile swizzle with mipmapping for GFX6 */
454 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
455 config->info.surf_index &&
456 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
457 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
458 !get_display_flag(config, surf)) {
459 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
460 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
461
462 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
463 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
464
465 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
466 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
467 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
468 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
469 AddrBaseSwizzleIn.tileMode = csio->tileMode;
470
471 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
472 &AddrBaseSwizzleOut);
473 if (r != ADDR_OK)
474 return r;
475
476 assert(AddrBaseSwizzleOut.tileSwizzle <=
477 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
478 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
479 }
480 return 0;
481 }
482
483 static void ac_compute_cmask(const struct radeon_info *info,
484 const struct ac_surf_config *config,
485 struct radeon_surf *surf)
486 {
487 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
488 unsigned num_pipes = info->num_tile_pipes;
489 unsigned cl_width, cl_height;
490
491 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
492 (config->info.samples >= 2 && !surf->fmask_size))
493 return;
494
495 assert(info->chip_class <= GFX8);
496
497 switch (num_pipes) {
498 case 2:
499 cl_width = 32;
500 cl_height = 16;
501 break;
502 case 4:
503 cl_width = 32;
504 cl_height = 32;
505 break;
506 case 8:
507 cl_width = 64;
508 cl_height = 32;
509 break;
510 case 16: /* Hawaii */
511 cl_width = 64;
512 cl_height = 64;
513 break;
514 default:
515 assert(0);
516 return;
517 }
518
519 unsigned base_align = num_pipes * pipe_interleave_bytes;
520
521 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
522 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
523 unsigned slice_elements = (width * height) / (8*8);
524
525 /* Each element of CMASK is a nibble. */
526 unsigned slice_bytes = slice_elements / 2;
527
528 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
529 if (surf->u.legacy.cmask_slice_tile_max)
530 surf->u.legacy.cmask_slice_tile_max -= 1;
531
532 unsigned num_layers;
533 if (config->is_3d)
534 num_layers = config->info.depth;
535 else if (config->is_cube)
536 num_layers = 6;
537 else
538 num_layers = config->info.array_size;
539
540 surf->cmask_alignment = MAX2(256, base_align);
541 surf->cmask_slice_size = align(slice_bytes, base_align);
542 surf->cmask_size = surf->cmask_slice_size * num_layers;
543 }
544
545 /**
546 * Fill in the tiling information in \p surf based on the given surface config.
547 *
548 * The following fields of \p surf must be initialized by the caller:
549 * blk_w, blk_h, bpe, flags.
550 */
551 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
552 const struct radeon_info *info,
553 const struct ac_surf_config *config,
554 enum radeon_surf_mode mode,
555 struct radeon_surf *surf)
556 {
557 unsigned level;
558 bool compressed;
559 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
560 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
561 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
562 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
563 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
564 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
565 ADDR_TILEINFO AddrTileInfoIn = {0};
566 ADDR_TILEINFO AddrTileInfoOut = {0};
567 int r;
568
569 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
570 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
571 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
572 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
573 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
574 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
575 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
576
577 compressed = surf->blk_w == 4 && surf->blk_h == 4;
578
579 /* MSAA requires 2D tiling. */
580 if (config->info.samples > 1)
581 mode = RADEON_SURF_MODE_2D;
582
583 /* DB doesn't support linear layouts. */
584 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
585 mode < RADEON_SURF_MODE_1D)
586 mode = RADEON_SURF_MODE_1D;
587
588 /* Set the requested tiling mode. */
589 switch (mode) {
590 case RADEON_SURF_MODE_LINEAR_ALIGNED:
591 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
592 break;
593 case RADEON_SURF_MODE_1D:
594 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
595 break;
596 case RADEON_SURF_MODE_2D:
597 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
598 break;
599 default:
600 assert(0);
601 }
602
603 /* The format must be set correctly for the allocation of compressed
604 * textures to work. In other cases, setting the bpp is sufficient.
605 */
606 if (compressed) {
607 switch (surf->bpe) {
608 case 8:
609 AddrSurfInfoIn.format = ADDR_FMT_BC1;
610 break;
611 case 16:
612 AddrSurfInfoIn.format = ADDR_FMT_BC3;
613 break;
614 default:
615 assert(0);
616 }
617 }
618 else {
619 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
620 }
621
622 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
623 MAX2(1, config->info.samples);
624 AddrSurfInfoIn.tileIndex = -1;
625
626 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
627 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
628 MAX2(1, config->info.storage_samples);
629 }
630
631 /* Set the micro tile type. */
632 if (surf->flags & RADEON_SURF_SCANOUT)
633 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
634 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
635 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
636 else
637 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
638
639 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
640 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
641 AddrSurfInfoIn.flags.cube = config->is_cube;
642 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
643 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
644 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
645
646 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
647 * requested, because TC-compatible HTILE requires 2D tiling.
648 */
649 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
650 !AddrSurfInfoIn.flags.fmask &&
651 config->info.samples <= 1 &&
652 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
653
654 /* DCC notes:
655 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
656 * with samples >= 4.
657 * - Mipmapped array textures have low performance (discovered by a closed
658 * driver team).
659 */
660 AddrSurfInfoIn.flags.dccCompatible =
661 info->chip_class >= GFX8 &&
662 info->has_graphics && /* disable DCC on compute-only chips */
663 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
664 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
665 !compressed &&
666 ((config->info.array_size == 1 && config->info.depth == 1) ||
667 config->info.levels == 1);
668
669 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
670 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
671
672 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
673 * for Z and stencil. This can cause a number of problems which we work
674 * around here:
675 *
676 * - a depth part that is incompatible with mipmapped texturing
677 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
678 * incorrect tiling applied to the stencil part, stencil buffer
679 * memory accesses that go out of bounds) even without mipmapping
680 *
681 * Some piglit tests that are prone to different types of related
682 * failures:
683 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
684 * ./bin/framebuffer-blit-levels {draw,read} stencil
685 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
686 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
687 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
688 */
689 int stencil_tile_idx = -1;
690
691 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
692 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
693 /* Compute stencilTileIdx that is compatible with the (depth)
694 * tileIdx. This degrades the depth surface if necessary to
695 * ensure that a matching stencilTileIdx exists. */
696 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
697
698 /* Keep the depth mip-tail compatible with texturing. */
699 AddrSurfInfoIn.flags.noStencil = 1;
700 }
701
702 /* Set preferred macrotile parameters. This is usually required
703 * for shared resources. This is for 2D tiling only. */
704 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
705 surf->u.legacy.bankw && surf->u.legacy.bankh &&
706 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
707 /* If any of these parameters are incorrect, the calculation
708 * will fail. */
709 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
710 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
711 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
712 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
713 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
714 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
715 AddrSurfInfoIn.flags.opt4Space = 0;
716 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
717
718 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
719 * the tile index, because we are expected to know it if
720 * we know the other parameters.
721 *
722 * This is something that can easily be fixed in Addrlib.
723 * For now, just figure it out here.
724 * Note that only 2D_TILE_THIN1 is handled here.
725 */
726 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
727 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
728
729 if (info->chip_class == GFX6) {
730 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
731 if (surf->bpe == 2)
732 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
733 else
734 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
735 } else {
736 if (surf->bpe == 1)
737 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
738 else if (surf->bpe == 2)
739 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
740 else if (surf->bpe == 4)
741 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
742 else
743 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
744 }
745 } else {
746 /* GFX7 - GFX8 */
747 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
748 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
749 else
750 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
751
752 /* Addrlib doesn't set this if tileIndex is forced like above. */
753 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
754 }
755 }
756
757 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
758 surf->num_dcc_levels = 0;
759 surf->surf_size = 0;
760 surf->dcc_size = 0;
761 surf->dcc_alignment = 1;
762 surf->htile_size = 0;
763 surf->htile_slice_size = 0;
764 surf->htile_alignment = 1;
765
766 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
767 !(surf->flags & RADEON_SURF_ZBUFFER);
768
769 /* Calculate texture layout information. */
770 if (!only_stencil) {
771 for (level = 0; level < config->info.levels; level++) {
772 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
773 &AddrSurfInfoIn, &AddrSurfInfoOut,
774 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
775 if (r)
776 return r;
777
778 if (level > 0)
779 continue;
780
781 /* Check that we actually got a TC-compatible HTILE if
782 * we requested it (only for level 0, since we're not
783 * supporting HTILE on higher mip levels anyway). */
784 assert(AddrSurfInfoOut.tcCompatible ||
785 !AddrSurfInfoIn.flags.tcCompatible ||
786 AddrSurfInfoIn.flags.matchStencilTileCfg);
787
788 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
789 if (!AddrSurfInfoOut.tcCompatible) {
790 AddrSurfInfoIn.flags.tcCompatible = 0;
791 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
792 }
793
794 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
795 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
796 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
797
798 assert(stencil_tile_idx >= 0);
799 }
800
801 r = gfx6_surface_settings(addrlib, info, config,
802 &AddrSurfInfoOut, surf);
803 if (r)
804 return r;
805 }
806 }
807
808 /* Calculate texture layout information for stencil. */
809 if (surf->flags & RADEON_SURF_SBUFFER) {
810 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
811 AddrSurfInfoIn.bpp = 8;
812 AddrSurfInfoIn.flags.depth = 0;
813 AddrSurfInfoIn.flags.stencil = 1;
814 AddrSurfInfoIn.flags.tcCompatible = 0;
815 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
816 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
817
818 for (level = 0; level < config->info.levels; level++) {
819 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
820 &AddrSurfInfoIn, &AddrSurfInfoOut,
821 &AddrDccIn, &AddrDccOut,
822 NULL, NULL);
823 if (r)
824 return r;
825
826 /* DB uses the depth pitch for both stencil and depth. */
827 if (!only_stencil) {
828 if (surf->u.legacy.stencil_level[level].nblk_x !=
829 surf->u.legacy.level[level].nblk_x)
830 surf->u.legacy.stencil_adjusted = true;
831 } else {
832 surf->u.legacy.level[level].nblk_x =
833 surf->u.legacy.stencil_level[level].nblk_x;
834 }
835
836 if (level == 0) {
837 if (only_stencil) {
838 r = gfx6_surface_settings(addrlib, info, config,
839 &AddrSurfInfoOut, surf);
840 if (r)
841 return r;
842 }
843
844 /* For 2D modes only. */
845 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
846 surf->u.legacy.stencil_tile_split =
847 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
848 }
849 }
850 }
851 }
852
853 /* Compute FMASK. */
854 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
855 !(surf->flags & RADEON_SURF_NO_FMASK)) {
856 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
857 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
858 ADDR_TILEINFO fmask_tile_info = {};
859
860 fin.size = sizeof(fin);
861 fout.size = sizeof(fout);
862
863 fin.tileMode = AddrSurfInfoOut.tileMode;
864 fin.pitch = AddrSurfInfoOut.pitch;
865 fin.height = config->info.height;
866 fin.numSlices = AddrSurfInfoIn.numSlices;
867 fin.numSamples = AddrSurfInfoIn.numSamples;
868 fin.numFrags = AddrSurfInfoIn.numFrags;
869 fin.tileIndex = -1;
870 fout.pTileInfo = &fmask_tile_info;
871
872 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
873 if (r)
874 return r;
875
876 surf->fmask_size = fout.fmaskBytes;
877 surf->fmask_alignment = fout.baseAlign;
878 surf->fmask_tile_swizzle = 0;
879
880 surf->u.legacy.fmask.slice_tile_max =
881 (fout.pitch * fout.height) / 64;
882 if (surf->u.legacy.fmask.slice_tile_max)
883 surf->u.legacy.fmask.slice_tile_max -= 1;
884
885 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
886 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
887 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
888 surf->u.legacy.fmask.slice_size = fout.sliceSize;
889
890 /* Compute tile swizzle for FMASK. */
891 if (config->info.fmask_surf_index &&
892 !(surf->flags & RADEON_SURF_SHAREABLE)) {
893 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
894 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
895
896 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
897 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
898
899 /* This counter starts from 1 instead of 0. */
900 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
901 xin.tileIndex = fout.tileIndex;
902 xin.macroModeIndex = fout.macroModeIndex;
903 xin.pTileInfo = fout.pTileInfo;
904 xin.tileMode = fin.tileMode;
905
906 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
907 if (r != ADDR_OK)
908 return r;
909
910 assert(xout.tileSwizzle <=
911 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
912 surf->fmask_tile_swizzle = xout.tileSwizzle;
913 }
914 }
915
916 /* Recalculate the whole DCC miptree size including disabled levels.
917 * This is what addrlib does, but calling addrlib would be a lot more
918 * complicated.
919 */
920 if (surf->dcc_size && config->info.levels > 1) {
921 /* The smallest miplevels that are never compressed by DCC
922 * still read the DCC buffer via TC if the base level uses DCC,
923 * and for some reason the DCC buffer needs to be larger if
924 * the miptree uses non-zero tile_swizzle. Otherwise there are
925 * VM faults.
926 *
927 * "dcc_alignment * 4" was determined by trial and error.
928 */
929 surf->dcc_size = align64(surf->surf_size >> 8,
930 surf->dcc_alignment * 4);
931 }
932
933 /* Make sure HTILE covers the whole miptree, because the shader reads
934 * TC-compatible HTILE even for levels where it's disabled by DB.
935 */
936 if (surf->htile_size && config->info.levels > 1 &&
937 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
938 /* MSAA can't occur with levels > 1, so ignore the sample count. */
939 const unsigned total_pixels = surf->surf_size / surf->bpe;
940 const unsigned htile_block_size = 8 * 8;
941 const unsigned htile_element_size = 4;
942
943 surf->htile_size = (total_pixels / htile_block_size) *
944 htile_element_size;
945 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
946 }
947
948 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
949 surf->is_displayable = surf->is_linear ||
950 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
951 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
952
953 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
954 * used at the same time. This case is not currently expected to occur
955 * because we don't use rotated. Enforce this restriction on all chips
956 * to facilitate testing.
957 */
958 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
959 assert(!"rotate micro tile mode is unsupported");
960 return ADDR_ERROR;
961 }
962
963 ac_compute_cmask(info, config, surf);
964 return 0;
965 }
966
967 /* This is only called when expecting a tiled layout. */
968 static int
969 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
970 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
971 bool is_fmask, AddrSwizzleMode *swizzle_mode)
972 {
973 ADDR_E_RETURNCODE ret;
974 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
975 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
976
977 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
978 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
979
980 sin.flags = in->flags;
981 sin.resourceType = in->resourceType;
982 sin.format = in->format;
983 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
984 /* TODO: We could allow some of these: */
985 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
986 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
987 sin.bpp = in->bpp;
988 sin.width = in->width;
989 sin.height = in->height;
990 sin.numSlices = in->numSlices;
991 sin.numMipLevels = in->numMipLevels;
992 sin.numSamples = in->numSamples;
993 sin.numFrags = in->numFrags;
994
995 if (is_fmask) {
996 sin.flags.display = 0;
997 sin.flags.color = 0;
998 sin.flags.fmask = 1;
999 }
1000
1001 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1002 if (ret != ADDR_OK)
1003 return ret;
1004
1005 *swizzle_mode = sout.swizzleMode;
1006 return 0;
1007 }
1008
1009 static bool gfx9_is_dcc_capable(const struct radeon_info *info, unsigned sw_mode)
1010 {
1011 if (info->chip_class >= GFX10)
1012 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1013
1014 return sw_mode != ADDR_SW_LINEAR;
1015 }
1016
1017 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1018 const struct radeon_info *info,
1019 const struct ac_surf_config *config,
1020 struct radeon_surf *surf, bool compressed,
1021 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1022 {
1023 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1024 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1025 ADDR_E_RETURNCODE ret;
1026
1027 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1028 out.pMipInfo = mip_info;
1029
1030 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1031 if (ret != ADDR_OK)
1032 return ret;
1033
1034 if (in->flags.stencil) {
1035 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1036 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1037 out.mipChainPitch - 1;
1038 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1039 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1040 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1041 return 0;
1042 }
1043
1044 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1045 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1046 out.mipChainPitch - 1;
1047
1048 /* CMASK fast clear uses these even if FMASK isn't allocated.
1049 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1050 */
1051 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1052 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1053
1054 surf->u.gfx9.surf_slice_size = out.sliceSize;
1055 surf->u.gfx9.surf_pitch = out.pitch;
1056 surf->u.gfx9.surf_height = out.height;
1057 surf->surf_size = out.surfSize;
1058 surf->surf_alignment = out.baseAlign;
1059
1060 if (in->swizzleMode == ADDR_SW_LINEAR) {
1061 for (unsigned i = 0; i < in->numMipLevels; i++)
1062 surf->u.gfx9.offset[i] = mip_info[i].offset;
1063 }
1064
1065 if (in->flags.depth) {
1066 assert(in->swizzleMode != ADDR_SW_LINEAR);
1067
1068 /* HTILE */
1069 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1070 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1071
1072 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1073 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1074
1075 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1076 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1077 hin.depthFlags = in->flags;
1078 hin.swizzleMode = in->swizzleMode;
1079 hin.unalignedWidth = in->width;
1080 hin.unalignedHeight = in->height;
1081 hin.numSlices = in->numSlices;
1082 hin.numMipLevels = in->numMipLevels;
1083 hin.firstMipIdInTail = out.firstMipIdInTail;
1084
1085 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1086 if (ret != ADDR_OK)
1087 return ret;
1088
1089 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1090 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1091 surf->htile_size = hout.htileBytes;
1092 surf->htile_slice_size = hout.sliceSize;
1093 surf->htile_alignment = hout.baseAlign;
1094 } else {
1095 /* Compute tile swizzle for the color surface.
1096 * All *_X and *_T modes can use the swizzle.
1097 */
1098 if (config->info.surf_index &&
1099 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1100 !out.mipChainInTail &&
1101 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1102 !in->flags.display) {
1103 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1104 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1105
1106 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1107 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1108
1109 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1110 xin.flags = in->flags;
1111 xin.swizzleMode = in->swizzleMode;
1112 xin.resourceType = in->resourceType;
1113 xin.format = in->format;
1114 xin.numSamples = in->numSamples;
1115 xin.numFrags = in->numFrags;
1116
1117 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1118 if (ret != ADDR_OK)
1119 return ret;
1120
1121 assert(xout.pipeBankXor <=
1122 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1123 surf->tile_swizzle = xout.pipeBankXor;
1124 }
1125
1126 /* DCC */
1127 if (info->has_graphics &&
1128 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1129 !compressed &&
1130 gfx9_is_dcc_capable(info, in->swizzleMode)) {
1131 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1132 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1133 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1134
1135 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1136 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1137 dout.pMipInfo = meta_mip_info;
1138
1139 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1140 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1141 din.colorFlags = in->flags;
1142 din.resourceType = in->resourceType;
1143 din.swizzleMode = in->swizzleMode;
1144 din.bpp = in->bpp;
1145 din.unalignedWidth = in->width;
1146 din.unalignedHeight = in->height;
1147 din.numSlices = in->numSlices;
1148 din.numFrags = in->numFrags;
1149 din.numMipLevels = in->numMipLevels;
1150 din.dataSurfaceSize = out.surfSize;
1151 din.firstMipIdInTail = out.firstMipIdInTail;
1152
1153 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1154 if (ret != ADDR_OK)
1155 return ret;
1156
1157 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1158 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1159 surf->dcc_size = dout.dccRamSize;
1160 surf->dcc_alignment = dout.dccRamBaseAlign;
1161 surf->num_dcc_levels = in->numMipLevels;
1162
1163 /* Disable DCC for levels that are in the mip tail.
1164 *
1165 * There are two issues that this is intended to
1166 * address:
1167 *
1168 * 1. Multiple mip levels may share a cache line. This
1169 * can lead to corruption when switching between
1170 * rendering to different mip levels because the
1171 * RBs don't maintain coherency.
1172 *
1173 * 2. Texturing with metadata after rendering sometimes
1174 * fails with corruption, probably for a similar
1175 * reason.
1176 *
1177 * Working around these issues for all levels in the
1178 * mip tail may be overly conservative, but it's what
1179 * Vulkan does.
1180 *
1181 * Alternative solutions that also work but are worse:
1182 * - Disable DCC entirely.
1183 * - Flush TC L2 after rendering.
1184 */
1185 for (unsigned i = 0; i < in->numMipLevels; i++) {
1186 if (meta_mip_info[i].inMiptail) {
1187 surf->num_dcc_levels = i;
1188 break;
1189 }
1190 }
1191
1192 if (!surf->num_dcc_levels)
1193 surf->dcc_size = 0;
1194
1195 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1196 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1197 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1198
1199 /* Compute displayable DCC. */
1200 if (in->flags.display &&
1201 surf->num_dcc_levels &&
1202 info->use_display_dcc_with_retile_blit) {
1203 /* Compute displayable DCC info. */
1204 din.dccKeyFlags.pipeAligned = 0;
1205 din.dccKeyFlags.rbAligned = 0;
1206
1207 assert(din.numSlices == 1);
1208 assert(din.numMipLevels == 1);
1209 assert(din.numFrags == 1);
1210 assert(surf->tile_swizzle == 0);
1211 assert(surf->u.gfx9.dcc.pipe_aligned ||
1212 surf->u.gfx9.dcc.rb_aligned);
1213
1214 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1215 if (ret != ADDR_OK)
1216 return ret;
1217
1218 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1219 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1220 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1221 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1222
1223 /* Compute address mapping from non-displayable to displayable DCC. */
1224 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1225 addrin.size = sizeof(addrin);
1226 addrin.colorFlags.color = 1;
1227 addrin.swizzleMode = din.swizzleMode;
1228 addrin.resourceType = din.resourceType;
1229 addrin.bpp = din.bpp;
1230 addrin.unalignedWidth = din.unalignedWidth;
1231 addrin.unalignedHeight = din.unalignedHeight;
1232 addrin.numSlices = 1;
1233 addrin.numMipLevels = 1;
1234 addrin.numFrags = 1;
1235
1236 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1237 addrout.size = sizeof(addrout);
1238
1239 surf->u.gfx9.dcc_retile_num_elements =
1240 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1241 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1242 /* Align the size to 4 (for the compute shader). */
1243 surf->u.gfx9.dcc_retile_num_elements =
1244 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1245
1246 surf->u.gfx9.dcc_retile_map =
1247 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1248 if (!surf->u.gfx9.dcc_retile_map)
1249 return ADDR_OUTOFMEMORY;
1250
1251 unsigned index = 0;
1252 surf->u.gfx9.dcc_retile_use_uint16 = true;
1253
1254 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1255 addrin.y = y;
1256
1257 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1258 addrin.x = x;
1259
1260 /* Compute src DCC address */
1261 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1262 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1263 addrout.addr = 0;
1264
1265 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1266 if (ret != ADDR_OK)
1267 return ret;
1268
1269 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1270 if (addrout.addr > UINT16_MAX)
1271 surf->u.gfx9.dcc_retile_use_uint16 = false;
1272
1273 /* Compute dst DCC address */
1274 addrin.dccKeyFlags.pipeAligned = 0;
1275 addrin.dccKeyFlags.rbAligned = 0;
1276 addrout.addr = 0;
1277
1278 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1279 if (ret != ADDR_OK)
1280 return ret;
1281
1282 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1283 if (addrout.addr > UINT16_MAX)
1284 surf->u.gfx9.dcc_retile_use_uint16 = false;
1285
1286 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1287 index++;
1288 }
1289 }
1290 /* Fill the remaining pairs with the last one (for the compute shader). */
1291 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1292 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1293 }
1294 }
1295
1296 /* FMASK */
1297 if (in->numSamples > 1 && !(surf->flags & RADEON_SURF_NO_FMASK)) {
1298 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1299 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1300
1301 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1302 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1303
1304 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1305 true, &fin.swizzleMode);
1306 if (ret != ADDR_OK)
1307 return ret;
1308
1309 fin.unalignedWidth = in->width;
1310 fin.unalignedHeight = in->height;
1311 fin.numSlices = in->numSlices;
1312 fin.numSamples = in->numSamples;
1313 fin.numFrags = in->numFrags;
1314
1315 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1316 if (ret != ADDR_OK)
1317 return ret;
1318
1319 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1320 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1321 surf->fmask_size = fout.fmaskBytes;
1322 surf->fmask_alignment = fout.baseAlign;
1323
1324 /* Compute tile swizzle for the FMASK surface. */
1325 if (config->info.fmask_surf_index &&
1326 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1327 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1328 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1329 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1330
1331 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1332 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1333
1334 /* This counter starts from 1 instead of 0. */
1335 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1336 xin.flags = in->flags;
1337 xin.swizzleMode = fin.swizzleMode;
1338 xin.resourceType = in->resourceType;
1339 xin.format = in->format;
1340 xin.numSamples = in->numSamples;
1341 xin.numFrags = in->numFrags;
1342
1343 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1344 if (ret != ADDR_OK)
1345 return ret;
1346
1347 assert(xout.pipeBankXor <=
1348 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1349 surf->fmask_tile_swizzle = xout.pipeBankXor;
1350 }
1351 }
1352
1353 /* CMASK -- on GFX10 only for FMASK */
1354 if (in->swizzleMode != ADDR_SW_LINEAR &&
1355 ((info->chip_class <= GFX9 && in->numSamples == 1) ||
1356 (surf->fmask_size && in->numSamples >= 2))) {
1357 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1358 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1359
1360 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1361 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1362
1363 if (in->numSamples > 1) {
1364 /* FMASK is always aligned. */
1365 cin.cMaskFlags.pipeAligned = 1;
1366 cin.cMaskFlags.rbAligned = 1;
1367 } else {
1368 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1369 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1370 }
1371 cin.colorFlags = in->flags;
1372 cin.resourceType = in->resourceType;
1373 cin.unalignedWidth = in->width;
1374 cin.unalignedHeight = in->height;
1375 cin.numSlices = in->numSlices;
1376
1377 if (in->numSamples > 1)
1378 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1379 else
1380 cin.swizzleMode = in->swizzleMode;
1381
1382 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1383 if (ret != ADDR_OK)
1384 return ret;
1385
1386 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1387 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1388 surf->cmask_size = cout.cmaskBytes;
1389 surf->cmask_alignment = cout.baseAlign;
1390 }
1391 }
1392
1393 return 0;
1394 }
1395
1396 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1397 const struct radeon_info *info,
1398 const struct ac_surf_config *config,
1399 enum radeon_surf_mode mode,
1400 struct radeon_surf *surf)
1401 {
1402 bool compressed;
1403 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1404 int r;
1405
1406 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1407
1408 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1409
1410 /* The format must be set correctly for the allocation of compressed
1411 * textures to work. In other cases, setting the bpp is sufficient. */
1412 if (compressed) {
1413 switch (surf->bpe) {
1414 case 8:
1415 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1416 break;
1417 case 16:
1418 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1419 break;
1420 default:
1421 assert(0);
1422 }
1423 } else {
1424 switch (surf->bpe) {
1425 case 1:
1426 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1427 AddrSurfInfoIn.format = ADDR_FMT_8;
1428 break;
1429 case 2:
1430 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1431 !(surf->flags & RADEON_SURF_SBUFFER));
1432 AddrSurfInfoIn.format = ADDR_FMT_16;
1433 break;
1434 case 4:
1435 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1436 !(surf->flags & RADEON_SURF_SBUFFER));
1437 AddrSurfInfoIn.format = ADDR_FMT_32;
1438 break;
1439 case 8:
1440 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1441 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1442 break;
1443 case 12:
1444 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1445 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1446 break;
1447 case 16:
1448 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1449 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1450 break;
1451 default:
1452 assert(0);
1453 }
1454 AddrSurfInfoIn.bpp = surf->bpe * 8;
1455 }
1456
1457 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1458 AddrSurfInfoIn.flags.color = is_color_surface &&
1459 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1460 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1461 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1462 /* flags.texture currently refers to TC-compatible HTILE */
1463 AddrSurfInfoIn.flags.texture = is_color_surface ||
1464 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1465 AddrSurfInfoIn.flags.opt4space = 1;
1466
1467 AddrSurfInfoIn.numMipLevels = config->info.levels;
1468 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1469 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1470
1471 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1472 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1473
1474 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1475 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1476 * must sample 1D textures as 2D. */
1477 if (config->is_3d)
1478 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1479 else if (info->chip_class != GFX9 && config->is_1d)
1480 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
1481 else
1482 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1483
1484 AddrSurfInfoIn.width = config->info.width;
1485 AddrSurfInfoIn.height = config->info.height;
1486
1487 if (config->is_3d)
1488 AddrSurfInfoIn.numSlices = config->info.depth;
1489 else if (config->is_cube)
1490 AddrSurfInfoIn.numSlices = 6;
1491 else
1492 AddrSurfInfoIn.numSlices = config->info.array_size;
1493
1494 /* This is propagated to HTILE/DCC/CMASK. */
1495 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1496 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1497
1498 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1499 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1500 *
1501 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1502 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1503 * after rendering, so PIPE_ALIGNED=1 is recommended.
1504 */
1505 if (info->use_display_dcc_unaligned && is_color_surface &&
1506 AddrSurfInfoIn.flags.display) {
1507 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1508 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1509 }
1510
1511 switch (mode) {
1512 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1513 assert(config->info.samples <= 1);
1514 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1515 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1516 break;
1517
1518 case RADEON_SURF_MODE_1D:
1519 case RADEON_SURF_MODE_2D:
1520 if (surf->flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FORCE_SWIZZLE_MODE)) {
1521 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1522 break;
1523 }
1524
1525 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1526 false, &AddrSurfInfoIn.swizzleMode);
1527 if (r)
1528 return r;
1529 break;
1530
1531 default:
1532 assert(0);
1533 }
1534
1535 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1536 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1537
1538 surf->num_dcc_levels = 0;
1539 surf->surf_size = 0;
1540 surf->fmask_size = 0;
1541 surf->dcc_size = 0;
1542 surf->htile_size = 0;
1543 surf->htile_slice_size = 0;
1544 surf->u.gfx9.surf_offset = 0;
1545 surf->u.gfx9.stencil_offset = 0;
1546 surf->cmask_size = 0;
1547 surf->u.gfx9.dcc_retile_use_uint16 = false;
1548 surf->u.gfx9.dcc_retile_num_elements = 0;
1549 surf->u.gfx9.dcc_retile_map = NULL;
1550
1551 /* Calculate texture layout information. */
1552 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1553 &AddrSurfInfoIn);
1554 if (r)
1555 goto error;
1556
1557 /* Calculate texture layout information for stencil. */
1558 if (surf->flags & RADEON_SURF_SBUFFER) {
1559 AddrSurfInfoIn.flags.stencil = 1;
1560 AddrSurfInfoIn.bpp = 8;
1561 AddrSurfInfoIn.format = ADDR_FMT_8;
1562
1563 if (!AddrSurfInfoIn.flags.depth) {
1564 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1565 false, &AddrSurfInfoIn.swizzleMode);
1566 if (r)
1567 goto error;
1568 } else
1569 AddrSurfInfoIn.flags.depth = 0;
1570
1571 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1572 &AddrSurfInfoIn);
1573 if (r)
1574 goto error;
1575 }
1576
1577 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1578
1579 /* Query whether the surface is displayable. */
1580 bool displayable = false;
1581 if (!config->is_3d && !config->is_cube) {
1582 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1583 surf->bpe * 8, &displayable);
1584 if (r)
1585 goto error;
1586
1587 /* Display needs unaligned DCC. */
1588 if (info->use_display_dcc_unaligned &&
1589 surf->num_dcc_levels &&
1590 (surf->u.gfx9.dcc.pipe_aligned ||
1591 surf->u.gfx9.dcc.rb_aligned))
1592 displayable = false;
1593 }
1594 surf->is_displayable = displayable;
1595
1596 switch (surf->u.gfx9.surf.swizzle_mode) {
1597 /* S = standard. */
1598 case ADDR_SW_256B_S:
1599 case ADDR_SW_4KB_S:
1600 case ADDR_SW_64KB_S:
1601 case ADDR_SW_VAR_S:
1602 case ADDR_SW_64KB_S_T:
1603 case ADDR_SW_4KB_S_X:
1604 case ADDR_SW_64KB_S_X:
1605 case ADDR_SW_VAR_S_X:
1606 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1607 break;
1608
1609 /* D = display. */
1610 case ADDR_SW_LINEAR:
1611 case ADDR_SW_256B_D:
1612 case ADDR_SW_4KB_D:
1613 case ADDR_SW_64KB_D:
1614 case ADDR_SW_VAR_D:
1615 case ADDR_SW_64KB_D_T:
1616 case ADDR_SW_4KB_D_X:
1617 case ADDR_SW_64KB_D_X:
1618 case ADDR_SW_VAR_D_X:
1619 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1620 break;
1621
1622 /* R = rotated (gfx9), render target (gfx10). */
1623 case ADDR_SW_256B_R:
1624 case ADDR_SW_4KB_R:
1625 case ADDR_SW_64KB_R:
1626 case ADDR_SW_VAR_R:
1627 case ADDR_SW_64KB_R_T:
1628 case ADDR_SW_4KB_R_X:
1629 case ADDR_SW_64KB_R_X:
1630 case ADDR_SW_VAR_R_X:
1631 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1632 * used at the same time. We currently do not use rotated
1633 * in gfx9.
1634 */
1635 assert(info->chip_class >= GFX10 ||
1636 !"rotate micro tile mode is unsupported");
1637 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1638 break;
1639
1640 /* Z = depth. */
1641 case ADDR_SW_4KB_Z:
1642 case ADDR_SW_64KB_Z:
1643 case ADDR_SW_VAR_Z:
1644 case ADDR_SW_64KB_Z_T:
1645 case ADDR_SW_4KB_Z_X:
1646 case ADDR_SW_64KB_Z_X:
1647 case ADDR_SW_VAR_Z_X:
1648 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1649 break;
1650
1651 default:
1652 assert(0);
1653 }
1654
1655 return 0;
1656
1657 error:
1658 free(surf->u.gfx9.dcc_retile_map);
1659 surf->u.gfx9.dcc_retile_map = NULL;
1660 return r;
1661 }
1662
1663 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1664 const struct ac_surf_config *config,
1665 enum radeon_surf_mode mode,
1666 struct radeon_surf *surf)
1667 {
1668 int r;
1669
1670 r = surf_config_sanity(config, surf->flags);
1671 if (r)
1672 return r;
1673
1674 if (info->chip_class >= GFX9)
1675 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1676 else
1677 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1678 }