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amd: prepare dropping include of p_compiler.h
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/inc/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
53 {
54 return malloc(pInput->sizeInBytes);
55 }
56
57 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
58 {
59 free(pInput->pVirtAddr);
60 return ADDR_OK;
61 }
62
63 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
64 const struct amdgpu_gpu_info *amdinfo,
65 uint64_t *max_alignment)
66 {
67 ADDR_CREATE_INPUT addrCreateInput = {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
69 ADDR_REGISTER_VALUE regValue = {0};
70 ADDR_CREATE_FLAGS createFlags = {{0}};
71 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
72 ADDR_E_RETURNCODE addrRet;
73
74 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
75 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
76
77 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
78 createFlags.value = 0;
79
80 addrCreateInput.chipFamily = info->family_id;
81 addrCreateInput.chipRevision = info->chip_external_rev;
82
83 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
84 return NULL;
85
86 if (addrCreateInput.chipFamily >= FAMILY_AI) {
87 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
88 regValue.blockVarSizeLog2 = 0;
89 } else {
90 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
91 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
92
93 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
94 regValue.pTileConfig = amdinfo->gb_tile_mode;
95 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
96 if (addrCreateInput.chipFamily == FAMILY_SI) {
97 regValue.pMacroTileConfig = NULL;
98 regValue.noOfMacroEntries = 0;
99 } else {
100 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
101 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
102 }
103
104 createFlags.useTileIndex = 1;
105 createFlags.useHtileSliceAlign = 1;
106
107 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
108 }
109
110 addrCreateInput.callbacks.allocSysMem = allocSysMem;
111 addrCreateInput.callbacks.freeSysMem = freeSysMem;
112 addrCreateInput.callbacks.debugPrint = 0;
113 addrCreateInput.createFlags = createFlags;
114 addrCreateInput.regValue = regValue;
115
116 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
117 if (addrRet != ADDR_OK)
118 return NULL;
119
120 if (max_alignment) {
121 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
122 if (addrRet == ADDR_OK){
123 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
124 }
125 }
126 return addrCreateOutput.hLib;
127 }
128
129 static int surf_config_sanity(const struct ac_surf_config *config,
130 unsigned flags)
131 {
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
134 */
135 assert(!(flags & RADEON_SURF_FMASK));
136 if (flags & RADEON_SURF_FMASK)
137 return -EINVAL;
138
139 /* all dimension must be at least 1 ! */
140 if (!config->info.width || !config->info.height || !config->info.depth ||
141 !config->info.array_size || !config->info.levels)
142 return -EINVAL;
143
144 switch (config->info.samples) {
145 case 0:
146 case 1:
147 case 2:
148 case 4:
149 case 8:
150 break;
151 case 16:
152 if (flags & RADEON_SURF_Z_OR_SBUFFER)
153 return -EINVAL;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
160 switch (config->info.storage_samples) {
161 case 0:
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 break;
167 default:
168 return -EINVAL;
169 }
170 }
171
172 if (config->is_3d && config->info.array_size > 1)
173 return -EINVAL;
174 if (config->is_cube && config->info.depth > 1)
175 return -EINVAL;
176
177 return 0;
178 }
179
180 static int gfx6_compute_level(ADDR_HANDLE addrlib,
181 const struct ac_surf_config *config,
182 struct radeon_surf *surf, bool is_stencil,
183 unsigned level, bool compressed,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
186 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
187 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
188 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
190 {
191 struct legacy_surf_level *surf_level;
192 ADDR_E_RETURNCODE ret;
193
194 AddrSurfInfoIn->mipLevel = level;
195 AddrSurfInfoIn->width = u_minify(config->info.width, level);
196 AddrSurfInfoIn->height = u_minify(config->info.height, level);
197
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
200 */
201 if (config->info.levels == 1 &&
202 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
203 AddrSurfInfoIn->bpp &&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
205 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
206
207 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
208 }
209
210 if (config->is_3d)
211 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
212 else if (config->is_cube)
213 AddrSurfInfoIn->numSlices = 6;
214 else
215 AddrSurfInfoIn->numSlices = config->info.array_size;
216
217 if (level > 0) {
218 /* Set the base level pitch. This is needed for calculation
219 * of non-zero levels. */
220 if (is_stencil)
221 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
222 else
223 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
224
225 /* Convert blocks to pixels for compressed formats. */
226 if (compressed)
227 AddrSurfInfoIn->basePitch *= surf->blk_w;
228 }
229
230 ret = AddrComputeSurfaceInfo(addrlib,
231 AddrSurfInfoIn,
232 AddrSurfInfoOut);
233 if (ret != ADDR_OK) {
234 return ret;
235 }
236
237 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
238 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
239 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
240 surf_level->nblk_x = AddrSurfInfoOut->pitch;
241 surf_level->nblk_y = AddrSurfInfoOut->height;
242
243 switch (AddrSurfInfoOut->tileMode) {
244 case ADDR_TM_LINEAR_ALIGNED:
245 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
246 break;
247 case ADDR_TM_1D_TILED_THIN1:
248 surf_level->mode = RADEON_SURF_MODE_1D;
249 break;
250 case ADDR_TM_2D_TILED_THIN1:
251 surf_level->mode = RADEON_SURF_MODE_2D;
252 break;
253 default:
254 assert(0);
255 }
256
257 if (is_stencil)
258 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
259 else
260 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
261
262 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
263
264 /* Clear DCC fields at the beginning. */
265 surf_level->dcc_offset = 0;
266
267 /* The previous level's flag tells us if we can use DCC for this level. */
268 if (AddrSurfInfoIn->flags.dccCompatible &&
269 (level == 0 || AddrDccOut->subLvlCompressible)) {
270 bool prev_level_clearable = level == 0 ||
271 AddrDccOut->dccRamSizeAligned;
272
273 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
274 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
275 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
276 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
277 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
278
279 ret = AddrComputeDccInfo(addrlib,
280 AddrDccIn,
281 AddrDccOut);
282
283 if (ret == ADDR_OK) {
284 surf_level->dcc_offset = surf->dcc_size;
285 surf->num_dcc_levels = level + 1;
286 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
287 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
288
289 /* If the DCC size of a subresource (1 mip level or 1 slice)
290 * is not aligned, the DCC memory layout is not contiguous for
291 * that subresource, which means we can't use fast clear.
292 *
293 * We only do fast clears for whole mipmap levels. If we did
294 * per-slice fast clears, the same restriction would apply.
295 * (i.e. only compute the slice size and see if it's aligned)
296 *
297 * The last level can be non-contiguous and still be clearable
298 * if it's interleaved with the next level that doesn't exist.
299 */
300 if (AddrDccOut->dccRamSizeAligned ||
301 (prev_level_clearable && level == config->info.levels - 1))
302 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
303 else
304 surf_level->dcc_fast_clear_size = 0;
305
306 /* Compute the DCC slice size because addrlib doesn't
307 * provide this info. As DCC memory is linear (each
308 * slice is the same size) it's easy to compute.
309 */
310 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
311
312 /* For arrays, we have to compute the DCC info again
313 * with one slice size to get a correct fast clear
314 * size.
315 */
316 if (config->info.array_size > 1) {
317 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
318 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
319 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
320 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
321 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
322
323 ret = AddrComputeDccInfo(addrlib,
324 AddrDccIn, AddrDccOut);
325 if (ret == ADDR_OK) {
326 /* If the DCC memory isn't properly
327 * aligned, the data are interleaved
328 * accross slices.
329 */
330 if (AddrDccOut->dccRamSizeAligned)
331 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
332 else
333 surf_level->dcc_slice_fast_clear_size = 0;
334 }
335 } else {
336 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
337 }
338 }
339 }
340
341 /* TC-compatible HTILE. */
342 if (!is_stencil &&
343 AddrSurfInfoIn->flags.depth &&
344 surf_level->mode == RADEON_SURF_MODE_2D &&
345 level == 0) {
346 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
347 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
348 AddrHtileIn->height = AddrSurfInfoOut->height;
349 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
350 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
351 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
352 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
353 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
354 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
355
356 ret = AddrComputeHtileInfo(addrlib,
357 AddrHtileIn,
358 AddrHtileOut);
359
360 if (ret == ADDR_OK) {
361 surf->htile_size = AddrHtileOut->htileBytes;
362 surf->htile_slice_size = AddrHtileOut->sliceSize;
363 surf->htile_alignment = AddrHtileOut->baseAlign;
364 }
365 }
366
367 return 0;
368 }
369
370 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
371 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
372 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
373
374 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
375 const struct radeon_info *info)
376 {
377 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
378
379 if (info->chip_class >= GFX7)
380 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
381 else
382 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
383 }
384
385 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
386 {
387 unsigned index, tileb;
388
389 tileb = 8 * 8 * surf->bpe;
390 tileb = MIN2(surf->u.legacy.tile_split, tileb);
391
392 for (index = 0; tileb > 64; index++)
393 tileb >>= 1;
394
395 assert(index < 16);
396 return index;
397 }
398
399 static bool get_display_flag(const struct ac_surf_config *config,
400 const struct radeon_surf *surf)
401 {
402 unsigned num_channels = config->info.num_channels;
403 unsigned bpe = surf->bpe;
404
405 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
406 surf->flags & RADEON_SURF_SCANOUT &&
407 config->info.samples <= 1 &&
408 surf->blk_w <= 2 && surf->blk_h == 1) {
409 /* subsampled */
410 if (surf->blk_w == 2 && surf->blk_h == 1)
411 return true;
412
413 if (/* RGBA8 or RGBA16F */
414 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
415 /* R5G6B5 or R5G5B5A1 */
416 (bpe == 2 && num_channels >= 3) ||
417 /* C8 palette */
418 (bpe == 1 && num_channels == 1))
419 return true;
420 }
421 return false;
422 }
423
424 /**
425 * This must be called after the first level is computed.
426 *
427 * Copy surface-global settings like pipe/bank config from level 0 surface
428 * computation, and compute tile swizzle.
429 */
430 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
431 const struct radeon_info *info,
432 const struct ac_surf_config *config,
433 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
434 struct radeon_surf *surf)
435 {
436 surf->surf_alignment = csio->baseAlign;
437 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
438 gfx6_set_micro_tile_mode(surf, info);
439
440 /* For 2D modes only. */
441 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
442 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
443 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
444 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
445 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
446 surf->u.legacy.num_banks = csio->pTileInfo->banks;
447 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
448 } else {
449 surf->u.legacy.macro_tile_index = 0;
450 }
451
452 /* Compute tile swizzle. */
453 /* TODO: fix tile swizzle with mipmapping for GFX6 */
454 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
455 config->info.surf_index &&
456 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
457 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
458 !get_display_flag(config, surf)) {
459 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
460 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
461
462 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
463 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
464
465 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
466 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
467 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
468 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
469 AddrBaseSwizzleIn.tileMode = csio->tileMode;
470
471 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
472 &AddrBaseSwizzleOut);
473 if (r != ADDR_OK)
474 return r;
475
476 assert(AddrBaseSwizzleOut.tileSwizzle <=
477 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
478 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
479 }
480 return 0;
481 }
482
483 static void ac_compute_cmask(const struct radeon_info *info,
484 const struct ac_surf_config *config,
485 struct radeon_surf *surf)
486 {
487 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
488 unsigned num_pipes = info->num_tile_pipes;
489 unsigned cl_width, cl_height;
490
491 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
492 return;
493
494 assert(info->chip_class <= GFX8);
495
496 switch (num_pipes) {
497 case 2:
498 cl_width = 32;
499 cl_height = 16;
500 break;
501 case 4:
502 cl_width = 32;
503 cl_height = 32;
504 break;
505 case 8:
506 cl_width = 64;
507 cl_height = 32;
508 break;
509 case 16: /* Hawaii */
510 cl_width = 64;
511 cl_height = 64;
512 break;
513 default:
514 assert(0);
515 return;
516 }
517
518 unsigned base_align = num_pipes * pipe_interleave_bytes;
519
520 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
521 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
522 unsigned slice_elements = (width * height) / (8*8);
523
524 /* Each element of CMASK is a nibble. */
525 unsigned slice_bytes = slice_elements / 2;
526
527 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
528 if (surf->u.legacy.cmask_slice_tile_max)
529 surf->u.legacy.cmask_slice_tile_max -= 1;
530
531 unsigned num_layers;
532 if (config->is_3d)
533 num_layers = config->info.depth;
534 else if (config->is_cube)
535 num_layers = 6;
536 else
537 num_layers = config->info.array_size;
538
539 surf->cmask_alignment = MAX2(256, base_align);
540 surf->cmask_slice_size = align(slice_bytes, base_align);
541 surf->cmask_size = surf->cmask_slice_size * num_layers;
542 }
543
544 /**
545 * Fill in the tiling information in \p surf based on the given surface config.
546 *
547 * The following fields of \p surf must be initialized by the caller:
548 * blk_w, blk_h, bpe, flags.
549 */
550 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
551 const struct radeon_info *info,
552 const struct ac_surf_config *config,
553 enum radeon_surf_mode mode,
554 struct radeon_surf *surf)
555 {
556 unsigned level;
557 bool compressed;
558 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
559 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
560 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
561 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
562 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
563 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
564 ADDR_TILEINFO AddrTileInfoIn = {0};
565 ADDR_TILEINFO AddrTileInfoOut = {0};
566 int r;
567
568 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
569 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
570 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
571 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
572 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
573 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
574 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
575
576 compressed = surf->blk_w == 4 && surf->blk_h == 4;
577
578 /* MSAA requires 2D tiling. */
579 if (config->info.samples > 1)
580 mode = RADEON_SURF_MODE_2D;
581
582 /* DB doesn't support linear layouts. */
583 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
584 mode < RADEON_SURF_MODE_1D)
585 mode = RADEON_SURF_MODE_1D;
586
587 /* Set the requested tiling mode. */
588 switch (mode) {
589 case RADEON_SURF_MODE_LINEAR_ALIGNED:
590 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
591 break;
592 case RADEON_SURF_MODE_1D:
593 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
594 break;
595 case RADEON_SURF_MODE_2D:
596 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
597 break;
598 default:
599 assert(0);
600 }
601
602 /* The format must be set correctly for the allocation of compressed
603 * textures to work. In other cases, setting the bpp is sufficient.
604 */
605 if (compressed) {
606 switch (surf->bpe) {
607 case 8:
608 AddrSurfInfoIn.format = ADDR_FMT_BC1;
609 break;
610 case 16:
611 AddrSurfInfoIn.format = ADDR_FMT_BC3;
612 break;
613 default:
614 assert(0);
615 }
616 }
617 else {
618 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
619 }
620
621 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
622 MAX2(1, config->info.samples);
623 AddrSurfInfoIn.tileIndex = -1;
624
625 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
626 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
627 MAX2(1, config->info.storage_samples);
628 }
629
630 /* Set the micro tile type. */
631 if (surf->flags & RADEON_SURF_SCANOUT)
632 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
633 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
634 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
635 else
636 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
637
638 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
639 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
640 AddrSurfInfoIn.flags.cube = config->is_cube;
641 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
642 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
643 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
644
645 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
646 * requested, because TC-compatible HTILE requires 2D tiling.
647 */
648 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
649 !AddrSurfInfoIn.flags.fmask &&
650 config->info.samples <= 1 &&
651 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
652
653 /* DCC notes:
654 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
655 * with samples >= 4.
656 * - Mipmapped array textures have low performance (discovered by a closed
657 * driver team).
658 */
659 AddrSurfInfoIn.flags.dccCompatible =
660 info->chip_class >= GFX8 &&
661 info->has_graphics && /* disable DCC on compute-only chips */
662 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
663 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
664 !compressed &&
665 ((config->info.array_size == 1 && config->info.depth == 1) ||
666 config->info.levels == 1);
667
668 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
669 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
670
671 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
672 * for Z and stencil. This can cause a number of problems which we work
673 * around here:
674 *
675 * - a depth part that is incompatible with mipmapped texturing
676 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
677 * incorrect tiling applied to the stencil part, stencil buffer
678 * memory accesses that go out of bounds) even without mipmapping
679 *
680 * Some piglit tests that are prone to different types of related
681 * failures:
682 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
683 * ./bin/framebuffer-blit-levels {draw,read} stencil
684 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
685 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
686 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
687 */
688 int stencil_tile_idx = -1;
689
690 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
691 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
692 /* Compute stencilTileIdx that is compatible with the (depth)
693 * tileIdx. This degrades the depth surface if necessary to
694 * ensure that a matching stencilTileIdx exists. */
695 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
696
697 /* Keep the depth mip-tail compatible with texturing. */
698 AddrSurfInfoIn.flags.noStencil = 1;
699 }
700
701 /* Set preferred macrotile parameters. This is usually required
702 * for shared resources. This is for 2D tiling only. */
703 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
704 surf->u.legacy.bankw && surf->u.legacy.bankh &&
705 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
706 /* If any of these parameters are incorrect, the calculation
707 * will fail. */
708 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
709 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
710 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
711 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
712 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
713 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
714 AddrSurfInfoIn.flags.opt4Space = 0;
715 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
716
717 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
718 * the tile index, because we are expected to know it if
719 * we know the other parameters.
720 *
721 * This is something that can easily be fixed in Addrlib.
722 * For now, just figure it out here.
723 * Note that only 2D_TILE_THIN1 is handled here.
724 */
725 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
726 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
727
728 if (info->chip_class == GFX6) {
729 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
730 if (surf->bpe == 2)
731 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
732 else
733 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
734 } else {
735 if (surf->bpe == 1)
736 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
737 else if (surf->bpe == 2)
738 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
739 else if (surf->bpe == 4)
740 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
741 else
742 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
743 }
744 } else {
745 /* GFX7 - GFX8 */
746 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
747 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
748 else
749 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
750
751 /* Addrlib doesn't set this if tileIndex is forced like above. */
752 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
753 }
754 }
755
756 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
757 surf->num_dcc_levels = 0;
758 surf->surf_size = 0;
759 surf->dcc_size = 0;
760 surf->dcc_alignment = 1;
761 surf->htile_size = 0;
762 surf->htile_slice_size = 0;
763 surf->htile_alignment = 1;
764
765 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
766 !(surf->flags & RADEON_SURF_ZBUFFER);
767
768 /* Calculate texture layout information. */
769 if (!only_stencil) {
770 for (level = 0; level < config->info.levels; level++) {
771 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
772 &AddrSurfInfoIn, &AddrSurfInfoOut,
773 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
774 if (r)
775 return r;
776
777 if (level > 0)
778 continue;
779
780 /* Check that we actually got a TC-compatible HTILE if
781 * we requested it (only for level 0, since we're not
782 * supporting HTILE on higher mip levels anyway). */
783 assert(AddrSurfInfoOut.tcCompatible ||
784 !AddrSurfInfoIn.flags.tcCompatible ||
785 AddrSurfInfoIn.flags.matchStencilTileCfg);
786
787 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
788 if (!AddrSurfInfoOut.tcCompatible) {
789 AddrSurfInfoIn.flags.tcCompatible = 0;
790 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
791 }
792
793 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
794 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
795 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
796
797 assert(stencil_tile_idx >= 0);
798 }
799
800 r = gfx6_surface_settings(addrlib, info, config,
801 &AddrSurfInfoOut, surf);
802 if (r)
803 return r;
804 }
805 }
806
807 /* Calculate texture layout information for stencil. */
808 if (surf->flags & RADEON_SURF_SBUFFER) {
809 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
810 AddrSurfInfoIn.bpp = 8;
811 AddrSurfInfoIn.flags.depth = 0;
812 AddrSurfInfoIn.flags.stencil = 1;
813 AddrSurfInfoIn.flags.tcCompatible = 0;
814 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
815 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
816
817 for (level = 0; level < config->info.levels; level++) {
818 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
819 &AddrSurfInfoIn, &AddrSurfInfoOut,
820 &AddrDccIn, &AddrDccOut,
821 NULL, NULL);
822 if (r)
823 return r;
824
825 /* DB uses the depth pitch for both stencil and depth. */
826 if (!only_stencil) {
827 if (surf->u.legacy.stencil_level[level].nblk_x !=
828 surf->u.legacy.level[level].nblk_x)
829 surf->u.legacy.stencil_adjusted = true;
830 } else {
831 surf->u.legacy.level[level].nblk_x =
832 surf->u.legacy.stencil_level[level].nblk_x;
833 }
834
835 if (level == 0) {
836 if (only_stencil) {
837 r = gfx6_surface_settings(addrlib, info, config,
838 &AddrSurfInfoOut, surf);
839 if (r)
840 return r;
841 }
842
843 /* For 2D modes only. */
844 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
845 surf->u.legacy.stencil_tile_split =
846 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
847 }
848 }
849 }
850 }
851
852 /* Compute FMASK. */
853 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
854 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
855 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
856 ADDR_TILEINFO fmask_tile_info = {};
857
858 fin.size = sizeof(fin);
859 fout.size = sizeof(fout);
860
861 fin.tileMode = AddrSurfInfoOut.tileMode;
862 fin.pitch = AddrSurfInfoOut.pitch;
863 fin.height = config->info.height;
864 fin.numSlices = AddrSurfInfoIn.numSlices;
865 fin.numSamples = AddrSurfInfoIn.numSamples;
866 fin.numFrags = AddrSurfInfoIn.numFrags;
867 fin.tileIndex = -1;
868 fout.pTileInfo = &fmask_tile_info;
869
870 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
871 if (r)
872 return r;
873
874 surf->fmask_size = fout.fmaskBytes;
875 surf->fmask_alignment = fout.baseAlign;
876 surf->fmask_tile_swizzle = 0;
877
878 surf->u.legacy.fmask.slice_tile_max =
879 (fout.pitch * fout.height) / 64;
880 if (surf->u.legacy.fmask.slice_tile_max)
881 surf->u.legacy.fmask.slice_tile_max -= 1;
882
883 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
884 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
885 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
886 surf->u.legacy.fmask.slice_size = fout.sliceSize;
887
888 /* Compute tile swizzle for FMASK. */
889 if (config->info.fmask_surf_index &&
890 !(surf->flags & RADEON_SURF_SHAREABLE)) {
891 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
892 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
893
894 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
895 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
896
897 /* This counter starts from 1 instead of 0. */
898 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
899 xin.tileIndex = fout.tileIndex;
900 xin.macroModeIndex = fout.macroModeIndex;
901 xin.pTileInfo = fout.pTileInfo;
902 xin.tileMode = fin.tileMode;
903
904 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
905 if (r != ADDR_OK)
906 return r;
907
908 assert(xout.tileSwizzle <=
909 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
910 surf->fmask_tile_swizzle = xout.tileSwizzle;
911 }
912 }
913
914 /* Recalculate the whole DCC miptree size including disabled levels.
915 * This is what addrlib does, but calling addrlib would be a lot more
916 * complicated.
917 */
918 if (surf->dcc_size && config->info.levels > 1) {
919 /* The smallest miplevels that are never compressed by DCC
920 * still read the DCC buffer via TC if the base level uses DCC,
921 * and for some reason the DCC buffer needs to be larger if
922 * the miptree uses non-zero tile_swizzle. Otherwise there are
923 * VM faults.
924 *
925 * "dcc_alignment * 4" was determined by trial and error.
926 */
927 surf->dcc_size = align64(surf->surf_size >> 8,
928 surf->dcc_alignment * 4);
929 }
930
931 /* Make sure HTILE covers the whole miptree, because the shader reads
932 * TC-compatible HTILE even for levels where it's disabled by DB.
933 */
934 if (surf->htile_size && config->info.levels > 1 &&
935 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
936 /* MSAA can't occur with levels > 1, so ignore the sample count. */
937 const unsigned total_pixels = surf->surf_size / surf->bpe;
938 const unsigned htile_block_size = 8 * 8;
939 const unsigned htile_element_size = 4;
940
941 surf->htile_size = (total_pixels / htile_block_size) *
942 htile_element_size;
943 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
944 }
945
946 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
947 surf->is_displayable = surf->is_linear ||
948 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
949 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
950
951 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
952 * used at the same time. This case is not currently expected to occur
953 * because we don't use rotated. Enforce this restriction on all chips
954 * to facilitate testing.
955 */
956 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
957 assert(!"rotate micro tile mode is unsupported");
958 return ADDR_ERROR;
959 }
960
961 ac_compute_cmask(info, config, surf);
962 return 0;
963 }
964
965 /* This is only called when expecting a tiled layout. */
966 static int
967 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
968 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
969 bool is_fmask, AddrSwizzleMode *swizzle_mode)
970 {
971 ADDR_E_RETURNCODE ret;
972 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
973 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
974
975 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
976 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
977
978 sin.flags = in->flags;
979 sin.resourceType = in->resourceType;
980 sin.format = in->format;
981 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
982 /* TODO: We could allow some of these: */
983 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
984 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
985 sin.bpp = in->bpp;
986 sin.width = in->width;
987 sin.height = in->height;
988 sin.numSlices = in->numSlices;
989 sin.numMipLevels = in->numMipLevels;
990 sin.numSamples = in->numSamples;
991 sin.numFrags = in->numFrags;
992
993 if (is_fmask) {
994 sin.flags.display = 0;
995 sin.flags.color = 0;
996 sin.flags.fmask = 1;
997 }
998
999 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1000 if (ret != ADDR_OK)
1001 return ret;
1002
1003 *swizzle_mode = sout.swizzleMode;
1004 return 0;
1005 }
1006
1007 static bool gfx9_is_dcc_capable(const struct radeon_info *info, unsigned sw_mode)
1008 {
1009 if (info->chip_class >= GFX10)
1010 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1011
1012 return sw_mode != ADDR_SW_LINEAR;
1013 }
1014
1015 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1016 const struct radeon_info *info,
1017 const struct ac_surf_config *config,
1018 struct radeon_surf *surf, bool compressed,
1019 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1020 {
1021 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1022 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1023 ADDR_E_RETURNCODE ret;
1024
1025 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1026 out.pMipInfo = mip_info;
1027
1028 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1029 if (ret != ADDR_OK)
1030 return ret;
1031
1032 if (in->flags.stencil) {
1033 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1034 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1035 out.mipChainPitch - 1;
1036 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1037 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1038 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1039 return 0;
1040 }
1041
1042 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1043 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1044 out.mipChainPitch - 1;
1045
1046 /* CMASK fast clear uses these even if FMASK isn't allocated.
1047 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1048 */
1049 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1050 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1051
1052 surf->u.gfx9.surf_slice_size = out.sliceSize;
1053 surf->u.gfx9.surf_pitch = out.pitch;
1054 surf->u.gfx9.surf_height = out.height;
1055 surf->surf_size = out.surfSize;
1056 surf->surf_alignment = out.baseAlign;
1057
1058 if (in->swizzleMode == ADDR_SW_LINEAR) {
1059 for (unsigned i = 0; i < in->numMipLevels; i++)
1060 surf->u.gfx9.offset[i] = mip_info[i].offset;
1061 }
1062
1063 if (in->flags.depth) {
1064 assert(in->swizzleMode != ADDR_SW_LINEAR);
1065
1066 /* HTILE */
1067 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1068 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1069
1070 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1071 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1072
1073 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1074 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1075 hin.depthFlags = in->flags;
1076 hin.swizzleMode = in->swizzleMode;
1077 hin.unalignedWidth = in->width;
1078 hin.unalignedHeight = in->height;
1079 hin.numSlices = in->numSlices;
1080 hin.numMipLevels = in->numMipLevels;
1081 hin.firstMipIdInTail = out.firstMipIdInTail;
1082
1083 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1084 if (ret != ADDR_OK)
1085 return ret;
1086
1087 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1088 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1089 surf->htile_size = hout.htileBytes;
1090 surf->htile_slice_size = hout.sliceSize;
1091 surf->htile_alignment = hout.baseAlign;
1092 } else {
1093 /* Compute tile swizzle for the color surface.
1094 * All *_X and *_T modes can use the swizzle.
1095 */
1096 if (config->info.surf_index &&
1097 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1098 !out.mipChainInTail &&
1099 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1100 !in->flags.display) {
1101 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1102 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1103
1104 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1105 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1106
1107 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1108 xin.flags = in->flags;
1109 xin.swizzleMode = in->swizzleMode;
1110 xin.resourceType = in->resourceType;
1111 xin.format = in->format;
1112 xin.numSamples = in->numSamples;
1113 xin.numFrags = in->numFrags;
1114
1115 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1116 if (ret != ADDR_OK)
1117 return ret;
1118
1119 assert(xout.pipeBankXor <=
1120 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1121 surf->tile_swizzle = xout.pipeBankXor;
1122 }
1123
1124 /* DCC */
1125 if (info->has_graphics &&
1126 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1127 !compressed &&
1128 gfx9_is_dcc_capable(info, in->swizzleMode)) {
1129 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1130 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1131 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1132
1133 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1134 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1135 dout.pMipInfo = meta_mip_info;
1136
1137 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1138 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1139 din.colorFlags = in->flags;
1140 din.resourceType = in->resourceType;
1141 din.swizzleMode = in->swizzleMode;
1142 din.bpp = in->bpp;
1143 din.unalignedWidth = in->width;
1144 din.unalignedHeight = in->height;
1145 din.numSlices = in->numSlices;
1146 din.numFrags = in->numFrags;
1147 din.numMipLevels = in->numMipLevels;
1148 din.dataSurfaceSize = out.surfSize;
1149 din.firstMipIdInTail = out.firstMipIdInTail;
1150
1151 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1152 if (ret != ADDR_OK)
1153 return ret;
1154
1155 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1156 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1157 surf->dcc_size = dout.dccRamSize;
1158 surf->dcc_alignment = dout.dccRamBaseAlign;
1159 surf->num_dcc_levels = in->numMipLevels;
1160
1161 /* Disable DCC for levels that are in the mip tail.
1162 *
1163 * There are two issues that this is intended to
1164 * address:
1165 *
1166 * 1. Multiple mip levels may share a cache line. This
1167 * can lead to corruption when switching between
1168 * rendering to different mip levels because the
1169 * RBs don't maintain coherency.
1170 *
1171 * 2. Texturing with metadata after rendering sometimes
1172 * fails with corruption, probably for a similar
1173 * reason.
1174 *
1175 * Working around these issues for all levels in the
1176 * mip tail may be overly conservative, but it's what
1177 * Vulkan does.
1178 *
1179 * Alternative solutions that also work but are worse:
1180 * - Disable DCC entirely.
1181 * - Flush TC L2 after rendering.
1182 */
1183 for (unsigned i = 0; i < in->numMipLevels; i++) {
1184 if (meta_mip_info[i].inMiptail) {
1185 surf->num_dcc_levels = i;
1186 break;
1187 }
1188 }
1189
1190 if (!surf->num_dcc_levels)
1191 surf->dcc_size = 0;
1192
1193 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1194 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1195 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1196
1197 /* Compute displayable DCC. */
1198 if (in->flags.display &&
1199 surf->num_dcc_levels &&
1200 info->use_display_dcc_with_retile_blit) {
1201 /* Compute displayable DCC info. */
1202 din.dccKeyFlags.pipeAligned = 0;
1203 din.dccKeyFlags.rbAligned = 0;
1204
1205 assert(din.numSlices == 1);
1206 assert(din.numMipLevels == 1);
1207 assert(din.numFrags == 1);
1208 assert(surf->tile_swizzle == 0);
1209 assert(surf->u.gfx9.dcc.pipe_aligned ||
1210 surf->u.gfx9.dcc.rb_aligned);
1211
1212 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1213 if (ret != ADDR_OK)
1214 return ret;
1215
1216 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1217 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1218 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1219 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1220
1221 /* Compute address mapping from non-displayable to displayable DCC. */
1222 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1223 addrin.size = sizeof(addrin);
1224 addrin.colorFlags.color = 1;
1225 addrin.swizzleMode = din.swizzleMode;
1226 addrin.resourceType = din.resourceType;
1227 addrin.bpp = din.bpp;
1228 addrin.unalignedWidth = din.unalignedWidth;
1229 addrin.unalignedHeight = din.unalignedHeight;
1230 addrin.numSlices = 1;
1231 addrin.numMipLevels = 1;
1232 addrin.numFrags = 1;
1233
1234 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1235 addrout.size = sizeof(addrout);
1236
1237 surf->u.gfx9.dcc_retile_num_elements =
1238 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1239 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1240 /* Align the size to 4 (for the compute shader). */
1241 surf->u.gfx9.dcc_retile_num_elements =
1242 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1243
1244 surf->u.gfx9.dcc_retile_map =
1245 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1246 if (!surf->u.gfx9.dcc_retile_map)
1247 return ADDR_OUTOFMEMORY;
1248
1249 unsigned index = 0;
1250 surf->u.gfx9.dcc_retile_use_uint16 = true;
1251
1252 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1253 addrin.y = y;
1254
1255 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1256 addrin.x = x;
1257
1258 /* Compute src DCC address */
1259 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1260 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1261 addrout.addr = 0;
1262
1263 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1264 if (ret != ADDR_OK)
1265 return ret;
1266
1267 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1268 if (addrout.addr > UINT16_MAX)
1269 surf->u.gfx9.dcc_retile_use_uint16 = false;
1270
1271 /* Compute dst DCC address */
1272 addrin.dccKeyFlags.pipeAligned = 0;
1273 addrin.dccKeyFlags.rbAligned = 0;
1274 addrout.addr = 0;
1275
1276 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1277 if (ret != ADDR_OK)
1278 return ret;
1279
1280 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1281 if (addrout.addr > UINT16_MAX)
1282 surf->u.gfx9.dcc_retile_use_uint16 = false;
1283
1284 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1285 index++;
1286 }
1287 }
1288 /* Fill the remaining pairs with the last one (for the compute shader). */
1289 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1290 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1291 }
1292 }
1293
1294 /* FMASK */
1295 if (in->numSamples > 1) {
1296 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1297 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1298
1299 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1300 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1301
1302 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1303 true, &fin.swizzleMode);
1304 if (ret != ADDR_OK)
1305 return ret;
1306
1307 fin.unalignedWidth = in->width;
1308 fin.unalignedHeight = in->height;
1309 fin.numSlices = in->numSlices;
1310 fin.numSamples = in->numSamples;
1311 fin.numFrags = in->numFrags;
1312
1313 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1314 if (ret != ADDR_OK)
1315 return ret;
1316
1317 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1318 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1319 surf->fmask_size = fout.fmaskBytes;
1320 surf->fmask_alignment = fout.baseAlign;
1321
1322 /* Compute tile swizzle for the FMASK surface. */
1323 if (config->info.fmask_surf_index &&
1324 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1325 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1326 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1327 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1328
1329 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1330 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1331
1332 /* This counter starts from 1 instead of 0. */
1333 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1334 xin.flags = in->flags;
1335 xin.swizzleMode = fin.swizzleMode;
1336 xin.resourceType = in->resourceType;
1337 xin.format = in->format;
1338 xin.numSamples = in->numSamples;
1339 xin.numFrags = in->numFrags;
1340
1341 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1342 if (ret != ADDR_OK)
1343 return ret;
1344
1345 assert(xout.pipeBankXor <=
1346 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1347 surf->fmask_tile_swizzle = xout.pipeBankXor;
1348 }
1349 }
1350
1351 /* CMASK -- on GFX10 only for FMASK */
1352 if (in->swizzleMode != ADDR_SW_LINEAR &&
1353 (info->chip_class <= GFX9 || in->numSamples > 1)) {
1354 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1355 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1356
1357 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1358 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1359
1360 if (in->numSamples > 1) {
1361 /* FMASK is always aligned. */
1362 cin.cMaskFlags.pipeAligned = 1;
1363 cin.cMaskFlags.rbAligned = 1;
1364 } else {
1365 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1366 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1367 }
1368 cin.colorFlags = in->flags;
1369 cin.resourceType = in->resourceType;
1370 cin.unalignedWidth = in->width;
1371 cin.unalignedHeight = in->height;
1372 cin.numSlices = in->numSlices;
1373
1374 if (in->numSamples > 1)
1375 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1376 else
1377 cin.swizzleMode = in->swizzleMode;
1378
1379 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1380 if (ret != ADDR_OK)
1381 return ret;
1382
1383 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1384 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1385 surf->cmask_size = cout.cmaskBytes;
1386 surf->cmask_alignment = cout.baseAlign;
1387 }
1388 }
1389
1390 return 0;
1391 }
1392
1393 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1394 const struct radeon_info *info,
1395 const struct ac_surf_config *config,
1396 enum radeon_surf_mode mode,
1397 struct radeon_surf *surf)
1398 {
1399 bool compressed;
1400 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1401 int r;
1402
1403 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1404
1405 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1406
1407 /* The format must be set correctly for the allocation of compressed
1408 * textures to work. In other cases, setting the bpp is sufficient. */
1409 if (compressed) {
1410 switch (surf->bpe) {
1411 case 8:
1412 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1413 break;
1414 case 16:
1415 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1416 break;
1417 default:
1418 assert(0);
1419 }
1420 } else {
1421 switch (surf->bpe) {
1422 case 1:
1423 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1424 AddrSurfInfoIn.format = ADDR_FMT_8;
1425 break;
1426 case 2:
1427 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1428 !(surf->flags & RADEON_SURF_SBUFFER));
1429 AddrSurfInfoIn.format = ADDR_FMT_16;
1430 break;
1431 case 4:
1432 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1433 !(surf->flags & RADEON_SURF_SBUFFER));
1434 AddrSurfInfoIn.format = ADDR_FMT_32;
1435 break;
1436 case 8:
1437 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1438 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1439 break;
1440 case 12:
1441 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1442 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1443 break;
1444 case 16:
1445 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1446 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1447 break;
1448 default:
1449 assert(0);
1450 }
1451 AddrSurfInfoIn.bpp = surf->bpe * 8;
1452 }
1453
1454 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1455 AddrSurfInfoIn.flags.color = is_color_surface &&
1456 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1457 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1458 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1459 /* flags.texture currently refers to TC-compatible HTILE */
1460 AddrSurfInfoIn.flags.texture = is_color_surface ||
1461 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1462 AddrSurfInfoIn.flags.opt4space = 1;
1463
1464 AddrSurfInfoIn.numMipLevels = config->info.levels;
1465 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1466 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1467
1468 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1469 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1470
1471 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1472 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1473 * must sample 1D textures as 2D. */
1474 if (config->is_3d)
1475 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1476 else if (info->chip_class != GFX9 && config->is_1d)
1477 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
1478 else
1479 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1480
1481 AddrSurfInfoIn.width = config->info.width;
1482 AddrSurfInfoIn.height = config->info.height;
1483
1484 if (config->is_3d)
1485 AddrSurfInfoIn.numSlices = config->info.depth;
1486 else if (config->is_cube)
1487 AddrSurfInfoIn.numSlices = 6;
1488 else
1489 AddrSurfInfoIn.numSlices = config->info.array_size;
1490
1491 /* This is propagated to HTILE/DCC/CMASK. */
1492 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1493 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1494
1495 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1496 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1497 *
1498 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1499 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1500 * after rendering, so PIPE_ALIGNED=1 is recommended.
1501 */
1502 if (info->use_display_dcc_unaligned && is_color_surface &&
1503 AddrSurfInfoIn.flags.display) {
1504 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1505 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1506 }
1507
1508 switch (mode) {
1509 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1510 assert(config->info.samples <= 1);
1511 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1512 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1513 break;
1514
1515 case RADEON_SURF_MODE_1D:
1516 case RADEON_SURF_MODE_2D:
1517 if (surf->flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FORCE_SWIZZLE_MODE)) {
1518 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1519 break;
1520 }
1521
1522 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1523 false, &AddrSurfInfoIn.swizzleMode);
1524 if (r)
1525 return r;
1526 break;
1527
1528 default:
1529 assert(0);
1530 }
1531
1532 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1533 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1534
1535 surf->num_dcc_levels = 0;
1536 surf->surf_size = 0;
1537 surf->fmask_size = 0;
1538 surf->dcc_size = 0;
1539 surf->htile_size = 0;
1540 surf->htile_slice_size = 0;
1541 surf->u.gfx9.surf_offset = 0;
1542 surf->u.gfx9.stencil_offset = 0;
1543 surf->cmask_size = 0;
1544 surf->u.gfx9.dcc_retile_use_uint16 = false;
1545 surf->u.gfx9.dcc_retile_num_elements = 0;
1546 surf->u.gfx9.dcc_retile_map = NULL;
1547
1548 /* Calculate texture layout information. */
1549 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1550 &AddrSurfInfoIn);
1551 if (r)
1552 goto error;
1553
1554 /* Calculate texture layout information for stencil. */
1555 if (surf->flags & RADEON_SURF_SBUFFER) {
1556 AddrSurfInfoIn.flags.stencil = 1;
1557 AddrSurfInfoIn.bpp = 8;
1558 AddrSurfInfoIn.format = ADDR_FMT_8;
1559
1560 if (!AddrSurfInfoIn.flags.depth) {
1561 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1562 false, &AddrSurfInfoIn.swizzleMode);
1563 if (r)
1564 goto error;
1565 } else
1566 AddrSurfInfoIn.flags.depth = 0;
1567
1568 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1569 &AddrSurfInfoIn);
1570 if (r)
1571 goto error;
1572 }
1573
1574 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1575
1576 /* Query whether the surface is displayable. */
1577 bool displayable = false;
1578 if (!config->is_3d && !config->is_cube) {
1579 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1580 surf->bpe * 8, &displayable);
1581 if (r)
1582 goto error;
1583
1584 /* Display needs unaligned DCC. */
1585 if (info->use_display_dcc_unaligned &&
1586 surf->num_dcc_levels &&
1587 (surf->u.gfx9.dcc.pipe_aligned ||
1588 surf->u.gfx9.dcc.rb_aligned))
1589 displayable = false;
1590 }
1591 surf->is_displayable = displayable;
1592
1593 switch (surf->u.gfx9.surf.swizzle_mode) {
1594 /* S = standard. */
1595 case ADDR_SW_256B_S:
1596 case ADDR_SW_4KB_S:
1597 case ADDR_SW_64KB_S:
1598 case ADDR_SW_VAR_S:
1599 case ADDR_SW_64KB_S_T:
1600 case ADDR_SW_4KB_S_X:
1601 case ADDR_SW_64KB_S_X:
1602 case ADDR_SW_VAR_S_X:
1603 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1604 break;
1605
1606 /* D = display. */
1607 case ADDR_SW_LINEAR:
1608 case ADDR_SW_256B_D:
1609 case ADDR_SW_4KB_D:
1610 case ADDR_SW_64KB_D:
1611 case ADDR_SW_VAR_D:
1612 case ADDR_SW_64KB_D_T:
1613 case ADDR_SW_4KB_D_X:
1614 case ADDR_SW_64KB_D_X:
1615 case ADDR_SW_VAR_D_X:
1616 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1617 break;
1618
1619 /* R = rotated (gfx9), render target (gfx10). */
1620 case ADDR_SW_256B_R:
1621 case ADDR_SW_4KB_R:
1622 case ADDR_SW_64KB_R:
1623 case ADDR_SW_VAR_R:
1624 case ADDR_SW_64KB_R_T:
1625 case ADDR_SW_4KB_R_X:
1626 case ADDR_SW_64KB_R_X:
1627 case ADDR_SW_VAR_R_X:
1628 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1629 * used at the same time. We currently do not use rotated
1630 * in gfx9.
1631 */
1632 assert(info->chip_class >= GFX10 ||
1633 !"rotate micro tile mode is unsupported");
1634 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1635 break;
1636
1637 /* Z = depth. */
1638 case ADDR_SW_4KB_Z:
1639 case ADDR_SW_64KB_Z:
1640 case ADDR_SW_VAR_Z:
1641 case ADDR_SW_64KB_Z_T:
1642 case ADDR_SW_4KB_Z_X:
1643 case ADDR_SW_64KB_Z_X:
1644 case ADDR_SW_VAR_Z_X:
1645 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1646 break;
1647
1648 default:
1649 assert(0);
1650 }
1651
1652 return 0;
1653
1654 error:
1655 free(surf->u.gfx9.dcc_retile_map);
1656 surf->u.gfx9.dcc_retile_map = NULL;
1657 return r;
1658 }
1659
1660 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1661 const struct ac_surf_config *config,
1662 enum radeon_surf_mode mode,
1663 struct radeon_surf *surf)
1664 {
1665 int r;
1666
1667 r = surf_config_sanity(config, surf->flags);
1668 if (r)
1669 return r;
1670
1671 if (info->chip_class >= GFX9)
1672 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1673 else
1674 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1675 }