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ac/surface/gfx10: DCC is only supported with SW_64KB_{Z,R}_X modes
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/inc/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
53 {
54 return malloc(pInput->sizeInBytes);
55 }
56
57 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
58 {
59 free(pInput->pVirtAddr);
60 return ADDR_OK;
61 }
62
63 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
64 const struct amdgpu_gpu_info *amdinfo,
65 uint64_t *max_alignment)
66 {
67 ADDR_CREATE_INPUT addrCreateInput = {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
69 ADDR_REGISTER_VALUE regValue = {0};
70 ADDR_CREATE_FLAGS createFlags = {{0}};
71 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
72 ADDR_E_RETURNCODE addrRet;
73
74 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
75 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
76
77 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
78 createFlags.value = 0;
79
80 addrCreateInput.chipFamily = info->family_id;
81 addrCreateInput.chipRevision = info->chip_external_rev;
82
83 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
84 return NULL;
85
86 if (addrCreateInput.chipFamily >= FAMILY_AI) {
87 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
88 regValue.blockVarSizeLog2 = 0;
89 } else {
90 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
91 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
92
93 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
94 regValue.pTileConfig = amdinfo->gb_tile_mode;
95 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
96 if (addrCreateInput.chipFamily == FAMILY_SI) {
97 regValue.pMacroTileConfig = NULL;
98 regValue.noOfMacroEntries = 0;
99 } else {
100 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
101 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
102 }
103
104 createFlags.useTileIndex = 1;
105 createFlags.useHtileSliceAlign = 1;
106
107 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
108 }
109
110 addrCreateInput.callbacks.allocSysMem = allocSysMem;
111 addrCreateInput.callbacks.freeSysMem = freeSysMem;
112 addrCreateInput.callbacks.debugPrint = 0;
113 addrCreateInput.createFlags = createFlags;
114 addrCreateInput.regValue = regValue;
115
116 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
117 if (addrRet != ADDR_OK)
118 return NULL;
119
120 if (max_alignment) {
121 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
122 if (addrRet == ADDR_OK){
123 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
124 }
125 }
126 return addrCreateOutput.hLib;
127 }
128
129 static int surf_config_sanity(const struct ac_surf_config *config,
130 unsigned flags)
131 {
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
134 */
135 assert(!(flags & RADEON_SURF_FMASK));
136 if (flags & RADEON_SURF_FMASK)
137 return -EINVAL;
138
139 /* all dimension must be at least 1 ! */
140 if (!config->info.width || !config->info.height || !config->info.depth ||
141 !config->info.array_size || !config->info.levels)
142 return -EINVAL;
143
144 switch (config->info.samples) {
145 case 0:
146 case 1:
147 case 2:
148 case 4:
149 case 8:
150 break;
151 case 16:
152 if (flags & RADEON_SURF_Z_OR_SBUFFER)
153 return -EINVAL;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
160 switch (config->info.storage_samples) {
161 case 0:
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 break;
167 default:
168 return -EINVAL;
169 }
170 }
171
172 if (config->is_3d && config->info.array_size > 1)
173 return -EINVAL;
174 if (config->is_cube && config->info.depth > 1)
175 return -EINVAL;
176
177 return 0;
178 }
179
180 static int gfx6_compute_level(ADDR_HANDLE addrlib,
181 const struct ac_surf_config *config,
182 struct radeon_surf *surf, bool is_stencil,
183 unsigned level, bool compressed,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
186 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
187 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
188 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
190 {
191 struct legacy_surf_level *surf_level;
192 ADDR_E_RETURNCODE ret;
193
194 AddrSurfInfoIn->mipLevel = level;
195 AddrSurfInfoIn->width = u_minify(config->info.width, level);
196 AddrSurfInfoIn->height = u_minify(config->info.height, level);
197
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
200 */
201 if (config->info.levels == 1 &&
202 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
203 AddrSurfInfoIn->bpp &&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
205 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
206
207 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
208 }
209
210 if (config->is_3d)
211 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
212 else if (config->is_cube)
213 AddrSurfInfoIn->numSlices = 6;
214 else
215 AddrSurfInfoIn->numSlices = config->info.array_size;
216
217 if (level > 0) {
218 /* Set the base level pitch. This is needed for calculation
219 * of non-zero levels. */
220 if (is_stencil)
221 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
222 else
223 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
224
225 /* Convert blocks to pixels for compressed formats. */
226 if (compressed)
227 AddrSurfInfoIn->basePitch *= surf->blk_w;
228 }
229
230 ret = AddrComputeSurfaceInfo(addrlib,
231 AddrSurfInfoIn,
232 AddrSurfInfoOut);
233 if (ret != ADDR_OK) {
234 return ret;
235 }
236
237 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
238 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
239 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
240 surf_level->nblk_x = AddrSurfInfoOut->pitch;
241 surf_level->nblk_y = AddrSurfInfoOut->height;
242
243 switch (AddrSurfInfoOut->tileMode) {
244 case ADDR_TM_LINEAR_ALIGNED:
245 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
246 break;
247 case ADDR_TM_1D_TILED_THIN1:
248 surf_level->mode = RADEON_SURF_MODE_1D;
249 break;
250 case ADDR_TM_2D_TILED_THIN1:
251 surf_level->mode = RADEON_SURF_MODE_2D;
252 break;
253 default:
254 assert(0);
255 }
256
257 if (is_stencil)
258 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
259 else
260 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
261
262 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
263
264 /* Clear DCC fields at the beginning. */
265 surf_level->dcc_offset = 0;
266
267 /* The previous level's flag tells us if we can use DCC for this level. */
268 if (AddrSurfInfoIn->flags.dccCompatible &&
269 (level == 0 || AddrDccOut->subLvlCompressible)) {
270 bool prev_level_clearable = level == 0 ||
271 AddrDccOut->dccRamSizeAligned;
272
273 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
274 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
275 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
276 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
277 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
278
279 ret = AddrComputeDccInfo(addrlib,
280 AddrDccIn,
281 AddrDccOut);
282
283 if (ret == ADDR_OK) {
284 surf_level->dcc_offset = surf->dcc_size;
285 surf->num_dcc_levels = level + 1;
286 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
287 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
288
289 /* If the DCC size of a subresource (1 mip level or 1 slice)
290 * is not aligned, the DCC memory layout is not contiguous for
291 * that subresource, which means we can't use fast clear.
292 *
293 * We only do fast clears for whole mipmap levels. If we did
294 * per-slice fast clears, the same restriction would apply.
295 * (i.e. only compute the slice size and see if it's aligned)
296 *
297 * The last level can be non-contiguous and still be clearable
298 * if it's interleaved with the next level that doesn't exist.
299 */
300 if (AddrDccOut->dccRamSizeAligned ||
301 (prev_level_clearable && level == config->info.levels - 1))
302 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
303 else
304 surf_level->dcc_fast_clear_size = 0;
305
306 /* Compute the DCC slice size because addrlib doesn't
307 * provide this info. As DCC memory is linear (each
308 * slice is the same size) it's easy to compute.
309 */
310 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
311
312 /* For arrays, we have to compute the DCC info again
313 * with one slice size to get a correct fast clear
314 * size.
315 */
316 if (config->info.array_size > 1) {
317 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
318 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
319 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
320 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
321 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
322
323 ret = AddrComputeDccInfo(addrlib,
324 AddrDccIn, AddrDccOut);
325 if (ret == ADDR_OK) {
326 /* If the DCC memory isn't properly
327 * aligned, the data are interleaved
328 * accross slices.
329 */
330 if (AddrDccOut->dccRamSizeAligned)
331 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
332 else
333 surf_level->dcc_slice_fast_clear_size = 0;
334 }
335 } else {
336 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
337 }
338 }
339 }
340
341 /* TC-compatible HTILE. */
342 if (!is_stencil &&
343 AddrSurfInfoIn->flags.depth &&
344 surf_level->mode == RADEON_SURF_MODE_2D &&
345 level == 0) {
346 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
347 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
348 AddrHtileIn->height = AddrSurfInfoOut->height;
349 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
350 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
351 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
352 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
353 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
354 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
355
356 ret = AddrComputeHtileInfo(addrlib,
357 AddrHtileIn,
358 AddrHtileOut);
359
360 if (ret == ADDR_OK) {
361 surf->htile_size = AddrHtileOut->htileBytes;
362 surf->htile_slice_size = AddrHtileOut->sliceSize;
363 surf->htile_alignment = AddrHtileOut->baseAlign;
364 }
365 }
366
367 return 0;
368 }
369
370 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
371 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
372 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
373
374 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
375 const struct radeon_info *info)
376 {
377 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
378
379 if (info->chip_class >= GFX7)
380 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
381 else
382 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
383 }
384
385 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
386 {
387 unsigned index, tileb;
388
389 tileb = 8 * 8 * surf->bpe;
390 tileb = MIN2(surf->u.legacy.tile_split, tileb);
391
392 for (index = 0; tileb > 64; index++)
393 tileb >>= 1;
394
395 assert(index < 16);
396 return index;
397 }
398
399 static bool get_display_flag(const struct ac_surf_config *config,
400 const struct radeon_surf *surf)
401 {
402 unsigned num_channels = config->info.num_channels;
403 unsigned bpe = surf->bpe;
404
405 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
406 surf->flags & RADEON_SURF_SCANOUT &&
407 config->info.samples <= 1 &&
408 surf->blk_w <= 2 && surf->blk_h == 1) {
409 /* subsampled */
410 if (surf->blk_w == 2 && surf->blk_h == 1)
411 return true;
412
413 if (/* RGBA8 or RGBA16F */
414 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
415 /* R5G6B5 or R5G5B5A1 */
416 (bpe == 2 && num_channels >= 3) ||
417 /* C8 palette */
418 (bpe == 1 && num_channels == 1))
419 return true;
420 }
421 return false;
422 }
423
424 /**
425 * This must be called after the first level is computed.
426 *
427 * Copy surface-global settings like pipe/bank config from level 0 surface
428 * computation, and compute tile swizzle.
429 */
430 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
431 const struct radeon_info *info,
432 const struct ac_surf_config *config,
433 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
434 struct radeon_surf *surf)
435 {
436 surf->surf_alignment = csio->baseAlign;
437 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
438 gfx6_set_micro_tile_mode(surf, info);
439
440 /* For 2D modes only. */
441 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
442 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
443 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
444 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
445 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
446 surf->u.legacy.num_banks = csio->pTileInfo->banks;
447 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
448 } else {
449 surf->u.legacy.macro_tile_index = 0;
450 }
451
452 /* Compute tile swizzle. */
453 /* TODO: fix tile swizzle with mipmapping for GFX6 */
454 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
455 config->info.surf_index &&
456 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
457 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
458 !get_display_flag(config, surf)) {
459 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
460 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
461
462 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
463 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
464
465 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
466 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
467 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
468 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
469 AddrBaseSwizzleIn.tileMode = csio->tileMode;
470
471 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
472 &AddrBaseSwizzleOut);
473 if (r != ADDR_OK)
474 return r;
475
476 assert(AddrBaseSwizzleOut.tileSwizzle <=
477 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
478 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
479 }
480 return 0;
481 }
482
483 static void ac_compute_cmask(const struct radeon_info *info,
484 const struct ac_surf_config *config,
485 struct radeon_surf *surf)
486 {
487 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
488 unsigned num_pipes = info->num_tile_pipes;
489 unsigned cl_width, cl_height;
490
491 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
492 return;
493
494 assert(info->chip_class <= GFX8);
495
496 switch (num_pipes) {
497 case 2:
498 cl_width = 32;
499 cl_height = 16;
500 break;
501 case 4:
502 cl_width = 32;
503 cl_height = 32;
504 break;
505 case 8:
506 cl_width = 64;
507 cl_height = 32;
508 break;
509 case 16: /* Hawaii */
510 cl_width = 64;
511 cl_height = 64;
512 break;
513 default:
514 assert(0);
515 return;
516 }
517
518 unsigned base_align = num_pipes * pipe_interleave_bytes;
519
520 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
521 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
522 unsigned slice_elements = (width * height) / (8*8);
523
524 /* Each element of CMASK is a nibble. */
525 unsigned slice_bytes = slice_elements / 2;
526
527 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
528 if (surf->u.legacy.cmask_slice_tile_max)
529 surf->u.legacy.cmask_slice_tile_max -= 1;
530
531 unsigned num_layers;
532 if (config->is_3d)
533 num_layers = config->info.depth;
534 else if (config->is_cube)
535 num_layers = 6;
536 else
537 num_layers = config->info.array_size;
538
539 surf->cmask_alignment = MAX2(256, base_align);
540 surf->cmask_slice_size = align(slice_bytes, base_align);
541 surf->cmask_size = surf->cmask_slice_size * num_layers;
542 }
543
544 /**
545 * Fill in the tiling information in \p surf based on the given surface config.
546 *
547 * The following fields of \p surf must be initialized by the caller:
548 * blk_w, blk_h, bpe, flags.
549 */
550 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
551 const struct radeon_info *info,
552 const struct ac_surf_config *config,
553 enum radeon_surf_mode mode,
554 struct radeon_surf *surf)
555 {
556 unsigned level;
557 bool compressed;
558 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
559 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
560 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
561 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
562 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
563 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
564 ADDR_TILEINFO AddrTileInfoIn = {0};
565 ADDR_TILEINFO AddrTileInfoOut = {0};
566 int r;
567
568 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
569 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
570 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
571 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
572 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
573 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
574 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
575
576 compressed = surf->blk_w == 4 && surf->blk_h == 4;
577
578 /* MSAA requires 2D tiling. */
579 if (config->info.samples > 1)
580 mode = RADEON_SURF_MODE_2D;
581
582 /* DB doesn't support linear layouts. */
583 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
584 mode < RADEON_SURF_MODE_1D)
585 mode = RADEON_SURF_MODE_1D;
586
587 /* Set the requested tiling mode. */
588 switch (mode) {
589 case RADEON_SURF_MODE_LINEAR_ALIGNED:
590 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
591 break;
592 case RADEON_SURF_MODE_1D:
593 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
594 break;
595 case RADEON_SURF_MODE_2D:
596 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
597 break;
598 default:
599 assert(0);
600 }
601
602 /* The format must be set correctly for the allocation of compressed
603 * textures to work. In other cases, setting the bpp is sufficient.
604 */
605 if (compressed) {
606 switch (surf->bpe) {
607 case 8:
608 AddrSurfInfoIn.format = ADDR_FMT_BC1;
609 break;
610 case 16:
611 AddrSurfInfoIn.format = ADDR_FMT_BC3;
612 break;
613 default:
614 assert(0);
615 }
616 }
617 else {
618 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
619 }
620
621 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
622 MAX2(1, config->info.samples);
623 AddrSurfInfoIn.tileIndex = -1;
624
625 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
626 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
627 MAX2(1, config->info.storage_samples);
628 }
629
630 /* Set the micro tile type. */
631 if (surf->flags & RADEON_SURF_SCANOUT)
632 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
633 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
634 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
635 else
636 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
637
638 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
639 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
640 AddrSurfInfoIn.flags.cube = config->is_cube;
641 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
642 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
643 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
644
645 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
646 * requested, because TC-compatible HTILE requires 2D tiling.
647 */
648 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
649 !AddrSurfInfoIn.flags.fmask &&
650 config->info.samples <= 1 &&
651 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
652
653 /* DCC notes:
654 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
655 * with samples >= 4.
656 * - Mipmapped array textures have low performance (discovered by a closed
657 * driver team).
658 */
659 AddrSurfInfoIn.flags.dccCompatible =
660 info->chip_class >= GFX8 &&
661 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
662 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
663 !compressed &&
664 ((config->info.array_size == 1 && config->info.depth == 1) ||
665 config->info.levels == 1);
666
667 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
668 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
669
670 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
671 * for Z and stencil. This can cause a number of problems which we work
672 * around here:
673 *
674 * - a depth part that is incompatible with mipmapped texturing
675 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
676 * incorrect tiling applied to the stencil part, stencil buffer
677 * memory accesses that go out of bounds) even without mipmapping
678 *
679 * Some piglit tests that are prone to different types of related
680 * failures:
681 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
682 * ./bin/framebuffer-blit-levels {draw,read} stencil
683 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
684 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
685 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
686 */
687 int stencil_tile_idx = -1;
688
689 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
690 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
691 /* Compute stencilTileIdx that is compatible with the (depth)
692 * tileIdx. This degrades the depth surface if necessary to
693 * ensure that a matching stencilTileIdx exists. */
694 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
695
696 /* Keep the depth mip-tail compatible with texturing. */
697 AddrSurfInfoIn.flags.noStencil = 1;
698 }
699
700 /* Set preferred macrotile parameters. This is usually required
701 * for shared resources. This is for 2D tiling only. */
702 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
703 surf->u.legacy.bankw && surf->u.legacy.bankh &&
704 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
705 /* If any of these parameters are incorrect, the calculation
706 * will fail. */
707 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
708 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
709 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
710 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
711 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
712 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
713 AddrSurfInfoIn.flags.opt4Space = 0;
714 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
715
716 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
717 * the tile index, because we are expected to know it if
718 * we know the other parameters.
719 *
720 * This is something that can easily be fixed in Addrlib.
721 * For now, just figure it out here.
722 * Note that only 2D_TILE_THIN1 is handled here.
723 */
724 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
725 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
726
727 if (info->chip_class == GFX6) {
728 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
729 if (surf->bpe == 2)
730 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
731 else
732 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
733 } else {
734 if (surf->bpe == 1)
735 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
736 else if (surf->bpe == 2)
737 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
738 else if (surf->bpe == 4)
739 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
740 else
741 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
742 }
743 } else {
744 /* GFX7 - GFX8 */
745 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
746 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
747 else
748 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
749
750 /* Addrlib doesn't set this if tileIndex is forced like above. */
751 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
752 }
753 }
754
755 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
756 surf->num_dcc_levels = 0;
757 surf->surf_size = 0;
758 surf->dcc_size = 0;
759 surf->dcc_alignment = 1;
760 surf->htile_size = 0;
761 surf->htile_slice_size = 0;
762 surf->htile_alignment = 1;
763
764 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
765 !(surf->flags & RADEON_SURF_ZBUFFER);
766
767 /* Calculate texture layout information. */
768 if (!only_stencil) {
769 for (level = 0; level < config->info.levels; level++) {
770 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
771 &AddrSurfInfoIn, &AddrSurfInfoOut,
772 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
773 if (r)
774 return r;
775
776 if (level > 0)
777 continue;
778
779 /* Check that we actually got a TC-compatible HTILE if
780 * we requested it (only for level 0, since we're not
781 * supporting HTILE on higher mip levels anyway). */
782 assert(AddrSurfInfoOut.tcCompatible ||
783 !AddrSurfInfoIn.flags.tcCompatible ||
784 AddrSurfInfoIn.flags.matchStencilTileCfg);
785
786 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
787 if (!AddrSurfInfoOut.tcCompatible) {
788 AddrSurfInfoIn.flags.tcCompatible = 0;
789 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
790 }
791
792 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
793 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
794 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
795
796 assert(stencil_tile_idx >= 0);
797 }
798
799 r = gfx6_surface_settings(addrlib, info, config,
800 &AddrSurfInfoOut, surf);
801 if (r)
802 return r;
803 }
804 }
805
806 /* Calculate texture layout information for stencil. */
807 if (surf->flags & RADEON_SURF_SBUFFER) {
808 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
809 AddrSurfInfoIn.bpp = 8;
810 AddrSurfInfoIn.flags.depth = 0;
811 AddrSurfInfoIn.flags.stencil = 1;
812 AddrSurfInfoIn.flags.tcCompatible = 0;
813 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
814 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
815
816 for (level = 0; level < config->info.levels; level++) {
817 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
818 &AddrSurfInfoIn, &AddrSurfInfoOut,
819 &AddrDccIn, &AddrDccOut,
820 NULL, NULL);
821 if (r)
822 return r;
823
824 /* DB uses the depth pitch for both stencil and depth. */
825 if (!only_stencil) {
826 if (surf->u.legacy.stencil_level[level].nblk_x !=
827 surf->u.legacy.level[level].nblk_x)
828 surf->u.legacy.stencil_adjusted = true;
829 } else {
830 surf->u.legacy.level[level].nblk_x =
831 surf->u.legacy.stencil_level[level].nblk_x;
832 }
833
834 if (level == 0) {
835 if (only_stencil) {
836 r = gfx6_surface_settings(addrlib, info, config,
837 &AddrSurfInfoOut, surf);
838 if (r)
839 return r;
840 }
841
842 /* For 2D modes only. */
843 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
844 surf->u.legacy.stencil_tile_split =
845 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
846 }
847 }
848 }
849 }
850
851 /* Compute FMASK. */
852 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
853 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
854 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
855 ADDR_TILEINFO fmask_tile_info = {};
856
857 fin.size = sizeof(fin);
858 fout.size = sizeof(fout);
859
860 fin.tileMode = AddrSurfInfoOut.tileMode;
861 fin.pitch = AddrSurfInfoOut.pitch;
862 fin.height = config->info.height;
863 fin.numSlices = AddrSurfInfoIn.numSlices;
864 fin.numSamples = AddrSurfInfoIn.numSamples;
865 fin.numFrags = AddrSurfInfoIn.numFrags;
866 fin.tileIndex = -1;
867 fout.pTileInfo = &fmask_tile_info;
868
869 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
870 if (r)
871 return r;
872
873 surf->fmask_size = fout.fmaskBytes;
874 surf->fmask_alignment = fout.baseAlign;
875 surf->fmask_tile_swizzle = 0;
876
877 surf->u.legacy.fmask.slice_tile_max =
878 (fout.pitch * fout.height) / 64;
879 if (surf->u.legacy.fmask.slice_tile_max)
880 surf->u.legacy.fmask.slice_tile_max -= 1;
881
882 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
883 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
884 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
885 surf->u.legacy.fmask.slice_size = fout.sliceSize;
886
887 /* Compute tile swizzle for FMASK. */
888 if (config->info.fmask_surf_index &&
889 !(surf->flags & RADEON_SURF_SHAREABLE)) {
890 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
891 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
892
893 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
894 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
895
896 /* This counter starts from 1 instead of 0. */
897 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
898 xin.tileIndex = fout.tileIndex;
899 xin.macroModeIndex = fout.macroModeIndex;
900 xin.pTileInfo = fout.pTileInfo;
901 xin.tileMode = fin.tileMode;
902
903 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
904 if (r != ADDR_OK)
905 return r;
906
907 assert(xout.tileSwizzle <=
908 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
909 surf->fmask_tile_swizzle = xout.tileSwizzle;
910 }
911 }
912
913 /* Recalculate the whole DCC miptree size including disabled levels.
914 * This is what addrlib does, but calling addrlib would be a lot more
915 * complicated.
916 */
917 if (surf->dcc_size && config->info.levels > 1) {
918 /* The smallest miplevels that are never compressed by DCC
919 * still read the DCC buffer via TC if the base level uses DCC,
920 * and for some reason the DCC buffer needs to be larger if
921 * the miptree uses non-zero tile_swizzle. Otherwise there are
922 * VM faults.
923 *
924 * "dcc_alignment * 4" was determined by trial and error.
925 */
926 surf->dcc_size = align64(surf->surf_size >> 8,
927 surf->dcc_alignment * 4);
928 }
929
930 /* Make sure HTILE covers the whole miptree, because the shader reads
931 * TC-compatible HTILE even for levels where it's disabled by DB.
932 */
933 if (surf->htile_size && config->info.levels > 1 &&
934 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
935 /* MSAA can't occur with levels > 1, so ignore the sample count. */
936 const unsigned total_pixels = surf->surf_size / surf->bpe;
937 const unsigned htile_block_size = 8 * 8;
938 const unsigned htile_element_size = 4;
939
940 surf->htile_size = (total_pixels / htile_block_size) *
941 htile_element_size;
942 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
943 }
944
945 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
946 surf->is_displayable = surf->is_linear ||
947 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
948 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
949
950 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
951 * used at the same time. This case is not currently expected to occur
952 * because we don't use rotated. Enforce this restriction on all chips
953 * to facilitate testing.
954 */
955 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
956 assert(!"rotate micro tile mode is unsupported");
957 return ADDR_ERROR;
958 }
959
960 ac_compute_cmask(info, config, surf);
961 return 0;
962 }
963
964 /* This is only called when expecting a tiled layout. */
965 static int
966 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
967 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
968 bool is_fmask, AddrSwizzleMode *swizzle_mode)
969 {
970 ADDR_E_RETURNCODE ret;
971 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
972 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
973
974 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
975 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
976
977 sin.flags = in->flags;
978 sin.resourceType = in->resourceType;
979 sin.format = in->format;
980 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
981 /* TODO: We could allow some of these: */
982 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
983 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
984 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
985 sin.bpp = in->bpp;
986 sin.width = in->width;
987 sin.height = in->height;
988 sin.numSlices = in->numSlices;
989 sin.numMipLevels = in->numMipLevels;
990 sin.numSamples = in->numSamples;
991 sin.numFrags = in->numFrags;
992
993 if (is_fmask) {
994 sin.flags.display = 0;
995 sin.flags.color = 0;
996 sin.flags.fmask = 1;
997 }
998
999 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1000 if (ret != ADDR_OK)
1001 return ret;
1002
1003 *swizzle_mode = sout.swizzleMode;
1004 return 0;
1005 }
1006
1007 static bool gfx9_is_dcc_capable(const struct radeon_info *info, unsigned sw_mode)
1008 {
1009 if (info->chip_class >= GFX10)
1010 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1011
1012 return sw_mode != ADDR_SW_LINEAR;
1013 }
1014
1015 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1016 const struct radeon_info *info,
1017 const struct ac_surf_config *config,
1018 struct radeon_surf *surf, bool compressed,
1019 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1020 {
1021 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1022 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1023 ADDR_E_RETURNCODE ret;
1024
1025 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1026 out.pMipInfo = mip_info;
1027
1028 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1029 if (ret != ADDR_OK)
1030 return ret;
1031
1032 if (in->flags.stencil) {
1033 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1034 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1035 out.mipChainPitch - 1;
1036 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1037 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1038 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1039 return 0;
1040 }
1041
1042 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1043 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1044 out.mipChainPitch - 1;
1045
1046 /* CMASK fast clear uses these even if FMASK isn't allocated.
1047 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1048 */
1049 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1050 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1051
1052 surf->u.gfx9.surf_slice_size = out.sliceSize;
1053 surf->u.gfx9.surf_pitch = out.pitch;
1054 surf->u.gfx9.surf_height = out.height;
1055 surf->surf_size = out.surfSize;
1056 surf->surf_alignment = out.baseAlign;
1057
1058 if (in->swizzleMode == ADDR_SW_LINEAR) {
1059 for (unsigned i = 0; i < in->numMipLevels; i++)
1060 surf->u.gfx9.offset[i] = mip_info[i].offset;
1061 }
1062
1063 if (in->flags.depth) {
1064 assert(in->swizzleMode != ADDR_SW_LINEAR);
1065
1066 /* HTILE */
1067 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1068 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1069
1070 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1071 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1072
1073 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1074 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1075 hin.depthFlags = in->flags;
1076 hin.swizzleMode = in->swizzleMode;
1077 hin.unalignedWidth = in->width;
1078 hin.unalignedHeight = in->height;
1079 hin.numSlices = in->numSlices;
1080 hin.numMipLevels = in->numMipLevels;
1081 hin.firstMipIdInTail = out.firstMipIdInTail;
1082
1083 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1084 if (ret != ADDR_OK)
1085 return ret;
1086
1087 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1088 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1089 surf->htile_size = hout.htileBytes;
1090 surf->htile_slice_size = hout.sliceSize;
1091 surf->htile_alignment = hout.baseAlign;
1092 } else {
1093 /* Compute tile swizzle for the color surface.
1094 * All *_X and *_T modes can use the swizzle.
1095 */
1096 if (config->info.surf_index &&
1097 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1098 !out.mipChainInTail &&
1099 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1100 !in->flags.display) {
1101 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1102 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1103
1104 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1105 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1106
1107 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1108 xin.flags = in->flags;
1109 xin.swizzleMode = in->swizzleMode;
1110 xin.resourceType = in->resourceType;
1111 xin.format = in->format;
1112 xin.numSamples = in->numSamples;
1113 xin.numFrags = in->numFrags;
1114
1115 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1116 if (ret != ADDR_OK)
1117 return ret;
1118
1119 assert(xout.pipeBankXor <=
1120 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1121 surf->tile_swizzle = xout.pipeBankXor;
1122 }
1123
1124 /* DCC */
1125 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed &&
1126 gfx9_is_dcc_capable(info, in->swizzleMode)) {
1127 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1128 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1129 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1130
1131 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1132 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1133 dout.pMipInfo = meta_mip_info;
1134
1135 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1136 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1137 din.colorFlags = in->flags;
1138 din.resourceType = in->resourceType;
1139 din.swizzleMode = in->swizzleMode;
1140 din.bpp = in->bpp;
1141 din.unalignedWidth = in->width;
1142 din.unalignedHeight = in->height;
1143 din.numSlices = in->numSlices;
1144 din.numFrags = in->numFrags;
1145 din.numMipLevels = in->numMipLevels;
1146 din.dataSurfaceSize = out.surfSize;
1147 din.firstMipIdInTail = out.firstMipIdInTail;
1148
1149 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1150 if (ret != ADDR_OK)
1151 return ret;
1152
1153 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1154 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1155 surf->dcc_size = dout.dccRamSize;
1156 surf->dcc_alignment = dout.dccRamBaseAlign;
1157 surf->num_dcc_levels = in->numMipLevels;
1158
1159 /* Disable DCC for levels that are in the mip tail.
1160 *
1161 * There are two issues that this is intended to
1162 * address:
1163 *
1164 * 1. Multiple mip levels may share a cache line. This
1165 * can lead to corruption when switching between
1166 * rendering to different mip levels because the
1167 * RBs don't maintain coherency.
1168 *
1169 * 2. Texturing with metadata after rendering sometimes
1170 * fails with corruption, probably for a similar
1171 * reason.
1172 *
1173 * Working around these issues for all levels in the
1174 * mip tail may be overly conservative, but it's what
1175 * Vulkan does.
1176 *
1177 * Alternative solutions that also work but are worse:
1178 * - Disable DCC entirely.
1179 * - Flush TC L2 after rendering.
1180 */
1181 for (unsigned i = 0; i < in->numMipLevels; i++) {
1182 if (meta_mip_info[i].inMiptail) {
1183 surf->num_dcc_levels = i;
1184 break;
1185 }
1186 }
1187
1188 if (!surf->num_dcc_levels)
1189 surf->dcc_size = 0;
1190
1191 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1192 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1193 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1194
1195 /* Compute displayable DCC. */
1196 if (in->flags.display &&
1197 surf->num_dcc_levels &&
1198 info->use_display_dcc_with_retile_blit) {
1199 /* Compute displayable DCC info. */
1200 din.dccKeyFlags.pipeAligned = 0;
1201 din.dccKeyFlags.rbAligned = 0;
1202
1203 assert(din.numSlices == 1);
1204 assert(din.numMipLevels == 1);
1205 assert(din.numFrags == 1);
1206 assert(surf->tile_swizzle == 0);
1207 assert(surf->u.gfx9.dcc.pipe_aligned ||
1208 surf->u.gfx9.dcc.rb_aligned);
1209
1210 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1211 if (ret != ADDR_OK)
1212 return ret;
1213
1214 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1215 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1216 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1217 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1218
1219 /* Compute address mapping from non-displayable to displayable DCC. */
1220 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1221 addrin.size = sizeof(addrin);
1222 addrin.colorFlags.color = 1;
1223 addrin.swizzleMode = din.swizzleMode;
1224 addrin.resourceType = din.resourceType;
1225 addrin.bpp = din.bpp;
1226 addrin.unalignedWidth = din.unalignedWidth;
1227 addrin.unalignedHeight = din.unalignedHeight;
1228 addrin.numSlices = 1;
1229 addrin.numMipLevels = 1;
1230 addrin.numFrags = 1;
1231
1232 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1233 addrout.size = sizeof(addrout);
1234
1235 surf->u.gfx9.dcc_retile_num_elements =
1236 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1237 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1238 /* Align the size to 4 (for the compute shader). */
1239 surf->u.gfx9.dcc_retile_num_elements =
1240 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1241
1242 surf->u.gfx9.dcc_retile_map =
1243 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1244 if (!surf->u.gfx9.dcc_retile_map)
1245 return ADDR_OUTOFMEMORY;
1246
1247 unsigned index = 0;
1248 surf->u.gfx9.dcc_retile_use_uint16 = true;
1249
1250 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1251 addrin.y = y;
1252
1253 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1254 addrin.x = x;
1255
1256 /* Compute src DCC address */
1257 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1258 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1259 addrout.addr = 0;
1260
1261 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1262 if (ret != ADDR_OK)
1263 return ret;
1264
1265 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1266 if (addrout.addr > USHRT_MAX)
1267 surf->u.gfx9.dcc_retile_use_uint16 = false;
1268
1269 /* Compute dst DCC address */
1270 addrin.dccKeyFlags.pipeAligned = 0;
1271 addrin.dccKeyFlags.rbAligned = 0;
1272 addrout.addr = 0;
1273
1274 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1275 if (ret != ADDR_OK)
1276 return ret;
1277
1278 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1279 if (addrout.addr > USHRT_MAX)
1280 surf->u.gfx9.dcc_retile_use_uint16 = false;
1281
1282 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1283 index++;
1284 }
1285 }
1286 /* Fill the remaining pairs with the last one (for the compute shader). */
1287 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1288 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1289 }
1290 }
1291
1292 /* FMASK */
1293 if (in->numSamples > 1) {
1294 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1295 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1296
1297 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1298 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1299
1300 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1301 true, &fin.swizzleMode);
1302 if (ret != ADDR_OK)
1303 return ret;
1304
1305 fin.unalignedWidth = in->width;
1306 fin.unalignedHeight = in->height;
1307 fin.numSlices = in->numSlices;
1308 fin.numSamples = in->numSamples;
1309 fin.numFrags = in->numFrags;
1310
1311 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1312 if (ret != ADDR_OK)
1313 return ret;
1314
1315 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1316 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1317 surf->fmask_size = fout.fmaskBytes;
1318 surf->fmask_alignment = fout.baseAlign;
1319
1320 /* Compute tile swizzle for the FMASK surface. */
1321 if (config->info.fmask_surf_index &&
1322 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1323 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1324 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1325 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1326
1327 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1328 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1329
1330 /* This counter starts from 1 instead of 0. */
1331 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1332 xin.flags = in->flags;
1333 xin.swizzleMode = fin.swizzleMode;
1334 xin.resourceType = in->resourceType;
1335 xin.format = in->format;
1336 xin.numSamples = in->numSamples;
1337 xin.numFrags = in->numFrags;
1338
1339 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1340 if (ret != ADDR_OK)
1341 return ret;
1342
1343 assert(xout.pipeBankXor <=
1344 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1345 surf->fmask_tile_swizzle = xout.pipeBankXor;
1346 }
1347 }
1348
1349 /* CMASK -- on GFX10 only for FMASK */
1350 if (in->swizzleMode != ADDR_SW_LINEAR &&
1351 (info->chip_class <= GFX9 || in->numSamples > 1)) {
1352 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1353 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1354
1355 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1356 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1357
1358 if (in->numSamples > 1) {
1359 /* FMASK is always aligned. */
1360 cin.cMaskFlags.pipeAligned = 1;
1361 cin.cMaskFlags.rbAligned = 1;
1362 } else {
1363 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1364 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1365 }
1366 cin.colorFlags = in->flags;
1367 cin.resourceType = in->resourceType;
1368 cin.unalignedWidth = in->width;
1369 cin.unalignedHeight = in->height;
1370 cin.numSlices = in->numSlices;
1371
1372 if (in->numSamples > 1)
1373 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1374 else
1375 cin.swizzleMode = in->swizzleMode;
1376
1377 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1378 if (ret != ADDR_OK)
1379 return ret;
1380
1381 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1382 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1383 surf->cmask_size = cout.cmaskBytes;
1384 surf->cmask_alignment = cout.baseAlign;
1385 }
1386 }
1387
1388 return 0;
1389 }
1390
1391 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1392 const struct radeon_info *info,
1393 const struct ac_surf_config *config,
1394 enum radeon_surf_mode mode,
1395 struct radeon_surf *surf)
1396 {
1397 bool compressed;
1398 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1399 int r;
1400
1401 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1402
1403 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1404
1405 /* The format must be set correctly for the allocation of compressed
1406 * textures to work. In other cases, setting the bpp is sufficient. */
1407 if (compressed) {
1408 switch (surf->bpe) {
1409 case 8:
1410 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1411 break;
1412 case 16:
1413 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1414 break;
1415 default:
1416 assert(0);
1417 }
1418 } else {
1419 switch (surf->bpe) {
1420 case 1:
1421 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1422 AddrSurfInfoIn.format = ADDR_FMT_8;
1423 break;
1424 case 2:
1425 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1426 !(surf->flags & RADEON_SURF_SBUFFER));
1427 AddrSurfInfoIn.format = ADDR_FMT_16;
1428 break;
1429 case 4:
1430 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1431 !(surf->flags & RADEON_SURF_SBUFFER));
1432 AddrSurfInfoIn.format = ADDR_FMT_32;
1433 break;
1434 case 8:
1435 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1436 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1437 break;
1438 case 12:
1439 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1440 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1441 break;
1442 case 16:
1443 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1444 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1445 break;
1446 default:
1447 assert(0);
1448 }
1449 AddrSurfInfoIn.bpp = surf->bpe * 8;
1450 }
1451
1452 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1453 AddrSurfInfoIn.flags.color = is_color_surface &&
1454 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1455 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1456 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1457 /* flags.texture currently refers to TC-compatible HTILE */
1458 AddrSurfInfoIn.flags.texture = is_color_surface ||
1459 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1460 AddrSurfInfoIn.flags.opt4space = 1;
1461
1462 AddrSurfInfoIn.numMipLevels = config->info.levels;
1463 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1464 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1465
1466 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1467 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1468
1469 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1470 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1471 * must sample 1D textures as 2D. */
1472 if (config->is_3d)
1473 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1474 else
1475 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1476
1477 AddrSurfInfoIn.width = config->info.width;
1478 AddrSurfInfoIn.height = config->info.height;
1479
1480 if (config->is_3d)
1481 AddrSurfInfoIn.numSlices = config->info.depth;
1482 else if (config->is_cube)
1483 AddrSurfInfoIn.numSlices = 6;
1484 else
1485 AddrSurfInfoIn.numSlices = config->info.array_size;
1486
1487 /* This is propagated to HTILE/DCC/CMASK. */
1488 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1489 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1490
1491 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1492 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1493 *
1494 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1495 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1496 * after rendering, so PIPE_ALIGNED=1 is recommended.
1497 */
1498 if (info->use_display_dcc_unaligned && is_color_surface &&
1499 AddrSurfInfoIn.flags.display) {
1500 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1501 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1502 }
1503
1504 switch (mode) {
1505 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1506 assert(config->info.samples <= 1);
1507 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1508 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1509 break;
1510
1511 case RADEON_SURF_MODE_1D:
1512 case RADEON_SURF_MODE_2D:
1513 if (surf->flags & RADEON_SURF_IMPORTED) {
1514 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1515 break;
1516 }
1517
1518 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1519 false, &AddrSurfInfoIn.swizzleMode);
1520 if (r)
1521 return r;
1522 break;
1523
1524 default:
1525 assert(0);
1526 }
1527
1528 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1529 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1530
1531 surf->num_dcc_levels = 0;
1532 surf->surf_size = 0;
1533 surf->fmask_size = 0;
1534 surf->dcc_size = 0;
1535 surf->htile_size = 0;
1536 surf->htile_slice_size = 0;
1537 surf->u.gfx9.surf_offset = 0;
1538 surf->u.gfx9.stencil_offset = 0;
1539 surf->cmask_size = 0;
1540 surf->u.gfx9.dcc_retile_use_uint16 = false;
1541 surf->u.gfx9.dcc_retile_num_elements = 0;
1542 surf->u.gfx9.dcc_retile_map = NULL;
1543
1544 /* Calculate texture layout information. */
1545 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1546 &AddrSurfInfoIn);
1547 if (r)
1548 goto error;
1549
1550 /* Calculate texture layout information for stencil. */
1551 if (surf->flags & RADEON_SURF_SBUFFER) {
1552 AddrSurfInfoIn.flags.stencil = 1;
1553 AddrSurfInfoIn.bpp = 8;
1554 AddrSurfInfoIn.format = ADDR_FMT_8;
1555
1556 if (!AddrSurfInfoIn.flags.depth) {
1557 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1558 false, &AddrSurfInfoIn.swizzleMode);
1559 if (r)
1560 goto error;
1561 } else
1562 AddrSurfInfoIn.flags.depth = 0;
1563
1564 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1565 &AddrSurfInfoIn);
1566 if (r)
1567 goto error;
1568 }
1569
1570 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1571
1572 /* Query whether the surface is displayable. */
1573 bool displayable = false;
1574 if (!config->is_3d && !config->is_cube) {
1575 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1576 surf->bpe * 8, &displayable);
1577 if (r)
1578 goto error;
1579
1580 /* Display needs unaligned DCC. */
1581 if (info->use_display_dcc_unaligned &&
1582 surf->num_dcc_levels &&
1583 (surf->u.gfx9.dcc.pipe_aligned ||
1584 surf->u.gfx9.dcc.rb_aligned))
1585 displayable = false;
1586 }
1587 surf->is_displayable = displayable;
1588
1589 switch (surf->u.gfx9.surf.swizzle_mode) {
1590 /* S = standard. */
1591 case ADDR_SW_256B_S:
1592 case ADDR_SW_4KB_S:
1593 case ADDR_SW_64KB_S:
1594 case ADDR_SW_VAR_S:
1595 case ADDR_SW_64KB_S_T:
1596 case ADDR_SW_4KB_S_X:
1597 case ADDR_SW_64KB_S_X:
1598 case ADDR_SW_VAR_S_X:
1599 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1600 break;
1601
1602 /* D = display. */
1603 case ADDR_SW_LINEAR:
1604 case ADDR_SW_256B_D:
1605 case ADDR_SW_4KB_D:
1606 case ADDR_SW_64KB_D:
1607 case ADDR_SW_VAR_D:
1608 case ADDR_SW_64KB_D_T:
1609 case ADDR_SW_4KB_D_X:
1610 case ADDR_SW_64KB_D_X:
1611 case ADDR_SW_VAR_D_X:
1612 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1613 break;
1614
1615 /* R = rotated. */
1616 case ADDR_SW_256B_R:
1617 case ADDR_SW_4KB_R:
1618 case ADDR_SW_64KB_R:
1619 case ADDR_SW_VAR_R:
1620 case ADDR_SW_64KB_R_T:
1621 case ADDR_SW_4KB_R_X:
1622 case ADDR_SW_64KB_R_X:
1623 case ADDR_SW_VAR_R_X:
1624 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1625 * used at the same time. This case is not currently expected to occur
1626 * because we don't use rotated. Enforce this restriction on all chips
1627 * to facilitate testing.
1628 */
1629 assert(!"rotate micro tile mode is unsupported");
1630 r = ADDR_ERROR;
1631 goto error;
1632
1633 /* Z = depth. */
1634 case ADDR_SW_4KB_Z:
1635 case ADDR_SW_64KB_Z:
1636 case ADDR_SW_VAR_Z:
1637 case ADDR_SW_64KB_Z_T:
1638 case ADDR_SW_4KB_Z_X:
1639 case ADDR_SW_64KB_Z_X:
1640 case ADDR_SW_VAR_Z_X:
1641 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1642 break;
1643
1644 default:
1645 assert(0);
1646 }
1647
1648 return 0;
1649
1650 error:
1651 free(surf->u.gfx9.dcc_retile_map);
1652 surf->u.gfx9.dcc_retile_map = NULL;
1653 return r;
1654 }
1655
1656 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1657 const struct ac_surf_config *config,
1658 enum radeon_surf_mode mode,
1659 struct radeon_surf *surf)
1660 {
1661 int r;
1662
1663 r = surf_config_sanity(config, surf->flags);
1664 if (r)
1665 return r;
1666
1667 if (info->chip_class >= GFX9)
1668 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1669 else
1670 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1671 }