projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ac/surface: set SCANOUT if surf->is_displayable
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35 #include "sid.h"
36
37 #include <errno.h>
38 #include <stdio.h>
39 #include <stdlib.h>
40 #include <amdgpu.h>
41 #include "drm-uapi/amdgpu_drm.h"
42
43 #include "addrlib/inc/addrinterface.h"
44
45 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
46 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
47 #endif
48
49 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
50 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
51 #endif
52
53 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
54 {
55 return malloc(pInput->sizeInBytes);
56 }
57
58 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
59 {
60 free(pInput->pVirtAddr);
61 return ADDR_OK;
62 }
63
64 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
65 const struct amdgpu_gpu_info *amdinfo,
66 uint64_t *max_alignment)
67 {
68 ADDR_CREATE_INPUT addrCreateInput = {0};
69 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
70 ADDR_REGISTER_VALUE regValue = {0};
71 ADDR_CREATE_FLAGS createFlags = {{0}};
72 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
73 ADDR_E_RETURNCODE addrRet;
74
75 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
76 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
77
78 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
79 createFlags.value = 0;
80
81 addrCreateInput.chipFamily = info->family_id;
82 addrCreateInput.chipRevision = info->chip_external_rev;
83
84 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
85 return NULL;
86
87 if (addrCreateInput.chipFamily >= FAMILY_AI) {
88 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
89 } else {
90 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
91 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
92
93 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
94 regValue.pTileConfig = amdinfo->gb_tile_mode;
95 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
96 if (addrCreateInput.chipFamily == FAMILY_SI) {
97 regValue.pMacroTileConfig = NULL;
98 regValue.noOfMacroEntries = 0;
99 } else {
100 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
101 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
102 }
103
104 createFlags.useTileIndex = 1;
105 createFlags.useHtileSliceAlign = 1;
106
107 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
108 }
109
110 addrCreateInput.callbacks.allocSysMem = allocSysMem;
111 addrCreateInput.callbacks.freeSysMem = freeSysMem;
112 addrCreateInput.callbacks.debugPrint = 0;
113 addrCreateInput.createFlags = createFlags;
114 addrCreateInput.regValue = regValue;
115
116 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
117 if (addrRet != ADDR_OK)
118 return NULL;
119
120 if (max_alignment) {
121 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
122 if (addrRet == ADDR_OK){
123 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
124 }
125 }
126 return addrCreateOutput.hLib;
127 }
128
129 static int surf_config_sanity(const struct ac_surf_config *config,
130 unsigned flags)
131 {
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
134 */
135 assert(!(flags & RADEON_SURF_FMASK));
136 if (flags & RADEON_SURF_FMASK)
137 return -EINVAL;
138
139 /* all dimension must be at least 1 ! */
140 if (!config->info.width || !config->info.height || !config->info.depth ||
141 !config->info.array_size || !config->info.levels)
142 return -EINVAL;
143
144 switch (config->info.samples) {
145 case 0:
146 case 1:
147 case 2:
148 case 4:
149 case 8:
150 break;
151 case 16:
152 if (flags & RADEON_SURF_Z_OR_SBUFFER)
153 return -EINVAL;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
160 switch (config->info.storage_samples) {
161 case 0:
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 break;
167 default:
168 return -EINVAL;
169 }
170 }
171
172 if (config->is_3d && config->info.array_size > 1)
173 return -EINVAL;
174 if (config->is_cube && config->info.depth > 1)
175 return -EINVAL;
176
177 return 0;
178 }
179
180 static int gfx6_compute_level(ADDR_HANDLE addrlib,
181 const struct ac_surf_config *config,
182 struct radeon_surf *surf, bool is_stencil,
183 unsigned level, bool compressed,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
186 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
187 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
188 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
190 {
191 struct legacy_surf_level *surf_level;
192 ADDR_E_RETURNCODE ret;
193
194 AddrSurfInfoIn->mipLevel = level;
195 AddrSurfInfoIn->width = u_minify(config->info.width, level);
196 AddrSurfInfoIn->height = u_minify(config->info.height, level);
197
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
200 */
201 if (config->info.levels == 1 &&
202 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
203 AddrSurfInfoIn->bpp &&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
205 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
206
207 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
208 }
209
210 /* addrlib assumes the bytes/pixel is a divisor of 64, which is not
211 * true for r32g32b32 formats. */
212 if (AddrSurfInfoIn->bpp == 96) {
213 assert(config->info.levels == 1);
214 assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
215
216 /* The least common multiple of 64 bytes and 12 bytes/pixel is
217 * 192 bytes, or 16 pixels. */
218 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
219 }
220
221 if (config->is_3d)
222 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
223 else if (config->is_cube)
224 AddrSurfInfoIn->numSlices = 6;
225 else
226 AddrSurfInfoIn->numSlices = config->info.array_size;
227
228 if (level > 0) {
229 /* Set the base level pitch. This is needed for calculation
230 * of non-zero levels. */
231 if (is_stencil)
232 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
233 else
234 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
235
236 /* Convert blocks to pixels for compressed formats. */
237 if (compressed)
238 AddrSurfInfoIn->basePitch *= surf->blk_w;
239 }
240
241 ret = AddrComputeSurfaceInfo(addrlib,
242 AddrSurfInfoIn,
243 AddrSurfInfoOut);
244 if (ret != ADDR_OK) {
245 return ret;
246 }
247
248 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
249 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
250 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
251 surf_level->nblk_x = AddrSurfInfoOut->pitch;
252 surf_level->nblk_y = AddrSurfInfoOut->height;
253
254 switch (AddrSurfInfoOut->tileMode) {
255 case ADDR_TM_LINEAR_ALIGNED:
256 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
257 break;
258 case ADDR_TM_1D_TILED_THIN1:
259 surf_level->mode = RADEON_SURF_MODE_1D;
260 break;
261 case ADDR_TM_2D_TILED_THIN1:
262 surf_level->mode = RADEON_SURF_MODE_2D;
263 break;
264 default:
265 assert(0);
266 }
267
268 if (is_stencil)
269 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
270 else
271 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
272
273 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
274
275 /* Clear DCC fields at the beginning. */
276 surf_level->dcc_offset = 0;
277
278 /* The previous level's flag tells us if we can use DCC for this level. */
279 if (AddrSurfInfoIn->flags.dccCompatible &&
280 (level == 0 || AddrDccOut->subLvlCompressible)) {
281 bool prev_level_clearable = level == 0 ||
282 AddrDccOut->dccRamSizeAligned;
283
284 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
285 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
286 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
287 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
288 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
289
290 ret = AddrComputeDccInfo(addrlib,
291 AddrDccIn,
292 AddrDccOut);
293
294 if (ret == ADDR_OK) {
295 surf_level->dcc_offset = surf->dcc_size;
296 surf->num_dcc_levels = level + 1;
297 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
298 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
299
300 /* If the DCC size of a subresource (1 mip level or 1 slice)
301 * is not aligned, the DCC memory layout is not contiguous for
302 * that subresource, which means we can't use fast clear.
303 *
304 * We only do fast clears for whole mipmap levels. If we did
305 * per-slice fast clears, the same restriction would apply.
306 * (i.e. only compute the slice size and see if it's aligned)
307 *
308 * The last level can be non-contiguous and still be clearable
309 * if it's interleaved with the next level that doesn't exist.
310 */
311 if (AddrDccOut->dccRamSizeAligned ||
312 (prev_level_clearable && level == config->info.levels - 1))
313 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
314 else
315 surf_level->dcc_fast_clear_size = 0;
316
317 /* Compute the DCC slice size because addrlib doesn't
318 * provide this info. As DCC memory is linear (each
319 * slice is the same size) it's easy to compute.
320 */
321 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
322
323 /* For arrays, we have to compute the DCC info again
324 * with one slice size to get a correct fast clear
325 * size.
326 */
327 if (config->info.array_size > 1) {
328 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
329 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
330 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
331 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
332 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
333
334 ret = AddrComputeDccInfo(addrlib,
335 AddrDccIn, AddrDccOut);
336 if (ret == ADDR_OK) {
337 /* If the DCC memory isn't properly
338 * aligned, the data are interleaved
339 * accross slices.
340 */
341 if (AddrDccOut->dccRamSizeAligned)
342 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
343 else
344 surf_level->dcc_slice_fast_clear_size = 0;
345 }
346
347 if (surf->flags & RADEON_SURF_CONTIGUOUS_DCC_LAYERS &&
348 surf->dcc_slice_size != surf_level->dcc_slice_fast_clear_size) {
349 surf->dcc_size = 0;
350 surf->num_dcc_levels = 0;
351 AddrDccOut->subLvlCompressible = false;
352 }
353 } else {
354 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
355 }
356 }
357 }
358
359 /* HTILE. */
360 if (!is_stencil &&
361 AddrSurfInfoIn->flags.depth &&
362 surf_level->mode == RADEON_SURF_MODE_2D &&
363 level == 0 &&
364 !(surf->flags & RADEON_SURF_NO_HTILE)) {
365 AddrHtileIn->flags.tcCompatible = AddrSurfInfoOut->tcCompatible;
366 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
367 AddrHtileIn->height = AddrSurfInfoOut->height;
368 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
369 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
370 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
371 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
372 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
373 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
374
375 ret = AddrComputeHtileInfo(addrlib,
376 AddrHtileIn,
377 AddrHtileOut);
378
379 if (ret == ADDR_OK) {
380 surf->htile_size = AddrHtileOut->htileBytes;
381 surf->htile_slice_size = AddrHtileOut->sliceSize;
382 surf->htile_alignment = AddrHtileOut->baseAlign;
383 }
384 }
385
386 return 0;
387 }
388
389 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
390 const struct radeon_info *info)
391 {
392 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
393
394 if (info->chip_class >= GFX7)
395 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
396 else
397 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
398 }
399
400 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
401 {
402 unsigned index, tileb;
403
404 tileb = 8 * 8 * surf->bpe;
405 tileb = MIN2(surf->u.legacy.tile_split, tileb);
406
407 for (index = 0; tileb > 64; index++)
408 tileb >>= 1;
409
410 assert(index < 16);
411 return index;
412 }
413
414 static bool get_display_flag(const struct ac_surf_config *config,
415 const struct radeon_surf *surf)
416 {
417 unsigned num_channels = config->info.num_channels;
418 unsigned bpe = surf->bpe;
419
420 if (!config->is_3d &&
421 !config->is_cube &&
422 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
423 surf->flags & RADEON_SURF_SCANOUT &&
424 config->info.samples <= 1 &&
425 surf->blk_w <= 2 && surf->blk_h == 1) {
426 /* subsampled */
427 if (surf->blk_w == 2 && surf->blk_h == 1)
428 return true;
429
430 if (/* RGBA8 or RGBA16F */
431 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
432 /* R5G6B5 or R5G5B5A1 */
433 (bpe == 2 && num_channels >= 3) ||
434 /* C8 palette */
435 (bpe == 1 && num_channels == 1))
436 return true;
437 }
438 return false;
439 }
440
441 /**
442 * This must be called after the first level is computed.
443 *
444 * Copy surface-global settings like pipe/bank config from level 0 surface
445 * computation, and compute tile swizzle.
446 */
447 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
448 const struct radeon_info *info,
449 const struct ac_surf_config *config,
450 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
451 struct radeon_surf *surf)
452 {
453 surf->surf_alignment = csio->baseAlign;
454 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
455 gfx6_set_micro_tile_mode(surf, info);
456
457 /* For 2D modes only. */
458 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
459 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
460 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
461 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
462 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
463 surf->u.legacy.num_banks = csio->pTileInfo->banks;
464 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
465 } else {
466 surf->u.legacy.macro_tile_index = 0;
467 }
468
469 /* Compute tile swizzle. */
470 /* TODO: fix tile swizzle with mipmapping for GFX6 */
471 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
472 config->info.surf_index &&
473 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
474 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
475 !get_display_flag(config, surf)) {
476 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
477 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
478
479 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
480 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
481
482 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
483 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
484 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
485 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
486 AddrBaseSwizzleIn.tileMode = csio->tileMode;
487
488 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
489 &AddrBaseSwizzleOut);
490 if (r != ADDR_OK)
491 return r;
492
493 assert(AddrBaseSwizzleOut.tileSwizzle <=
494 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
495 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
496 }
497 return 0;
498 }
499
500 static void ac_compute_cmask(const struct radeon_info *info,
501 const struct ac_surf_config *config,
502 struct radeon_surf *surf)
503 {
504 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
505 unsigned num_pipes = info->num_tile_pipes;
506 unsigned cl_width, cl_height;
507
508 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER || surf->is_linear ||
509 (config->info.samples >= 2 && !surf->fmask_size))
510 return;
511
512 assert(info->chip_class <= GFX8);
513
514 switch (num_pipes) {
515 case 2:
516 cl_width = 32;
517 cl_height = 16;
518 break;
519 case 4:
520 cl_width = 32;
521 cl_height = 32;
522 break;
523 case 8:
524 cl_width = 64;
525 cl_height = 32;
526 break;
527 case 16: /* Hawaii */
528 cl_width = 64;
529 cl_height = 64;
530 break;
531 default:
532 assert(0);
533 return;
534 }
535
536 unsigned base_align = num_pipes * pipe_interleave_bytes;
537
538 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
539 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
540 unsigned slice_elements = (width * height) / (8*8);
541
542 /* Each element of CMASK is a nibble. */
543 unsigned slice_bytes = slice_elements / 2;
544
545 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
546 if (surf->u.legacy.cmask_slice_tile_max)
547 surf->u.legacy.cmask_slice_tile_max -= 1;
548
549 unsigned num_layers;
550 if (config->is_3d)
551 num_layers = config->info.depth;
552 else if (config->is_cube)
553 num_layers = 6;
554 else
555 num_layers = config->info.array_size;
556
557 surf->cmask_alignment = MAX2(256, base_align);
558 surf->cmask_slice_size = align(slice_bytes, base_align);
559 surf->cmask_size = surf->cmask_slice_size * num_layers;
560 }
561
562 /**
563 * Fill in the tiling information in \p surf based on the given surface config.
564 *
565 * The following fields of \p surf must be initialized by the caller:
566 * blk_w, blk_h, bpe, flags.
567 */
568 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
569 const struct radeon_info *info,
570 const struct ac_surf_config *config,
571 enum radeon_surf_mode mode,
572 struct radeon_surf *surf)
573 {
574 unsigned level;
575 bool compressed;
576 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
577 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
578 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
579 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
580 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
581 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
582 ADDR_TILEINFO AddrTileInfoIn = {0};
583 ADDR_TILEINFO AddrTileInfoOut = {0};
584 int r;
585
586 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
587 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
588 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
589 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
590 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
591 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
592 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
593
594 compressed = surf->blk_w == 4 && surf->blk_h == 4;
595
596 /* MSAA requires 2D tiling. */
597 if (config->info.samples > 1)
598 mode = RADEON_SURF_MODE_2D;
599
600 /* DB doesn't support linear layouts. */
601 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
602 mode < RADEON_SURF_MODE_1D)
603 mode = RADEON_SURF_MODE_1D;
604
605 /* Set the requested tiling mode. */
606 switch (mode) {
607 case RADEON_SURF_MODE_LINEAR_ALIGNED:
608 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
609 break;
610 case RADEON_SURF_MODE_1D:
611 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
612 break;
613 case RADEON_SURF_MODE_2D:
614 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
615 break;
616 default:
617 assert(0);
618 }
619
620 /* The format must be set correctly for the allocation of compressed
621 * textures to work. In other cases, setting the bpp is sufficient.
622 */
623 if (compressed) {
624 switch (surf->bpe) {
625 case 8:
626 AddrSurfInfoIn.format = ADDR_FMT_BC1;
627 break;
628 case 16:
629 AddrSurfInfoIn.format = ADDR_FMT_BC3;
630 break;
631 default:
632 assert(0);
633 }
634 }
635 else {
636 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
637 }
638
639 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
640 MAX2(1, config->info.samples);
641 AddrSurfInfoIn.tileIndex = -1;
642
643 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
644 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
645 MAX2(1, config->info.storage_samples);
646 }
647
648 /* Set the micro tile type. */
649 if (surf->flags & RADEON_SURF_SCANOUT)
650 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
651 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
652 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
653 else
654 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
655
656 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
657 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
658 AddrSurfInfoIn.flags.cube = config->is_cube;
659 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
660 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
661 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
662
663 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
664 * requested, because TC-compatible HTILE requires 2D tiling.
665 */
666 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
667 !AddrSurfInfoIn.flags.fmask &&
668 config->info.samples <= 1 &&
669 !(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE);
670
671 /* DCC notes:
672 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
673 * with samples >= 4.
674 * - Mipmapped array textures have low performance (discovered by a closed
675 * driver team).
676 */
677 AddrSurfInfoIn.flags.dccCompatible =
678 info->chip_class >= GFX8 &&
679 info->has_graphics && /* disable DCC on compute-only chips */
680 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
681 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
682 !compressed &&
683 ((config->info.array_size == 1 && config->info.depth == 1) ||
684 config->info.levels == 1);
685
686 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
687 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
688
689 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
690 * for Z and stencil. This can cause a number of problems which we work
691 * around here:
692 *
693 * - a depth part that is incompatible with mipmapped texturing
694 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
695 * incorrect tiling applied to the stencil part, stencil buffer
696 * memory accesses that go out of bounds) even without mipmapping
697 *
698 * Some piglit tests that are prone to different types of related
699 * failures:
700 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
701 * ./bin/framebuffer-blit-levels {draw,read} stencil
702 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
703 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
704 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
705 */
706 int stencil_tile_idx = -1;
707
708 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
709 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
710 /* Compute stencilTileIdx that is compatible with the (depth)
711 * tileIdx. This degrades the depth surface if necessary to
712 * ensure that a matching stencilTileIdx exists. */
713 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
714
715 /* Keep the depth mip-tail compatible with texturing. */
716 AddrSurfInfoIn.flags.noStencil = 1;
717 }
718
719 /* Set preferred macrotile parameters. This is usually required
720 * for shared resources. This is for 2D tiling only. */
721 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
722 surf->u.legacy.bankw && surf->u.legacy.bankh &&
723 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
724 /* If any of these parameters are incorrect, the calculation
725 * will fail. */
726 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
727 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
728 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
729 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
730 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
731 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
732 AddrSurfInfoIn.flags.opt4Space = 0;
733 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
734
735 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
736 * the tile index, because we are expected to know it if
737 * we know the other parameters.
738 *
739 * This is something that can easily be fixed in Addrlib.
740 * For now, just figure it out here.
741 * Note that only 2D_TILE_THIN1 is handled here.
742 */
743 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
744 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
745
746 if (info->chip_class == GFX6) {
747 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
748 if (surf->bpe == 2)
749 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
750 else
751 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
752 } else {
753 if (surf->bpe == 1)
754 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
755 else if (surf->bpe == 2)
756 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
757 else if (surf->bpe == 4)
758 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
759 else
760 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
761 }
762 } else {
763 /* GFX7 - GFX8 */
764 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
765 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
766 else
767 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
768
769 /* Addrlib doesn't set this if tileIndex is forced like above. */
770 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
771 }
772 }
773
774 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
775 surf->num_dcc_levels = 0;
776 surf->surf_size = 0;
777 surf->dcc_size = 0;
778 surf->dcc_alignment = 1;
779 surf->htile_size = 0;
780 surf->htile_slice_size = 0;
781 surf->htile_alignment = 1;
782
783 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
784 !(surf->flags & RADEON_SURF_ZBUFFER);
785
786 /* Calculate texture layout information. */
787 if (!only_stencil) {
788 for (level = 0; level < config->info.levels; level++) {
789 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
790 &AddrSurfInfoIn, &AddrSurfInfoOut,
791 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
792 if (r)
793 return r;
794
795 if (level > 0)
796 continue;
797
798 if (!AddrSurfInfoOut.tcCompatible) {
799 AddrSurfInfoIn.flags.tcCompatible = 0;
800 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
801 }
802
803 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
804 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
805 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
806 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
807
808 assert(stencil_tile_idx >= 0);
809 }
810
811 r = gfx6_surface_settings(addrlib, info, config,
812 &AddrSurfInfoOut, surf);
813 if (r)
814 return r;
815 }
816 }
817
818 /* Calculate texture layout information for stencil. */
819 if (surf->flags & RADEON_SURF_SBUFFER) {
820 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
821 AddrSurfInfoIn.bpp = 8;
822 AddrSurfInfoIn.flags.depth = 0;
823 AddrSurfInfoIn.flags.stencil = 1;
824 AddrSurfInfoIn.flags.tcCompatible = 0;
825 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
826 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
827
828 for (level = 0; level < config->info.levels; level++) {
829 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
830 &AddrSurfInfoIn, &AddrSurfInfoOut,
831 &AddrDccIn, &AddrDccOut,
832 NULL, NULL);
833 if (r)
834 return r;
835
836 /* DB uses the depth pitch for both stencil and depth. */
837 if (!only_stencil) {
838 if (surf->u.legacy.stencil_level[level].nblk_x !=
839 surf->u.legacy.level[level].nblk_x)
840 surf->u.legacy.stencil_adjusted = true;
841 } else {
842 surf->u.legacy.level[level].nblk_x =
843 surf->u.legacy.stencil_level[level].nblk_x;
844 }
845
846 if (level == 0) {
847 if (only_stencil) {
848 r = gfx6_surface_settings(addrlib, info, config,
849 &AddrSurfInfoOut, surf);
850 if (r)
851 return r;
852 }
853
854 /* For 2D modes only. */
855 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
856 surf->u.legacy.stencil_tile_split =
857 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
858 }
859 }
860 }
861 }
862
863 /* Compute FMASK. */
864 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
865 info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
866 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
867 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
868 ADDR_TILEINFO fmask_tile_info = {};
869
870 fin.size = sizeof(fin);
871 fout.size = sizeof(fout);
872
873 fin.tileMode = AddrSurfInfoOut.tileMode;
874 fin.pitch = AddrSurfInfoOut.pitch;
875 fin.height = config->info.height;
876 fin.numSlices = AddrSurfInfoIn.numSlices;
877 fin.numSamples = AddrSurfInfoIn.numSamples;
878 fin.numFrags = AddrSurfInfoIn.numFrags;
879 fin.tileIndex = -1;
880 fout.pTileInfo = &fmask_tile_info;
881
882 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
883 if (r)
884 return r;
885
886 surf->fmask_size = fout.fmaskBytes;
887 surf->fmask_alignment = fout.baseAlign;
888 surf->fmask_tile_swizzle = 0;
889
890 surf->u.legacy.fmask.slice_tile_max =
891 (fout.pitch * fout.height) / 64;
892 if (surf->u.legacy.fmask.slice_tile_max)
893 surf->u.legacy.fmask.slice_tile_max -= 1;
894
895 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
896 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
897 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
898 surf->u.legacy.fmask.slice_size = fout.sliceSize;
899
900 /* Compute tile swizzle for FMASK. */
901 if (config->info.fmask_surf_index &&
902 !(surf->flags & RADEON_SURF_SHAREABLE)) {
903 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
904 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
905
906 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
907 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
908
909 /* This counter starts from 1 instead of 0. */
910 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
911 xin.tileIndex = fout.tileIndex;
912 xin.macroModeIndex = fout.macroModeIndex;
913 xin.pTileInfo = fout.pTileInfo;
914 xin.tileMode = fin.tileMode;
915
916 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
917 if (r != ADDR_OK)
918 return r;
919
920 assert(xout.tileSwizzle <=
921 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
922 surf->fmask_tile_swizzle = xout.tileSwizzle;
923 }
924 }
925
926 /* Recalculate the whole DCC miptree size including disabled levels.
927 * This is what addrlib does, but calling addrlib would be a lot more
928 * complicated.
929 */
930 if (surf->dcc_size && config->info.levels > 1) {
931 /* The smallest miplevels that are never compressed by DCC
932 * still read the DCC buffer via TC if the base level uses DCC,
933 * and for some reason the DCC buffer needs to be larger if
934 * the miptree uses non-zero tile_swizzle. Otherwise there are
935 * VM faults.
936 *
937 * "dcc_alignment * 4" was determined by trial and error.
938 */
939 surf->dcc_size = align64(surf->surf_size >> 8,
940 surf->dcc_alignment * 4);
941 }
942
943 /* Make sure HTILE covers the whole miptree, because the shader reads
944 * TC-compatible HTILE even for levels where it's disabled by DB.
945 */
946 if (surf->htile_size && config->info.levels > 1 &&
947 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
948 /* MSAA can't occur with levels > 1, so ignore the sample count. */
949 const unsigned total_pixels = surf->surf_size / surf->bpe;
950 const unsigned htile_block_size = 8 * 8;
951 const unsigned htile_element_size = 4;
952
953 surf->htile_size = (total_pixels / htile_block_size) *
954 htile_element_size;
955 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
956 } else if (!surf->htile_size) {
957 /* Unset this if HTILE is not present. */
958 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
959 }
960
961 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
962 surf->is_displayable = surf->is_linear ||
963 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
964 surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
965
966 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
967 * used at the same time. This case is not currently expected to occur
968 * because we don't use rotated. Enforce this restriction on all chips
969 * to facilitate testing.
970 */
971 if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) {
972 assert(!"rotate micro tile mode is unsupported");
973 return ADDR_ERROR;
974 }
975
976 ac_compute_cmask(info, config, surf);
977 return 0;
978 }
979
980 /* This is only called when expecting a tiled layout. */
981 static int
982 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
983 struct radeon_surf *surf,
984 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
985 bool is_fmask, AddrSwizzleMode *swizzle_mode)
986 {
987 ADDR_E_RETURNCODE ret;
988 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
989 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
990
991 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
992 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
993
994 sin.flags = in->flags;
995 sin.resourceType = in->resourceType;
996 sin.format = in->format;
997 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
998 /* TODO: We could allow some of these: */
999 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
1000 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
1001 sin.bpp = in->bpp;
1002 sin.width = in->width;
1003 sin.height = in->height;
1004 sin.numSlices = in->numSlices;
1005 sin.numMipLevels = in->numMipLevels;
1006 sin.numSamples = in->numSamples;
1007 sin.numFrags = in->numFrags;
1008
1009 if (is_fmask) {
1010 sin.flags.display = 0;
1011 sin.flags.color = 0;
1012 sin.flags.fmask = 1;
1013 }
1014
1015 if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
1016 sin.forbiddenBlock.linear = 1;
1017
1018 if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1019 sin.preferredSwSet.sw_D = 1;
1020 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_STANDARD)
1021 sin.preferredSwSet.sw_S = 1;
1022 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
1023 sin.preferredSwSet.sw_Z = 1;
1024 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER)
1025 sin.preferredSwSet.sw_R = 1;
1026 }
1027
1028 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1029 if (ret != ADDR_OK)
1030 return ret;
1031
1032 *swizzle_mode = sout.swizzleMode;
1033 return 0;
1034 }
1035
1036 static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_mode)
1037 {
1038 if (info->chip_class >= GFX10)
1039 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1040
1041 return sw_mode != ADDR_SW_LINEAR;
1042 }
1043
1044 ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info,
1045 const struct radeon_surf *surf)
1046 {
1047 if (info->chip_class <= GFX9) {
1048 /* Only independent 64B blocks are supported. */
1049 return surf->u.gfx9.dcc.independent_64B_blocks &&
1050 !surf->u.gfx9.dcc.independent_128B_blocks &&
1051 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B;
1052 }
1053
1054 if (info->family == CHIP_NAVI10) {
1055 /* Only independent 128B blocks are supported. */
1056 return !surf->u.gfx9.dcc.independent_64B_blocks &&
1057 surf->u.gfx9.dcc.independent_128B_blocks &&
1058 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1059 }
1060
1061 if (info->family == CHIP_NAVI12 ||
1062 info->family == CHIP_NAVI14) {
1063 /* Either 64B or 128B can be used, but not both.
1064 * If 64B is used, DCC image stores are unsupported.
1065 */
1066 return surf->u.gfx9.dcc.independent_64B_blocks !=
1067 surf->u.gfx9.dcc.independent_128B_blocks &&
1068 (!surf->u.gfx9.dcc.independent_64B_blocks ||
1069 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) &&
1070 (!surf->u.gfx9.dcc.independent_128B_blocks ||
1071 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B);
1072 }
1073
1074 /* 128B is recommended, but 64B can be set too if needed for 4K by DCN.
1075 * Since there is no reason to ever disable 128B, require it.
1076 * DCC image stores are always supported.
1077 */
1078 return surf->u.gfx9.dcc.independent_128B_blocks &&
1079 surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1080 }
1081
1082 static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
1083 const struct ac_surf_config *config,
1084 const struct radeon_surf *surf,
1085 bool rb_aligned, bool pipe_aligned)
1086 {
1087 if (!info->use_display_dcc_unaligned &&
1088 !info->use_display_dcc_with_retile_blit)
1089 return false;
1090
1091 /* 16bpp and 64bpp are more complicated, so they are disallowed for now. */
1092 if (surf->bpe != 4)
1093 return false;
1094
1095 /* Handle unaligned DCC. */
1096 if (info->use_display_dcc_unaligned &&
1097 (rb_aligned || pipe_aligned))
1098 return false;
1099
1100 switch (info->chip_class) {
1101 case GFX9:
1102 /* There are more constraints, but we always set
1103 * INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B,
1104 * which always works.
1105 */
1106 assert(surf->u.gfx9.dcc.independent_64B_blocks &&
1107 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
1108 return true;
1109 case GFX10:
1110 case GFX10_3:
1111 /* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */
1112 if (info->chip_class == GFX10 &&
1113 surf->u.gfx9.dcc.independent_128B_blocks)
1114 return false;
1115
1116 /* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1. */
1117 return ((config->info.width <= 2560 &&
1118 config->info.height <= 2560) ||
1119 (surf->u.gfx9.dcc.independent_64B_blocks &&
1120 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
1121 default:
1122 unreachable("unhandled chip");
1123 return false;
1124 }
1125 }
1126
1127 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1128 const struct radeon_info *info,
1129 const struct ac_surf_config *config,
1130 struct radeon_surf *surf, bool compressed,
1131 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1132 {
1133 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1134 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1135 ADDR_E_RETURNCODE ret;
1136
1137 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1138 out.pMipInfo = mip_info;
1139
1140 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1141 if (ret != ADDR_OK)
1142 return ret;
1143
1144 if (in->flags.stencil) {
1145 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1146 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1147 out.mipChainPitch - 1;
1148 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1149 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1150 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1151 return 0;
1152 }
1153
1154 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1155 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1156 out.mipChainPitch - 1;
1157
1158 /* CMASK fast clear uses these even if FMASK isn't allocated.
1159 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1160 */
1161 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1162 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1163
1164 surf->u.gfx9.surf_slice_size = out.sliceSize;
1165 surf->u.gfx9.surf_pitch = out.pitch;
1166 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch) {
1167 /* Adjust surf_pitch to be in elements units,
1168 * not in pixels */
1169 surf->u.gfx9.surf_pitch /= surf->blk_w;
1170 }
1171 surf->u.gfx9.surf_height = out.height;
1172 surf->surf_size = out.surfSize;
1173 surf->surf_alignment = out.baseAlign;
1174
1175 if (in->swizzleMode == ADDR_SW_LINEAR) {
1176 for (unsigned i = 0; i < in->numMipLevels; i++) {
1177 surf->u.gfx9.offset[i] = mip_info[i].offset;
1178 surf->u.gfx9.pitch[i] = mip_info[i].pitch;
1179 }
1180 }
1181
1182 if (in->flags.depth) {
1183 assert(in->swizzleMode != ADDR_SW_LINEAR);
1184
1185 if (surf->flags & RADEON_SURF_NO_HTILE)
1186 return 0;
1187
1188 /* HTILE */
1189 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1190 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1191
1192 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1193 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1194
1195 assert(in->flags.metaPipeUnaligned == 0);
1196 assert(in->flags.metaRbUnaligned == 0);
1197
1198 hin.hTileFlags.pipeAligned = 1;
1199 hin.hTileFlags.rbAligned = 1;
1200 hin.depthFlags = in->flags;
1201 hin.swizzleMode = in->swizzleMode;
1202 hin.unalignedWidth = in->width;
1203 hin.unalignedHeight = in->height;
1204 hin.numSlices = in->numSlices;
1205 hin.numMipLevels = in->numMipLevels;
1206 hin.firstMipIdInTail = out.firstMipIdInTail;
1207
1208 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1209 if (ret != ADDR_OK)
1210 return ret;
1211
1212 surf->htile_size = hout.htileBytes;
1213 surf->htile_slice_size = hout.sliceSize;
1214 surf->htile_alignment = hout.baseAlign;
1215 return 0;
1216 }
1217
1218 {
1219 /* Compute tile swizzle for the color surface.
1220 * All *_X and *_T modes can use the swizzle.
1221 */
1222 if (config->info.surf_index &&
1223 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1224 !out.mipChainInTail &&
1225 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1226 !in->flags.display) {
1227 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1228 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1229
1230 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1231 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1232
1233 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1234 xin.flags = in->flags;
1235 xin.swizzleMode = in->swizzleMode;
1236 xin.resourceType = in->resourceType;
1237 xin.format = in->format;
1238 xin.numSamples = in->numSamples;
1239 xin.numFrags = in->numFrags;
1240
1241 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1242 if (ret != ADDR_OK)
1243 return ret;
1244
1245 assert(xout.pipeBankXor <=
1246 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1247 surf->tile_swizzle = xout.pipeBankXor;
1248 }
1249
1250 /* DCC */
1251 if (info->has_graphics &&
1252 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1253 !compressed &&
1254 is_dcc_supported_by_CB(info, in->swizzleMode) &&
1255 (!in->flags.display ||
1256 is_dcc_supported_by_DCN(info, config, surf,
1257 !in->flags.metaRbUnaligned,
1258 !in->flags.metaPipeUnaligned))) {
1259 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1260 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1261 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1262
1263 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1264 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1265 dout.pMipInfo = meta_mip_info;
1266
1267 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1268 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1269 din.colorFlags = in->flags;
1270 din.resourceType = in->resourceType;
1271 din.swizzleMode = in->swizzleMode;
1272 din.bpp = in->bpp;
1273 din.unalignedWidth = in->width;
1274 din.unalignedHeight = in->height;
1275 din.numSlices = in->numSlices;
1276 din.numFrags = in->numFrags;
1277 din.numMipLevels = in->numMipLevels;
1278 din.dataSurfaceSize = out.surfSize;
1279 din.firstMipIdInTail = out.firstMipIdInTail;
1280
1281 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1282 if (ret != ADDR_OK)
1283 return ret;
1284
1285 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1286 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1287 surf->u.gfx9.dcc_block_width = dout.compressBlkWidth;
1288 surf->u.gfx9.dcc_block_height = dout.compressBlkHeight;
1289 surf->u.gfx9.dcc_block_depth = dout.compressBlkDepth;
1290 surf->dcc_size = dout.dccRamSize;
1291 surf->dcc_alignment = dout.dccRamBaseAlign;
1292 surf->num_dcc_levels = in->numMipLevels;
1293
1294 /* Disable DCC for levels that are in the mip tail.
1295 *
1296 * There are two issues that this is intended to
1297 * address:
1298 *
1299 * 1. Multiple mip levels may share a cache line. This
1300 * can lead to corruption when switching between
1301 * rendering to different mip levels because the
1302 * RBs don't maintain coherency.
1303 *
1304 * 2. Texturing with metadata after rendering sometimes
1305 * fails with corruption, probably for a similar
1306 * reason.
1307 *
1308 * Working around these issues for all levels in the
1309 * mip tail may be overly conservative, but it's what
1310 * Vulkan does.
1311 *
1312 * Alternative solutions that also work but are worse:
1313 * - Disable DCC entirely.
1314 * - Flush TC L2 after rendering.
1315 */
1316 for (unsigned i = 0; i < in->numMipLevels; i++) {
1317 if (meta_mip_info[i].inMiptail) {
1318 surf->num_dcc_levels = i;
1319 break;
1320 }
1321 }
1322
1323 if (!surf->num_dcc_levels)
1324 surf->dcc_size = 0;
1325
1326 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1327 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1328 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1329
1330 /* Compute displayable DCC. */
1331 if (in->flags.display &&
1332 surf->num_dcc_levels &&
1333 info->use_display_dcc_with_retile_blit) {
1334 /* Compute displayable DCC info. */
1335 din.dccKeyFlags.pipeAligned = 0;
1336 din.dccKeyFlags.rbAligned = 0;
1337
1338 assert(din.numSlices == 1);
1339 assert(din.numMipLevels == 1);
1340 assert(din.numFrags == 1);
1341 assert(surf->tile_swizzle == 0);
1342 assert(surf->u.gfx9.dcc.pipe_aligned ||
1343 surf->u.gfx9.dcc.rb_aligned);
1344
1345 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1346 if (ret != ADDR_OK)
1347 return ret;
1348
1349 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1350 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1351 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1352 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1353
1354 /* Compute address mapping from non-displayable to displayable DCC. */
1355 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1356 addrin.size = sizeof(addrin);
1357 addrin.colorFlags.color = 1;
1358 addrin.swizzleMode = din.swizzleMode;
1359 addrin.resourceType = din.resourceType;
1360 addrin.bpp = din.bpp;
1361 addrin.unalignedWidth = din.unalignedWidth;
1362 addrin.unalignedHeight = din.unalignedHeight;
1363 addrin.numSlices = 1;
1364 addrin.numMipLevels = 1;
1365 addrin.numFrags = 1;
1366
1367 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1368 addrout.size = sizeof(addrout);
1369
1370 surf->u.gfx9.dcc_retile_num_elements =
1371 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1372 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1373 /* Align the size to 4 (for the compute shader). */
1374 surf->u.gfx9.dcc_retile_num_elements =
1375 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1376
1377 surf->u.gfx9.dcc_retile_map =
1378 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1379 if (!surf->u.gfx9.dcc_retile_map)
1380 return ADDR_OUTOFMEMORY;
1381
1382 unsigned index = 0;
1383 surf->u.gfx9.dcc_retile_use_uint16 = true;
1384
1385 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1386 addrin.y = y;
1387
1388 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1389 addrin.x = x;
1390
1391 /* Compute src DCC address */
1392 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1393 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1394 addrout.addr = 0;
1395
1396 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1397 if (ret != ADDR_OK)
1398 return ret;
1399
1400 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1401 if (addrout.addr > UINT16_MAX)
1402 surf->u.gfx9.dcc_retile_use_uint16 = false;
1403
1404 /* Compute dst DCC address */
1405 addrin.dccKeyFlags.pipeAligned = 0;
1406 addrin.dccKeyFlags.rbAligned = 0;
1407 addrout.addr = 0;
1408
1409 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1410 if (ret != ADDR_OK)
1411 return ret;
1412
1413 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1414 if (addrout.addr > UINT16_MAX)
1415 surf->u.gfx9.dcc_retile_use_uint16 = false;
1416
1417 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1418 index++;
1419 }
1420 }
1421 /* Fill the remaining pairs with the last one (for the compute shader). */
1422 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1423 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1424 }
1425 }
1426
1427 /* FMASK */
1428 if (in->numSamples > 1 && info->has_graphics &&
1429 !(surf->flags & RADEON_SURF_NO_FMASK)) {
1430 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1431 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1432
1433 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1434 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1435
1436 ret = gfx9_get_preferred_swizzle_mode(addrlib, surf, in,
1437 true, &fin.swizzleMode);
1438 if (ret != ADDR_OK)
1439 return ret;
1440
1441 fin.unalignedWidth = in->width;
1442 fin.unalignedHeight = in->height;
1443 fin.numSlices = in->numSlices;
1444 fin.numSamples = in->numSamples;
1445 fin.numFrags = in->numFrags;
1446
1447 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1448 if (ret != ADDR_OK)
1449 return ret;
1450
1451 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1452 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1453 surf->fmask_size = fout.fmaskBytes;
1454 surf->fmask_alignment = fout.baseAlign;
1455
1456 /* Compute tile swizzle for the FMASK surface. */
1457 if (config->info.fmask_surf_index &&
1458 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1459 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1460 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1461 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1462
1463 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1464 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1465
1466 /* This counter starts from 1 instead of 0. */
1467 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1468 xin.flags = in->flags;
1469 xin.swizzleMode = fin.swizzleMode;
1470 xin.resourceType = in->resourceType;
1471 xin.format = in->format;
1472 xin.numSamples = in->numSamples;
1473 xin.numFrags = in->numFrags;
1474
1475 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1476 if (ret != ADDR_OK)
1477 return ret;
1478
1479 assert(xout.pipeBankXor <=
1480 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1481 surf->fmask_tile_swizzle = xout.pipeBankXor;
1482 }
1483 }
1484
1485 /* CMASK -- on GFX10 only for FMASK */
1486 if (in->swizzleMode != ADDR_SW_LINEAR &&
1487 in->resourceType == ADDR_RSRC_TEX_2D &&
1488 ((info->chip_class <= GFX9 &&
1489 in->numSamples == 1 &&
1490 in->flags.metaPipeUnaligned == 0 &&
1491 in->flags.metaRbUnaligned == 0) ||
1492 (surf->fmask_size && in->numSamples >= 2))) {
1493 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1494 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1495
1496 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1497 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1498
1499 assert(in->flags.metaPipeUnaligned == 0);
1500 assert(in->flags.metaRbUnaligned == 0);
1501
1502 cin.cMaskFlags.pipeAligned = 1;
1503 cin.cMaskFlags.rbAligned = 1;
1504 cin.colorFlags = in->flags;
1505 cin.resourceType = in->resourceType;
1506 cin.unalignedWidth = in->width;
1507 cin.unalignedHeight = in->height;
1508 cin.numSlices = in->numSlices;
1509
1510 if (in->numSamples > 1)
1511 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1512 else
1513 cin.swizzleMode = in->swizzleMode;
1514
1515 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1516 if (ret != ADDR_OK)
1517 return ret;
1518
1519 surf->cmask_size = cout.cmaskBytes;
1520 surf->cmask_alignment = cout.baseAlign;
1521 }
1522 }
1523
1524 return 0;
1525 }
1526
1527 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1528 const struct radeon_info *info,
1529 const struct ac_surf_config *config,
1530 enum radeon_surf_mode mode,
1531 struct radeon_surf *surf)
1532 {
1533 bool compressed;
1534 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1535 int r;
1536
1537 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1538
1539 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1540
1541 /* The format must be set correctly for the allocation of compressed
1542 * textures to work. In other cases, setting the bpp is sufficient. */
1543 if (compressed) {
1544 switch (surf->bpe) {
1545 case 8:
1546 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1547 break;
1548 case 16:
1549 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1550 break;
1551 default:
1552 assert(0);
1553 }
1554 } else {
1555 switch (surf->bpe) {
1556 case 1:
1557 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1558 AddrSurfInfoIn.format = ADDR_FMT_8;
1559 break;
1560 case 2:
1561 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1562 !(surf->flags & RADEON_SURF_SBUFFER));
1563 AddrSurfInfoIn.format = ADDR_FMT_16;
1564 break;
1565 case 4:
1566 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1567 !(surf->flags & RADEON_SURF_SBUFFER));
1568 AddrSurfInfoIn.format = ADDR_FMT_32;
1569 break;
1570 case 8:
1571 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1572 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1573 break;
1574 case 12:
1575 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1576 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1577 break;
1578 case 16:
1579 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1580 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1581 break;
1582 default:
1583 assert(0);
1584 }
1585 AddrSurfInfoIn.bpp = surf->bpe * 8;
1586 }
1587
1588 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1589 AddrSurfInfoIn.flags.color = is_color_surface &&
1590 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1591 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1592 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1593 /* flags.texture currently refers to TC-compatible HTILE */
1594 AddrSurfInfoIn.flags.texture = is_color_surface ||
1595 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1596 AddrSurfInfoIn.flags.opt4space = 1;
1597
1598 AddrSurfInfoIn.numMipLevels = config->info.levels;
1599 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1600 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1601
1602 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1603 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1604
1605 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1606 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1607 * must sample 1D textures as 2D. */
1608 if (config->is_3d)
1609 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1610 else if (info->chip_class != GFX9 && config->is_1d)
1611 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
1612 else
1613 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1614
1615 AddrSurfInfoIn.width = config->info.width;
1616 AddrSurfInfoIn.height = config->info.height;
1617
1618 if (config->is_3d)
1619 AddrSurfInfoIn.numSlices = config->info.depth;
1620 else if (config->is_cube)
1621 AddrSurfInfoIn.numSlices = 6;
1622 else
1623 AddrSurfInfoIn.numSlices = config->info.array_size;
1624
1625 /* This is propagated to DCC. It must be 0 for HTILE and CMASK. */
1626 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1627 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1628
1629 /* Optimal values for the L2 cache. */
1630 if (info->chip_class == GFX9) {
1631 surf->u.gfx9.dcc.independent_64B_blocks = 1;
1632 surf->u.gfx9.dcc.independent_128B_blocks = 0;
1633 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
1634 } else if (info->chip_class >= GFX10) {
1635 surf->u.gfx9.dcc.independent_64B_blocks = 0;
1636 surf->u.gfx9.dcc.independent_128B_blocks = 1;
1637 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
1638 }
1639
1640 if (AddrSurfInfoIn.flags.display) {
1641 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1642 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1643 *
1644 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1645 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1646 * after rendering, so PIPE_ALIGNED=1 is recommended.
1647 */
1648 if (info->use_display_dcc_unaligned) {
1649 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1650 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1651 }
1652
1653 /* Adjust DCC settings to meet DCN requirements. */
1654 if (info->use_display_dcc_unaligned ||
1655 info->use_display_dcc_with_retile_blit) {
1656 /* Only Navi12/14 support independent 64B blocks in L2,
1657 * but without DCC image stores.
1658 */
1659 if (info->family == CHIP_NAVI12 ||
1660 info->family == CHIP_NAVI14) {
1661 surf->u.gfx9.dcc.independent_64B_blocks = 1;
1662 surf->u.gfx9.dcc.independent_128B_blocks = 0;
1663 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
1664 }
1665
1666 if (info->chip_class >= GFX10_3) {
1667 surf->u.gfx9.dcc.independent_64B_blocks = 1;
1668 surf->u.gfx9.dcc.independent_128B_blocks = 1;
1669 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
1670 }
1671 }
1672 }
1673
1674 switch (mode) {
1675 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1676 assert(config->info.samples <= 1);
1677 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1678 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1679 break;
1680
1681 case RADEON_SURF_MODE_1D:
1682 case RADEON_SURF_MODE_2D:
1683 if (surf->flags & RADEON_SURF_IMPORTED ||
1684 (info->chip_class >= GFX10 &&
1685 surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) {
1686 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1687 break;
1688 }
1689
1690 r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
1691 false, &AddrSurfInfoIn.swizzleMode);
1692 if (r)
1693 return r;
1694 break;
1695
1696 default:
1697 assert(0);
1698 }
1699
1700 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1701 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1702
1703 surf->num_dcc_levels = 0;
1704 surf->surf_size = 0;
1705 surf->fmask_size = 0;
1706 surf->dcc_size = 0;
1707 surf->htile_size = 0;
1708 surf->htile_slice_size = 0;
1709 surf->u.gfx9.surf_offset = 0;
1710 surf->u.gfx9.stencil_offset = 0;
1711 surf->cmask_size = 0;
1712 surf->u.gfx9.dcc_retile_use_uint16 = false;
1713 surf->u.gfx9.dcc_retile_num_elements = 0;
1714 surf->u.gfx9.dcc_retile_map = NULL;
1715
1716 /* Calculate texture layout information. */
1717 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1718 &AddrSurfInfoIn);
1719 if (r)
1720 goto error;
1721
1722 /* Calculate texture layout information for stencil. */
1723 if (surf->flags & RADEON_SURF_SBUFFER) {
1724 AddrSurfInfoIn.flags.stencil = 1;
1725 AddrSurfInfoIn.bpp = 8;
1726 AddrSurfInfoIn.format = ADDR_FMT_8;
1727
1728 if (!AddrSurfInfoIn.flags.depth) {
1729 r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
1730 false, &AddrSurfInfoIn.swizzleMode);
1731 if (r)
1732 goto error;
1733 } else
1734 AddrSurfInfoIn.flags.depth = 0;
1735
1736 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1737 &AddrSurfInfoIn);
1738 if (r)
1739 goto error;
1740 }
1741
1742 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1743
1744 /* Query whether the surface is displayable. */
1745 /* This is only useful for surfaces that are allocated without SCANOUT. */
1746 bool displayable = false;
1747 if (!config->is_3d && !config->is_cube) {
1748 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1749 surf->bpe * 8, &displayable);
1750 if (r)
1751 goto error;
1752
1753 /* Display needs unaligned DCC. */
1754 if (surf->num_dcc_levels &&
1755 !is_dcc_supported_by_DCN(info, config, surf,
1756 surf->u.gfx9.dcc.rb_aligned,
1757 surf->u.gfx9.dcc.pipe_aligned))
1758 displayable = false;
1759 }
1760 surf->is_displayable = displayable;
1761
1762 /* Validate that we allocated a displayable surface if requested. */
1763 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable);
1764
1765 /* Validate that DCC is set up correctly. */
1766 if (surf->num_dcc_levels) {
1767 assert(is_dcc_supported_by_L2(info, surf));
1768 if (AddrSurfInfoIn.flags.color)
1769 assert(is_dcc_supported_by_CB(info, surf->u.gfx9.surf.swizzle_mode));
1770 if (AddrSurfInfoIn.flags.display) {
1771 assert(is_dcc_supported_by_DCN(info, config, surf,
1772 surf->u.gfx9.dcc.rb_aligned,
1773 surf->u.gfx9.dcc.pipe_aligned));
1774 }
1775 }
1776
1777 if (info->has_graphics &&
1778 !compressed &&
1779 !config->is_3d &&
1780 config->info.levels == 1 &&
1781 AddrSurfInfoIn.flags.color &&
1782 !surf->is_linear &&
1783 surf->surf_alignment >= 64 * 1024 && /* 64KB tiling */
1784 !(surf->flags & (RADEON_SURF_DISABLE_DCC |
1785 RADEON_SURF_FORCE_SWIZZLE_MODE |
1786 RADEON_SURF_FORCE_MICRO_TILE_MODE))) {
1787 /* Validate that DCC is enabled if DCN can do it. */
1788 if ((info->use_display_dcc_unaligned ||
1789 info->use_display_dcc_with_retile_blit) &&
1790 AddrSurfInfoIn.flags.display &&
1791 surf->bpe == 4) {
1792 assert(surf->num_dcc_levels);
1793 }
1794
1795 /* Validate that non-scanout DCC is always enabled. */
1796 if (!AddrSurfInfoIn.flags.display)
1797 assert(surf->num_dcc_levels);
1798 }
1799
1800 if (!surf->htile_size) {
1801 /* Unset this if HTILE is not present. */
1802 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
1803 }
1804
1805 switch (surf->u.gfx9.surf.swizzle_mode) {
1806 /* S = standard. */
1807 case ADDR_SW_256B_S:
1808 case ADDR_SW_4KB_S:
1809 case ADDR_SW_64KB_S:
1810 case ADDR_SW_64KB_S_T:
1811 case ADDR_SW_4KB_S_X:
1812 case ADDR_SW_64KB_S_X:
1813 surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
1814 break;
1815
1816 /* D = display. */
1817 case ADDR_SW_LINEAR:
1818 case ADDR_SW_256B_D:
1819 case ADDR_SW_4KB_D:
1820 case ADDR_SW_64KB_D:
1821 case ADDR_SW_64KB_D_T:
1822 case ADDR_SW_4KB_D_X:
1823 case ADDR_SW_64KB_D_X:
1824 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1825 break;
1826
1827 /* R = rotated (gfx9), render target (gfx10). */
1828 case ADDR_SW_256B_R:
1829 case ADDR_SW_4KB_R:
1830 case ADDR_SW_64KB_R:
1831 case ADDR_SW_64KB_R_T:
1832 case ADDR_SW_4KB_R_X:
1833 case ADDR_SW_64KB_R_X:
1834 case ADDR_SW_VAR_R_X:
1835 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1836 * used at the same time. We currently do not use rotated
1837 * in gfx9.
1838 */
1839 assert(info->chip_class >= GFX10 ||
1840 !"rotate micro tile mode is unsupported");
1841 surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER;
1842 break;
1843
1844 /* Z = depth. */
1845 case ADDR_SW_4KB_Z:
1846 case ADDR_SW_64KB_Z:
1847 case ADDR_SW_64KB_Z_T:
1848 case ADDR_SW_4KB_Z_X:
1849 case ADDR_SW_64KB_Z_X:
1850 case ADDR_SW_VAR_Z_X:
1851 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1852 break;
1853
1854 default:
1855 assert(0);
1856 }
1857
1858 return 0;
1859
1860 error:
1861 free(surf->u.gfx9.dcc_retile_map);
1862 surf->u.gfx9.dcc_retile_map = NULL;
1863 return r;
1864 }
1865
1866 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1867 const struct ac_surf_config *config,
1868 enum radeon_surf_mode mode,
1869 struct radeon_surf *surf)
1870 {
1871 int r;
1872
1873 r = surf_config_sanity(config, surf->flags);
1874 if (r)
1875 return r;
1876
1877 if (info->chip_class >= GFX9)
1878 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
1879 else
1880 r = gfx6_compute_surface(addrlib, info, config, mode, surf);
1881
1882 if (r)
1883 return r;
1884
1885 /* Determine the memory layout of multiple allocations in one buffer. */
1886 surf->total_size = surf->surf_size;
1887 surf->alignment = surf->surf_alignment;
1888
1889 if (surf->htile_size) {
1890 surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
1891 surf->total_size = surf->htile_offset + surf->htile_size;
1892 surf->alignment = MAX2(surf->alignment, surf->htile_alignment);
1893 }
1894
1895 if (surf->fmask_size) {
1896 assert(config->info.samples >= 2);
1897 surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
1898 surf->total_size = surf->fmask_offset + surf->fmask_size;
1899 surf->alignment = MAX2(surf->alignment, surf->fmask_alignment);
1900 }
1901
1902 /* Single-sample CMASK is in a separate buffer. */
1903 if (surf->cmask_size && config->info.samples >= 2) {
1904 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
1905 surf->total_size = surf->cmask_offset + surf->cmask_size;
1906 surf->alignment = MAX2(surf->alignment, surf->cmask_alignment);
1907 }
1908
1909 if (surf->is_displayable)
1910 surf->flags |= RADEON_SURF_SCANOUT;
1911
1912 if (surf->dcc_size &&
1913 /* dcc_size is computed on GFX9+ only if it's displayable. */
1914 (info->chip_class >= GFX9 || !get_display_flag(config, surf))) {
1915 /* It's better when displayable DCC is immediately after
1916 * the image due to hw-specific reasons.
1917 */
1918 if (info->chip_class >= GFX9 &&
1919 surf->u.gfx9.dcc_retile_num_elements) {
1920 /* Add space for the displayable DCC buffer. */
1921 surf->display_dcc_offset =
1922 align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
1923 surf->total_size = surf->display_dcc_offset +
1924 surf->u.gfx9.display_dcc_size;
1925
1926 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1927 surf->dcc_retile_map_offset =
1928 align64(surf->total_size, info->tcc_cache_line_size);
1929
1930 if (surf->u.gfx9.dcc_retile_use_uint16) {
1931 surf->total_size = surf->dcc_retile_map_offset +
1932 surf->u.gfx9.dcc_retile_num_elements * 2;
1933 } else {
1934 surf->total_size = surf->dcc_retile_map_offset +
1935 surf->u.gfx9.dcc_retile_num_elements * 4;
1936 }
1937 }
1938
1939 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
1940 surf->total_size = surf->dcc_offset + surf->dcc_size;
1941 surf->alignment = MAX2(surf->alignment, surf->dcc_alignment);
1942 }
1943
1944 return 0;
1945 }
1946
1947 /* This is meant to be used for disabling DCC. */
1948 void ac_surface_zero_dcc_fields(struct radeon_surf *surf)
1949 {
1950 surf->dcc_offset = 0;
1951 surf->display_dcc_offset = 0;
1952 surf->dcc_retile_map_offset = 0;
1953 }
1954
1955 static unsigned eg_tile_split(unsigned tile_split)
1956 {
1957 switch (tile_split) {
1958 case 0: tile_split = 64; break;
1959 case 1: tile_split = 128; break;
1960 case 2: tile_split = 256; break;
1961 case 3: tile_split = 512; break;
1962 default:
1963 case 4: tile_split = 1024; break;
1964 case 5: tile_split = 2048; break;
1965 case 6: tile_split = 4096; break;
1966 }
1967 return tile_split;
1968 }
1969
1970 static unsigned eg_tile_split_rev(unsigned eg_tile_split)
1971 {
1972 switch (eg_tile_split) {
1973 case 64: return 0;
1974 case 128: return 1;
1975 case 256: return 2;
1976 case 512: return 3;
1977 default:
1978 case 1024: return 4;
1979 case 2048: return 5;
1980 case 4096: return 6;
1981 }
1982 }
1983
1984 #define AMDGPU_TILING_DCC_MAX_COMPRESSED_BLOCK_SIZE_SHIFT 45
1985 #define AMDGPU_TILING_DCC_MAX_COMPRESSED_BLOCK_SIZE_MASK 0x3
1986
1987 /* This should be called before ac_compute_surface. */
1988 void ac_surface_set_bo_metadata(const struct radeon_info *info,
1989 struct radeon_surf *surf, uint64_t tiling_flags,
1990 enum radeon_surf_mode *mode)
1991 {
1992 bool scanout;
1993
1994 if (info->chip_class >= GFX9) {
1995 surf->u.gfx9.surf.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1996 surf->u.gfx9.dcc.independent_64B_blocks = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B);
1997 surf->u.gfx9.dcc.independent_128B_blocks = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_128B);
1998 surf->u.gfx9.dcc.max_compressed_block_size = AMDGPU_TILING_GET(tiling_flags, DCC_MAX_COMPRESSED_BLOCK_SIZE);
1999 surf->u.gfx9.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX);
2000 scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT);
2001 *mode = surf->u.gfx9.surf.swizzle_mode > 0 ? RADEON_SURF_MODE_2D : RADEON_SURF_MODE_LINEAR_ALIGNED;
2002 } else {
2003 surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2004 surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2005 surf->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2006 surf->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
2007 surf->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2008 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2009 scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
2010
2011 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
2012 *mode = RADEON_SURF_MODE_2D;
2013 else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
2014 *mode = RADEON_SURF_MODE_1D;
2015 else
2016 *mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
2017 }
2018
2019 if (scanout)
2020 surf->flags |= RADEON_SURF_SCANOUT;
2021 else
2022 surf->flags &= ~RADEON_SURF_SCANOUT;
2023 }
2024
2025 void ac_surface_get_bo_metadata(const struct radeon_info *info,
2026 struct radeon_surf *surf, uint64_t *tiling_flags)
2027 {
2028 *tiling_flags = 0;
2029
2030 if (info->chip_class >= GFX9) {
2031 uint64_t dcc_offset = 0;
2032
2033 if (surf->dcc_offset) {
2034 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset
2035 : surf->dcc_offset;
2036 assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24));
2037 }
2038
2039 *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.surf.swizzle_mode);
2040 *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8);
2041 *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.display_dcc_pitch_max);
2042 *tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.dcc.independent_64B_blocks);
2043 *tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.dcc.independent_128B_blocks);
2044 *tiling_flags |= AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE, surf->u.gfx9.dcc.max_compressed_block_size);
2045 *tiling_flags |= AMDGPU_TILING_SET(SCANOUT, (surf->flags & RADEON_SURF_SCANOUT) != 0);
2046 } else {
2047 if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D)
2048 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
2049 else if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D)
2050 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
2051 else
2052 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
2053
2054 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, surf->u.legacy.pipe_config);
2055 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(surf->u.legacy.bankw));
2056 *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(surf->u.legacy.bankh));
2057 if (surf->u.legacy.tile_split)
2058 *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(surf->u.legacy.tile_split));
2059 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(surf->u.legacy.mtilea));
2060 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks)-1);
2061
2062 if (surf->flags & RADEON_SURF_SCANOUT)
2063 *tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */
2064 else
2065 *tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */
2066 }
2067 }
2068
2069 static uint32_t ac_get_umd_metadata_word1(const struct radeon_info *info)
2070 {
2071 return (ATI_VENDOR_ID << 16) | info->pci_id;
2072 }
2073
2074 /* This should be called after ac_compute_surface. */
2075 bool ac_surface_set_umd_metadata(const struct radeon_info *info,
2076 struct radeon_surf *surf,
2077 unsigned num_storage_samples,
2078 unsigned num_mipmap_levels,
2079 unsigned size_metadata,
2080 uint32_t metadata[64])
2081 {
2082 uint32_t *desc = &metadata[2];
2083 uint64_t offset;
2084
2085 if (info->chip_class >= GFX9)
2086 offset = surf->u.gfx9.surf_offset;
2087 else
2088 offset = surf->u.legacy.level[0].offset;
2089
2090 if (offset || /* Non-zero planes ignore metadata. */
2091 size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */
2092 metadata[0] == 0 || /* invalid version number */
2093 metadata[1] != ac_get_umd_metadata_word1(info)) /* invalid PCI ID */ {
2094 /* Disable DCC because it might not be enabled. */
2095 ac_surface_zero_dcc_fields(surf);
2096
2097 /* Don't report an error if the texture comes from an incompatible driver,
2098 * but this might not work.
2099 */
2100 return true;
2101 }
2102
2103 /* Validate that sample counts and the number of mipmap levels match. */
2104 unsigned desc_last_level = G_008F1C_LAST_LEVEL(desc[3]);
2105 unsigned type = G_008F1C_TYPE(desc[3]);
2106
2107 if (type == V_008F1C_SQ_RSRC_IMG_2D_MSAA || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2108 unsigned log_samples = util_logbase2(MAX2(1, num_storage_samples));
2109
2110 if (desc_last_level != log_samples) {
2111 fprintf(stderr,
2112 "amdgpu: invalid MSAA texture import, "
2113 "metadata has log2(samples) = %u, the caller set %u\n",
2114 desc_last_level, log_samples);
2115 return false;
2116 }
2117 } else {
2118 if (desc_last_level != num_mipmap_levels - 1) {
2119 fprintf(stderr,
2120 "amdgpu: invalid mipmapped texture import, "
2121 "metadata has last_level = %u, the caller set %u\n",
2122 desc_last_level, num_mipmap_levels - 1);
2123 return false;
2124 }
2125 }
2126
2127 if (info->chip_class >= GFX8 && G_008F28_COMPRESSION_EN(desc[6])) {
2128 /* Read DCC information. */
2129 switch (info->chip_class) {
2130 case GFX8:
2131 surf->dcc_offset = (uint64_t)desc[7] << 8;
2132 break;
2133
2134 case GFX9:
2135 surf->dcc_offset =
2136 ((uint64_t)desc[7] << 8) | ((uint64_t)G_008F24_META_DATA_ADDRESS(desc[5]) << 40);
2137 surf->u.gfx9.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]);
2138 surf->u.gfx9.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]);
2139
2140 /* If DCC is unaligned, this can only be a displayable image. */
2141 if (!surf->u.gfx9.dcc.pipe_aligned && !surf->u.gfx9.dcc.rb_aligned)
2142 assert(surf->is_displayable);
2143 break;
2144
2145 case GFX10:
2146 case GFX10_3:
2147 surf->dcc_offset =
2148 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) | ((uint64_t)desc[7] << 16);
2149 surf->u.gfx9.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]);
2150 break;
2151
2152 default:
2153 assert(0);
2154 return false;
2155 }
2156 } else {
2157 /* Disable DCC. dcc_offset is always set by texture_from_handle
2158 * and must be cleared here.
2159 */
2160 ac_surface_zero_dcc_fields(surf);
2161 }
2162
2163 return true;
2164 }
2165
2166 void ac_surface_get_umd_metadata(const struct radeon_info *info,
2167 struct radeon_surf *surf,
2168 unsigned num_mipmap_levels,
2169 uint32_t desc[8],
2170 unsigned *size_metadata, uint32_t metadata[64])
2171 {
2172 /* Clear the base address and set the relative DCC offset. */
2173 desc[0] = 0;
2174 desc[1] &= C_008F14_BASE_ADDRESS_HI;
2175
2176 switch (info->chip_class) {
2177 case GFX6:
2178 case GFX7:
2179 break;
2180 case GFX8:
2181 desc[7] = surf->dcc_offset >> 8;
2182 break;
2183 case GFX9:
2184 desc[7] = surf->dcc_offset >> 8;
2185 desc[5] &= C_008F24_META_DATA_ADDRESS;
2186 desc[5] |= S_008F24_META_DATA_ADDRESS(surf->dcc_offset >> 40);
2187 break;
2188 case GFX10:
2189 case GFX10_3:
2190 desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
2191 desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->dcc_offset >> 8);
2192 desc[7] = surf->dcc_offset >> 16;
2193 break;
2194 default:
2195 assert(0);
2196 }
2197
2198 /* Metadata image format format version 1:
2199 * [0] = 1 (metadata format identifier)
2200 * [1] = (VENDOR_ID << 16) | PCI_ID
2201 * [2:9] = image descriptor for the whole resource
2202 * [2] is always 0, because the base address is cleared
2203 * [9] is the DCC offset bits [39:8] from the beginning of
2204 * the buffer
2205 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
2206 */
2207
2208 metadata[0] = 1; /* metadata image format version 1 */
2209
2210 /* Tiling modes are ambiguous without a PCI ID. */
2211 metadata[1] = ac_get_umd_metadata_word1(info);
2212
2213 /* Dwords [2:9] contain the image descriptor. */
2214 memcpy(&metadata[2], desc, 8 * 4);
2215 *size_metadata = 10 * 4;
2216
2217 /* Dwords [10:..] contain the mipmap level offsets. */
2218 if (info->chip_class <= GFX8) {
2219 for (unsigned i = 0; i < num_mipmap_levels; i++)
2220 metadata[10 + i] = surf->u.legacy.level[i].offset >> 8;
2221
2222 *size_metadata += num_mipmap_levels * 4;
2223 }
2224 }
2225
2226 void ac_surface_override_offset_stride(const struct radeon_info *info,
2227 struct radeon_surf *surf,
2228 unsigned num_mipmap_levels,
2229 uint64_t offset, unsigned pitch)
2230 {
2231 if (info->chip_class >= GFX9) {
2232 if (pitch) {
2233 surf->u.gfx9.surf_pitch = pitch;
2234 if (num_mipmap_levels == 1)
2235 surf->u.gfx9.surf.epitch = pitch - 1;
2236 surf->u.gfx9.surf_slice_size =
2237 (uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe;
2238 }
2239 surf->u.gfx9.surf_offset = offset;
2240 if (surf->u.gfx9.stencil_offset)
2241 surf->u.gfx9.stencil_offset += offset;
2242 } else {
2243 if (pitch) {
2244 surf->u.legacy.level[0].nblk_x = pitch;
2245 surf->u.legacy.level[0].slice_size_dw =
2246 ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4;
2247 }
2248
2249 if (offset) {
2250 for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i)
2251 surf->u.legacy.level[i].offset += offset;
2252 }
2253 }
2254
2255 if (surf->htile_offset)
2256 surf->htile_offset += offset;
2257 if (surf->fmask_offset)
2258 surf->fmask_offset += offset;
2259 if (surf->cmask_offset)
2260 surf->cmask_offset += offset;
2261 if (surf->dcc_offset)
2262 surf->dcc_offset += offset;
2263 if (surf->display_dcc_offset)
2264 surf->display_dcc_offset += offset;
2265 if (surf->dcc_retile_map_offset)
2266 surf->dcc_retile_map_offset += offset;
2267 }