2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
32 #include "amd_family.h"
38 /* Forward declarations. */
41 struct amdgpu_gpu_info
;
44 #define RADEON_SURF_MAX_LEVELS 15
46 enum radeon_surf_mode
{
47 RADEON_SURF_MODE_LINEAR_ALIGNED
= 1,
48 RADEON_SURF_MODE_1D
= 2,
49 RADEON_SURF_MODE_2D
= 3,
52 /* This describes D/S/Z/R swizzle modes.
53 * Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order.
55 enum radeon_micro_mode
{
56 RADEON_MICRO_MODE_DISPLAY
= 0,
57 RADEON_MICRO_MODE_STANDARD
= 1,
58 RADEON_MICRO_MODE_DEPTH
= 2,
59 RADEON_MICRO_MODE_RENDER
= 3, /* gfx9 and older: rotated */
62 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
63 #define RADEON_SURF_SCANOUT (1 << 16)
64 #define RADEON_SURF_ZBUFFER (1 << 17)
65 #define RADEON_SURF_SBUFFER (1 << 18)
66 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
67 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
68 #define RADEON_SURF_FMASK (1 << 21)
69 #define RADEON_SURF_DISABLE_DCC (1 << 22)
70 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
71 #define RADEON_SURF_IMPORTED (1 << 24)
72 #define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1 << 25)
73 #define RADEON_SURF_SHAREABLE (1 << 26)
74 #define RADEON_SURF_NO_RENDER_TARGET (1 << 27)
75 /* Force a swizzle mode (gfx9+) or tile mode (gfx6-8).
76 * If this is not set, optimize for space. */
77 #define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
78 #define RADEON_SURF_NO_FMASK (1 << 29)
79 #define RADEON_SURF_NO_HTILE (1 << 30)
80 #define RADEON_SURF_FORCE_MICRO_TILE_MODE (1u << 31)
82 struct legacy_surf_level
{
84 uint32_t slice_size_dw
; /* in dwords; max = 4GB / 4. */
85 uint32_t dcc_offset
; /* relative offset within DCC mip tree */
86 uint32_t dcc_fast_clear_size
;
87 uint32_t dcc_slice_fast_clear_size
;
90 enum radeon_surf_mode mode
:2;
93 struct legacy_surf_fmask
{
94 unsigned slice_tile_max
; /* max 4M */
95 uint8_t tiling_index
; /* max 31 */
96 uint8_t bankh
; /* max 8 */
97 uint16_t pitch_in_pixels
;
101 struct legacy_surf_layout
{
102 unsigned bankw
:4; /* max 8 */
103 unsigned bankh
:4; /* max 8 */
104 unsigned mtilea
:4; /* max 8 */
105 unsigned tile_split
:13; /* max 4K */
106 unsigned stencil_tile_split
:13; /* max 4K */
107 unsigned pipe_config
:5; /* max 17 */
108 unsigned num_banks
:5; /* max 16 */
109 unsigned macro_tile_index
:4; /* max 15 */
111 /* Whether the depth miptree or stencil miptree as used by the DB are
112 * adjusted from their TC compatible form to ensure depth/stencil
113 * compatibility. If either is true, the corresponding plane cannot be
116 unsigned depth_adjusted
:1;
117 unsigned stencil_adjusted
:1;
119 struct legacy_surf_level level
[RADEON_SURF_MAX_LEVELS
];
120 struct legacy_surf_level stencil_level
[RADEON_SURF_MAX_LEVELS
];
121 uint8_t tiling_index
[RADEON_SURF_MAX_LEVELS
];
122 uint8_t stencil_tiling_index
[RADEON_SURF_MAX_LEVELS
];
123 struct legacy_surf_fmask fmask
;
124 unsigned cmask_slice_tile_max
;
127 /* Same as addrlib - AddrResourceType. */
128 enum gfx9_resource_type
{
129 RADEON_RESOURCE_1D
= 0,
134 struct gfx9_surf_flags
{
135 uint16_t swizzle_mode
; /* tile mode */
136 uint16_t epitch
; /* (pitch - 1) or (height - 1) */
139 struct gfx9_surf_meta_flags
{
140 unsigned rb_aligned
:1; /* optimal for RBs */
141 unsigned pipe_aligned
:1; /* optimal for TC */
142 unsigned independent_64B_blocks
:1;
143 unsigned independent_128B_blocks
:1;
144 unsigned max_compressed_block_size
:2;
147 struct gfx9_surf_layout
{
148 struct gfx9_surf_flags surf
; /* color or depth surface */
149 struct gfx9_surf_flags fmask
; /* not added to surf_size */
150 struct gfx9_surf_flags stencil
; /* added to surf_size, use stencil_offset */
152 struct gfx9_surf_meta_flags dcc
; /* metadata of color */
154 enum gfx9_resource_type resource_type
; /* 1D, 2D or 3D */
155 uint16_t surf_pitch
; /* in blocks */
156 uint16_t surf_height
;
158 uint64_t surf_offset
; /* 0 unless imported with an offset */
159 /* The size of the 2D plane containing all mipmap levels. */
160 uint64_t surf_slice_size
;
161 /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
162 uint32_t offset
[RADEON_SURF_MAX_LEVELS
];
163 /* Mipmap level pitch in elements. Only valid for LINEAR. */
164 uint16_t pitch
[RADEON_SURF_MAX_LEVELS
];
166 uint64_t stencil_offset
; /* separate stencil */
168 uint8_t dcc_block_width
;
169 uint8_t dcc_block_height
;
170 uint8_t dcc_block_depth
;
172 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
173 * The 3D engine doesn't support that layout except for chips with 1 RB.
174 * All other chips must set rb_aligned=1.
175 * A compute shader needs to convert from aligned DCC to unaligned.
177 uint32_t display_dcc_size
;
178 uint32_t display_dcc_alignment
;
179 uint16_t display_dcc_pitch_max
; /* (mip chain pitch - 1) */
180 bool dcc_retile_use_uint16
; /* if all values fit into uint16_t */
181 uint32_t dcc_retile_num_elements
;
182 void *dcc_retile_map
;
186 /* Format properties. */
190 /* Number of mipmap levels where DCC is enabled starting from level 0.
191 * Non-zero levels may be disabled due to alignment constraints, but not
194 unsigned num_dcc_levels
:4;
195 unsigned is_linear
:1;
196 unsigned has_stencil
:1;
197 /* This might be true even if micro_tile_mode isn't displayable or rotated. */
198 unsigned is_displayable
:1;
199 /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
200 unsigned micro_tile_mode
:3;
203 /* These are return values. Some of them can be set by the caller, but
204 * they will be treated as hints (e.g. bankw, bankh) and might be
205 * changed by the calculator.
208 /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
209 * The value is the same for all mipmap levels. Supported tile modes:
210 * - GFX6: Only macro tiling.
211 * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
214 * Only these surfaces are allowed to set it:
215 * - color (if it doesn't have to be displayable)
216 * - DCC (same tile swizzle as color)
218 * - CMASK if it's TC-compatible or if the gen is GFX9
219 * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
221 uint8_t tile_swizzle
;
222 uint8_t fmask_tile_swizzle
;
226 uint32_t surf_alignment
;
227 uint32_t fmask_alignment
;
229 /* DCC and HTILE are very small. */
231 uint32_t dcc_slice_size
;
232 uint32_t dcc_alignment
;
235 uint32_t htile_slice_size
;
236 uint32_t htile_alignment
;
239 uint32_t cmask_slice_size
;
240 uint32_t cmask_alignment
;
242 /* All buffers combined. */
243 uint64_t htile_offset
;
244 uint64_t fmask_offset
;
245 uint64_t cmask_offset
;
247 uint64_t display_dcc_offset
;
248 uint64_t dcc_retile_map_offset
;
253 /* Return values for GFX8 and older.
255 * Some of them can be set by the caller if certain parameters are
256 * desirable. The allocator will try to obey them.
258 struct legacy_surf_layout legacy
;
260 /* GFX9+ return values. */
261 struct gfx9_surf_layout gfx9
;
265 struct ac_surf_info
{
269 uint8_t samples
; /* For Z/S: samples; For color: FMASK coverage samples */
270 uint8_t storage_samples
; /* For color: allocated samples */
272 uint8_t num_channels
; /* heuristic for displayability */
274 uint32_t *surf_index
; /* Set a monotonic counter for tile swizzling. */
275 uint32_t *fmask_surf_index
;
278 struct ac_surf_config
{
279 struct ac_surf_info info
;
282 unsigned is_cube
: 1;
285 struct ac_addrlib
*ac_addrlib_create(const struct radeon_info
*info
,
286 const struct amdgpu_gpu_info
*amdinfo
,
287 uint64_t *max_alignment
);
288 void ac_addrlib_destroy(struct ac_addrlib
*addrlib
);
290 int ac_compute_surface(struct ac_addrlib
*addrlib
, const struct radeon_info
*info
,
291 const struct ac_surf_config
* config
,
292 enum radeon_surf_mode mode
,
293 struct radeon_surf
*surf
);
294 void ac_surface_zero_dcc_fields(struct radeon_surf
*surf
);
296 void ac_surface_set_bo_metadata(const struct radeon_info
*info
,
297 struct radeon_surf
*surf
, uint64_t tiling_flags
,
298 enum radeon_surf_mode
*mode
);
299 void ac_surface_get_bo_metadata(const struct radeon_info
*info
,
300 struct radeon_surf
*surf
, uint64_t *tiling_flags
);
302 bool ac_surface_set_umd_metadata(const struct radeon_info
*info
,
303 struct radeon_surf
*surf
,
304 unsigned num_storage_samples
,
305 unsigned num_mipmap_levels
,
306 unsigned size_metadata
,
307 uint32_t metadata
[64]);
308 void ac_surface_get_umd_metadata(const struct radeon_info
*info
,
309 struct radeon_surf
*surf
,
310 unsigned num_mipmap_levels
,
312 unsigned *size_metadata
, uint32_t metadata
[64]);
314 void ac_surface_override_offset_stride(const struct radeon_info
*info
,
315 struct radeon_surf
*surf
,
316 unsigned num_mipmap_levels
,
317 uint64_t offset
, unsigned pitch
);
323 #endif /* AC_SURFACE_H */