src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30
  31 #include "amd_family.h"
  32
  33 /* Forward declarations. */
  34 typedef void* ADDR_HANDLE;
  35
  36 struct amdgpu_gpu_info;
  37
  38 #define RADEON_SURF_MAX_LEVELS                  15
  39
  40 enum radeon_surf_mode {
  41     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  42     RADEON_SURF_MODE_1D = 2,
  43     RADEON_SURF_MODE_2D = 3,
  44 };
  45
  46 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  47 enum radeon_micro_mode {
  48     RADEON_MICRO_MODE_DISPLAY = 0,
  49     RADEON_MICRO_MODE_THIN = 1,
  50     RADEON_MICRO_MODE_DEPTH = 2,
  51     RADEON_MICRO_MODE_ROTATED = 3,
  52 };
  53
  54 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  55 #define RADEON_SURF_SCANOUT                     (1 << 16)
  56 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  57 #define RADEON_SURF_SBUFFER                     (1 << 18)
  58 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  59 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  60 #define RADEON_SURF_FMASK                       (1 << 21)
  61 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  62 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  63 #define RADEON_SURF_IMPORTED                    (1 << 24)
  64 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  65
  66 struct legacy_surf_level {
  67     uint64_t                    offset;
  68     uint64_t                    slice_size;
  69     uint64_t                    dcc_offset;
  70     uint64_t                    dcc_fast_clear_size;
  71     uint16_t                    nblk_x;
  72     uint16_t                    nblk_y;
  73     enum radeon_surf_mode       mode;
  74 };
  75
  76 struct legacy_surf_layout {
  77     unsigned                    bankw:4;  /* max 8 */
  78     unsigned                    bankh:4;  /* max 8 */
  79     unsigned                    mtilea:4; /* max 8 */
  80     unsigned                    tile_split:13;         /* max 4K */
  81     unsigned                    stencil_tile_split:13; /* max 4K */
  82     unsigned                    pipe_config:5;      /* max 17 */
  83     unsigned                    num_banks:5;        /* max 16 */
  84     unsigned                    macro_tile_index:4; /* max 15 */
  85
  86     /* Whether the depth miptree or stencil miptree as used by the DB are
  87      * adjusted from their TC compatible form to ensure depth/stencil
  88      * compatibility. If either is true, the corresponding plane cannot be
  89      * sampled from.
  90      */
  91     unsigned                    depth_adjusted:1;
  92     unsigned                    stencil_adjusted:1;
  93
  94     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
  95     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
  96     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
  97     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
  98 };
  99
 100 /* Same as addrlib - AddrResourceType. */
 101 enum gfx9_resource_type {
 102     RADEON_RESOURCE_1D = 0,
 103     RADEON_RESOURCE_2D,
 104     RADEON_RESOURCE_3D,
 105 };
 106
 107 struct gfx9_surf_flags {
 108     uint16_t                    swizzle_mode; /* tile mode */
 109     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 110 };
 111
 112 struct gfx9_surf_meta_flags {
 113     unsigned                    rb_aligned:1;   /* optimal for RBs */
 114     unsigned                    pipe_aligned:1; /* optimal for TC */
 115 };
 116
 117 struct gfx9_surf_layout {
 118     struct gfx9_surf_flags      surf;    /* color or depth surface */
 119     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 120     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 121
 122     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 123     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 124     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 125
 126     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 127     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 128     /* The size of the 2D plane containing all mipmap levels. */
 129     uint64_t                    surf_slice_size;
 130     uint16_t                    surf_pitch; /* in blocks */
 131     uint16_t                    surf_height;
 132     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 133     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 134
 135     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 136
 137     uint64_t                    stencil_offset; /* separate stencil */
 138     uint64_t                    fmask_size;
 139     uint64_t                    cmask_size;
 140
 141     uint32_t                    fmask_alignment;
 142     uint32_t                    cmask_alignment;
 143 };
 144
 145 struct radeon_surf {
 146     /* Format properties. */
 147     unsigned                    blk_w:4;
 148     unsigned                    blk_h:4;
 149     unsigned                    bpe:5;
 150     /* Number of mipmap levels where DCC is enabled starting from level 0.
 151      * Non-zero levels may be disabled due to alignment constraints, but not
 152      * the first level.
 153      */
 154     unsigned                    num_dcc_levels:4;
 155     unsigned                    is_linear:1;
 156     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 157     unsigned                    micro_tile_mode:3;
 158     uint32_t                    flags;
 159
 160     /* These are return values. Some of them can be set by the caller, but
 161      * they will be treated as hints (e.g. bankw, bankh) and might be
 162      * changed by the calculator.
 163      */
 164     uint64_t                    surf_size;
 165     uint64_t                    dcc_size;
 166     uint64_t                    htile_size;
 167
 168     uint32_t                    surf_alignment;
 169     uint32_t                    dcc_alignment;
 170     uint32_t                    htile_alignment;
 171
 172     union {
 173         /* R600-VI return values.
 174          *
 175          * Some of them can be set by the caller if certain parameters are
 176          * desirable. The allocator will try to obey them.
 177          */
 178         struct legacy_surf_layout legacy;
 179
 180         /* GFX9+ return values. */
 181         struct gfx9_surf_layout gfx9;
 182     } u;
 183 };
 184
 185 ADDR_HANDLE amdgpu_addr_create(enum radeon_family family,
 186                                const struct amdgpu_gpu_info *info);
 187
 188 #endif /* AC_SURFACE_H */