src/amd/common/amdgpu_id.h

   1 /*
   2  * Copyright © 2014 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 /**
  28  * This file is included by addrlib. It adds GPU family definitions and
  29  * macros compatible with addrlib.
  30  */
  31
  32 #ifndef AMDGPU_ID_H
  33 #define AMDGPU_ID_H
  34
  35 #include "util/u_endian.h"
  36
  37 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
  38 #define LITTLEENDIAN_CPU
  39 #elif defined(PIPE_ARCH_BIG_ENDIAN)
  40 #define BIGENDIAN_CPU
  41 #endif
  42
  43 enum {
  44         FAMILY_UNKNOWN,
  45         FAMILY_SI,
  46         FAMILY_CI,
  47         FAMILY_KV,
  48         FAMILY_VI,
  49         FAMILY_CZ,
  50         FAMILY_PI,
  51         FAMILY_AI,
  52         FAMILY_LAST,
  53 };
  54
  55 /* SI specific rev IDs */
  56 enum {
  57         SI_TAHITI_P_A11      = 1,
  58         SI_TAHITI_P_A0       = SI_TAHITI_P_A11,      /*A0 is alias of A11*/
  59         SI_TAHITI_P_A21      = 5,
  60         SI_TAHITI_P_B0       = SI_TAHITI_P_A21,      /*B0 is alias of A21*/
  61         SI_TAHITI_P_A22      = 6,
  62         SI_TAHITI_P_B1       = SI_TAHITI_P_A22,      /*B1 is alias of A22*/
  63
  64         SI_PITCAIRN_PM_A11   = 20,
  65         SI_PITCAIRN_PM_A0    = SI_PITCAIRN_PM_A11,   /*A0 is alias of A11*/
  66         SI_PITCAIRN_PM_A12   = 21,
  67         SI_PITCAIRN_PM_A1    = SI_PITCAIRN_PM_A12,   /*A1 is alias of A12*/
  68
  69         SI_CAPEVERDE_M_A11   = 40,
  70         SI_CAPEVERDE_M_A0    = SI_CAPEVERDE_M_A11,   /*A0 is alias of A11*/
  71         SI_CAPEVERDE_M_A12   = 41,
  72         SI_CAPEVERDE_M_A1    = SI_CAPEVERDE_M_A12,   /*A1 is alias of A12*/
  73
  74         SI_OLAND_M_A0        = 60,
  75
  76         SI_HAINAN_V_A0       = 70,
  77
  78         SI_UNKNOWN           = 0xFF
  79 };
  80
  81
  82 #define ASICREV_IS_TAHITI_P(eChipRev)   \
  83         (eChipRev < SI_PITCAIRN_PM_A11)
  84 #define ASICREV_IS_PITCAIRN_PM(eChipRev)        \
  85         ((eChipRev >= SI_PITCAIRN_PM_A11) && (eChipRev < SI_CAPEVERDE_M_A11))
  86 #define ASICREV_IS_CAPEVERDE_M(eChipRev)        \
  87         ((eChipRev >= SI_CAPEVERDE_M_A11) && (eChipRev < SI_OLAND_M_A0))
  88 #define ASICREV_IS_OLAND_M(eChipRev)    \
  89         ((eChipRev >= SI_OLAND_M_A0) && (eChipRev < SI_HAINAN_V_A0))
  90 #define ASICREV_IS_HAINAN_V(eChipRev)   \
  91 (eChipRev >= SI_HAINAN_V_A0)
  92
  93 /* CI specific revIDs */
  94 enum {
  95         CI_BONAIRE_M_A0 = 20,
  96         CI_BONAIRE_M_A1 = 21,
  97
  98         CI_HAWAII_P_A0  = 40,
  99
 100         CI_UNKNOWN      = 0xFF
 101 };
 102
 103 #define ASICREV_IS_BONAIRE_M(eChipRev)  \
 104         ((eChipRev >= CI_BONAIRE_M_A0) && (eChipRev < CI_HAWAII_P_A0))
 105 #define ASICREV_IS_HAWAII_P(eChipRev)   \
 106         (eChipRev >= CI_HAWAII_P_A0)
 107
 108 /* KV specific rev IDs */
 109 enum {
 110         KV_SPECTRE_A0      = 0x01,       /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
 111         KV_SPOOKY_A0       = 0x41,       /* KV2 with Spooky GFX core, including downgraded from Spectre core, 3-4-1-1 (CU-Pix-Primitive-RB) */
 112         KB_KALINDI_A0      = 0x81,       /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
 113         KB_KALINDI_A1      = 0x82,       /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
 114         BV_KALINDI_A2      = 0x85,       /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
 115         ML_GODAVARI_A0     = 0xa1,      /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
 116         ML_GODAVARI_A1     = 0xa2,      /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
 117         KV_UNKNOWN = 0xFF
 118 };
 119
 120 #define ASICREV_IS_SPECTRE(eChipRev)    \
 121         ((eChipRev >= KV_SPECTRE_A0) && (eChipRev < KV_SPOOKY_A0))         /* identify all versions of SPRECTRE and supported features set */
 122 #define ASICREV_IS_SPOOKY(eChipRev)     \
 123         ((eChipRev >= KV_SPOOKY_A0) && (eChipRev < KB_KALINDI_A0))          /* identify all versions of SPOOKY and supported features set */
 124 #define ASICREV_IS_KALINDI(eChipRev)    \
 125         ((eChipRev >= KB_KALINDI_A0) && (eChipRev < KV_UNKNOWN))           /* identify all versions of KALINDI and supported features set */
 126
 127 /* Following macros are subset of ASICREV_IS_KALINDI macro */
 128 #define ASICREV_IS_KALINDI_BHAVANI(eChipRev)    \
 129         ((eChipRev >= BV_KALINDI_A2) && (eChipRev < ML_GODAVARI_A0))   /* identify all versions of BHAVANI and supported features set */
 130 #define ASICREV_IS_KALINDI_GODAVARI(eChipRev)   \
 131         ((eChipRev >= ML_GODAVARI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of GODAVARI and supported features set */
 132
 133 /* VI specific rev IDs */
 134 enum {
 135         VI_ICELAND_M_A0   = 1,
 136
 137         VI_TONGA_P_A0     = 20,
 138         VI_TONGA_P_A1     = 21,
 139
 140         VI_FIJI_P_A0      = 60,
 141
 142         VI_POLARIS10_P_A0 = 80,
 143
 144         VI_POLARIS11_M_A0 = 90,
 145
 146         VI_POLARIS12_V_A0 = 100,
 147
 148         VI_UNKNOWN        = 0xFF
 149 };
 150
 151
 152 #define ASICREV_IS_ICELAND_M(eChipRev)  \
 153         (eChipRev < VI_TONGA_P_A0)
 154 #define ASICREV_IS_TONGA_P(eChipRev)    \
 155         ((eChipRev >= VI_TONGA_P_A0) && (eChipRev < VI_FIJI_P_A0))
 156 #define ASICREV_IS_FIJI_P(eChipRev)     \
 157         ((eChipRev >= VI_FIJI_P_A0)  && (eChipRev < VI_POLARIS10_P_A0))
 158 #define ASICREV_IS_POLARIS10_P(eChipRev)\
 159         ((eChipRev >= VI_POLARIS10_P_A0) && (eChipRev < VI_POLARIS11_M_A0))
 160 #define ASICREV_IS_POLARIS11_M(eChipRev)   \
 161         (eChipRev >= VI_POLARIS11_M_A0 && eChipRev < VI_POLARIS12_V_A0)
 162 #define ASICREV_IS_POLARIS12_V(eChipRev)\
 163         (eChipRev >= VI_POLARIS12_V_A0)
 164
 165 /* CZ specific rev IDs */
 166 enum {
 167         CARRIZO_A0   = 0x01,
 168     STONEY_A0    = 0x61,
 169         CZ_UNKNOWN      = 0xFF
 170 };
 171
 172 #define ASICREV_IS_CARRIZO(eChipRev) \
 173         ((eChipRev >= CARRIZO_A0) && (eChipRev < STONEY_A0))
 174
 175 #define ASICREV_IS_STONEY(eChipRev) \
 176         ((eChipRev >= STONEY_A0) && (eChipRev < CZ_UNKNOWN))
 177
 178 /* AI specific rev IDs */
 179 enum {
 180    AI_VEGA10_P_A0 = 0x01,
 181
 182    AI_UNKNOWN        = 0xFF
 183 };
 184
 185 #define ASICREV_IS_VEGA10_P(eChipRev) \
 186    ((eChipRev) >= AI_VEGA10_P_A0 && (eChipRev) < AI_UNKNOWN)
 187
 188 #endif /* AMDGPU_ID_H */