4 * Copyright (c) 2019 Valve Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * This file was generated by aco_builder_h.py
32 #include "util/u_math.h"
33 #include "util/bitscan.h"
37 _dpp_quad_perm = 0x000,
45 dpp_row_mirror = 0x140,
46 dpp_row_half_mirror = 0x141,
47 dpp_row_bcast15 = 0x142,
48 dpp_row_bcast31 = 0x143
52 dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
54 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
55 return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
59 dpp_row_sl(unsigned amount)
61 assert(amount > 0 && amount < 16);
62 return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
66 dpp_row_sr(unsigned amount)
68 assert(amount > 0 && amount < 16);
69 return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
73 ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
75 assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
76 return and_mask | (or_mask << 5) | (xor_mask << 10);
79 aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
86 Result(Instruction *instr) : instr(instr) {}
88 operator Instruction *() const {
92 operator Temp() const {
93 return instr->definitions[0].getTemp();
96 operator Operand() const {
97 return Operand((Temp)*this);
100 Definition& def(unsigned index) const {
101 return instr->definitions[index];
104 aco_ptr<Instruction> get_ptr() const {
105 return aco_ptr<Instruction>(instr);
111 Op(Temp tmp) : op(tmp) {}
112 Op(Operand op_) : op(op_) {}
113 Op(Result res) : op((Temp)res) {}
119 bool forwards; //when use_iterator == true
120 bool start; //when use_iterator == false
122 std::vector<aco_ptr<Instruction>> *instructions;
123 std::vector<aco_ptr<Instruction>>::iterator it;
125 Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), instructions(NULL) {}
126 Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), instructions(&block->instructions) {}
127 Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), instructions(instrs) {}
129 void moveEnd(Block *block) {
130 instructions = &block->instructions;
134 use_iterator = false;
139 void reset(Block *block) {
140 use_iterator = false;
142 instructions = &block->instructions;
145 void reset(std::vector<aco_ptr<Instruction>> *instrs) {
146 use_iterator = false;
148 instructions = instrs;
151 Result insert(aco_ptr<Instruction> instr) {
152 Instruction *instr_ptr = instr.get();
155 it = instructions->emplace(it, std::move(instr));
159 instructions->emplace_back(std::move(instr));
161 instructions->emplace(instructions->begin(), std::move(instr));
164 return Result(instr_ptr);
167 Result insert(Instruction* instr) {
170 it = instructions->emplace(it, aco_ptr<Instruction>(instr));
174 instructions->emplace_back(aco_ptr<Instruction>(instr));
176 instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
179 return Result(instr);
182 Temp tmp(RegClass rc) {
183 return (Temp){program->allocateId(), rc};
186 Temp tmp(RegType type, unsigned size) {
187 return (Temp){program->allocateId(), RegClass(type, size)};
190 Definition def(RegClass rc) {
191 return Definition((Temp){program->allocateId(), rc});
194 Definition def(RegType type, unsigned size) {
195 return Definition((Temp){program->allocateId(), RegClass(type, size)});
198 Definition def(RegClass rc, PhysReg reg) {
199 return Definition(program->allocateId(), reg, rc);
202 % for fixed in ['m0', 'vcc', 'exec', 'scc']:
203 Operand ${fixed}(Temp tmp) {
205 op.setFixed(aco::${fixed});
209 Definition ${fixed}(Definition def) {
210 def.setFixed(aco::${fixed});
214 Definition hint_${fixed}(Definition def) {
215 def.setHint(aco::${fixed});
220 /* hand-written helpers */
221 Temp as_uniform(Op op)
223 assert(op.op.isTemp());
224 if (op.op.getTemp().type() == RegType::vgpr)
225 return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
227 return op.op.getTemp();
230 Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false)
232 assert(tmp.type() == RegType::vgpr);
234 return vop1(aco_opcode::v_mov_b32, dst, Operand(0u));
235 } else if (imm == 1) {
236 return copy(dst, Operand(tmp));
237 } else if (util_is_power_of_two_or_zero(imm)) {
238 return vop2(aco_opcode::v_lshlrev_b32, dst, Operand((uint32_t)ffs(imm) - 1u), tmp);
240 return vop2(aco_opcode::v_mul_u32_u24, dst, Operand(imm), tmp);
242 Temp imm_tmp = copy(def(v1), Operand(imm));
243 return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
247 Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
249 return v_mul_imm(dst, tmp, imm, true);
252 Result copy(Definition dst, Op op_) {
254 if (dst.regClass() == s1 && op.size() == 1 && op.isLiteral()) {
255 uint32_t imm = op.constantValue();
256 if (imm >= 0xffff8000 || imm <= 0x7fff) {
257 return sopk(aco_opcode::s_movk_i32, dst, imm & 0xFFFFu);
258 } else if (util_bitreverse(imm) <= 64 || util_bitreverse(imm) >= 0xFFFFFFF0) {
259 uint32_t rev = util_bitreverse(imm);
260 return dst.regClass() == v1 ?
261 vop1(aco_opcode::v_bfrev_b32, dst, Operand(rev)) :
262 sop1(aco_opcode::s_brev_b32, dst, Operand(rev));
263 } else if (imm != 0) {
264 unsigned start = (ffs(imm) - 1) & 0x1f;
265 unsigned size = util_bitcount(imm) & 0x1f;
266 if ((((1u << size) - 1u) << start) == imm)
267 return sop2(aco_opcode::s_bfm_b32, dst, Operand(size), Operand(start));
271 if (dst.regClass() == s2) {
272 return sop1(aco_opcode::s_mov_b64, dst, op);
273 } else if (op.size() > 1) {
274 return pseudo(aco_opcode::p_create_vector, dst, op);
275 } else if (dst.regClass() == v1 || dst.regClass() == v1.as_linear()) {
276 return vop1(aco_opcode::v_mov_b32, dst, op);
278 assert(dst.regClass() == s1);
279 return sop1(aco_opcode::s_mov_b32, dst, op);
283 Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2))) {
284 if (!b.op.isTemp() || b.op.regClass().type() != RegType::vgpr)
286 assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
288 if (!carry_in.op.isUndefined())
289 return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(s2)), a, b, carry_in);
290 else if (program->chip_class < GFX9 || carry_out)
291 return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(s2)), a, b);
293 return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
296 Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
298 if (!borrow.op.isUndefined() || program->chip_class < GFX9)
301 bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
304 assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
310 if (borrow.op.isUndefined())
311 op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
313 op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
315 op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
318 int num_ops = borrow.op.isUndefined() ? 2 : 3;
319 int num_defs = carry_out ? 2 : 1;
320 aco_ptr<Instruction> sub{create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs)};
321 sub->operands[0] = a.op;
322 sub->operands[1] = b.op;
323 if (!borrow.op.isUndefined())
324 sub->operands[2] = borrow.op;
325 sub->definitions[0] = dst;
327 sub->definitions[1] = Definition(carry);
328 sub->definitions[1].setHint(aco::vcc);
330 return insert(std::move(sub));
334 formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(5))) + [(8, 1), (1, 8)]),
335 ("sop1", [Format.SOP1], 'SOP1_instruction', [(1, 1), (2, 1), (3, 2)]),
336 ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])),
337 ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])),
338 ("sopp", [Format.SOPP], 'SOPP_instruction', [(0, 0), (0, 1)]),
339 ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]),
340 ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]),
341 ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]),
342 ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]),
343 ("mimg", [Format.MIMG], 'MIMG_instruction', [(0, 4), (1, 3), (0, 3), (1, 2)]), #TODO(pendingchaos): less shapes?
344 ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]),
345 ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([0], [0, 1])),
346 ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
347 ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]),
348 ("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
349 ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
350 ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
351 ("vop3", [Format.VOP3A], 'VOP3A_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]),
352 ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]),
353 ("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]),
354 ("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])),
355 ("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])),
356 ("vop1_e64", [Format.VOP1, Format.VOP3A], 'VOP3A_instruction', itertools.product([1], [1])),
357 ("vop2_e64", [Format.VOP2, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2, 3])),
358 ("vopc_e64", [Format.VOPC, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2])),
359 ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]),
360 ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])]
362 % for name, formats, struct, shapes in formats:
363 % for num_definitions, num_operands in shapes:
365 args = ['aco_opcode opcode']
366 for i in range(num_definitions):
367 args.append('Definition def%d' % i)
368 for i in range(num_operands):
369 args.append('Op op%d' % i)
371 args += f.get_builder_field_decls()
374 Result ${name}(${', '.join(args)})
376 ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
377 % for i in range(num_definitions):
378 instr->definitions[${i}] = def${i};
380 % for i in range(num_operands):
381 instr->operands[${i}] = op${i}.op;
384 % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
385 instr->${dest} = ${field_name};
388 return insert(instr);
395 #endif /* _ACO_BUILDER_ */"""
397 from aco_opcodes
import opcodes
, Format
398 from mako
.template
import Template
400 print(Template(template
).render(opcodes
=opcodes
, Format
=Format
))