src/amd/compiler/aco_builder_h.py

   1
   2 template = """\
   3 /*
   4  * Copyright (c) 2019 Valve Corporation
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  *
  25  * This file was generated by aco_builder_h.py
  26  */
  27
  28 #ifndef _ACO_BUILDER_
  29 #define _ACO_BUILDER_
  30
  31 #include "aco_ir.h"
  32 #include "util/u_math.h"
  33 #include "util/bitscan.h"
  34
  35 namespace aco {
  36 enum dpp_ctrl {
  37     _dpp_quad_perm = 0x000,
  38     _dpp_row_sl = 0x100,
  39     _dpp_row_sr = 0x110,
  40     _dpp_row_rr = 0x120,
  41     dpp_wf_sl1 = 0x130,
  42     dpp_wf_rl1 = 0x134,
  43     dpp_wf_sr1 = 0x138,
  44     dpp_wf_rr1 = 0x13C,
  45     dpp_row_mirror = 0x140,
  46     dpp_row_half_mirror = 0x141,
  47     dpp_row_bcast15 = 0x142,
  48     dpp_row_bcast31 = 0x143
  49 };
  50
  51 inline dpp_ctrl
  52 dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
  53 {
  54     assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
  55     return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
  56 }
  57
  58 inline dpp_ctrl
  59 dpp_row_sl(unsigned amount)
  60 {
  61     assert(amount > 0 && amount < 16);
  62     return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
  63 }
  64
  65 inline dpp_ctrl
  66 dpp_row_sr(unsigned amount)
  67 {
  68     assert(amount > 0 && amount < 16);
  69     return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
  70 }
  71
  72 inline dpp_ctrl
  73 dpp_row_rr(unsigned amount)
  74 {
  75     assert(amount > 0 && amount < 16);
  76     return (dpp_ctrl)(((unsigned) _dpp_row_rr) | amount);
  77 }
  78
  79 inline unsigned
  80 ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
  81 {
  82     assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
  83     return and_mask | (or_mask << 5) | (xor_mask << 10);
  84 }
  85
  86 aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
  87
  88 extern uint8_t int8_mul_table[512];
  89
  90 enum sendmsg {
  91    sendmsg_none = 0,
  92    _sendmsg_gs = 2,
  93    _sendmsg_gs_done = 3,
  94    sendmsg_save_wave = 4,
  95    sendmsg_stall_wave_gen = 5,
  96    sendmsg_halt_waves = 6,
  97    sendmsg_ordered_ps_done = 7,
  98    sendmsg_early_prim_dealloc = 8,
  99    sendmsg_gs_alloc_req = 9,
 100    sendmsg_id_mask = 0xf,
 101 };
 102
 103 inline sendmsg
 104 sendmsg_gs(bool cut, bool emit, unsigned stream)
 105 {
 106     assert(stream < 4);
 107     return (sendmsg)((unsigned)_sendmsg_gs | (cut << 4) | (emit << 5) | (stream << 8));
 108 }
 109
 110 inline sendmsg
 111 sendmsg_gs_done(bool cut, bool emit, unsigned stream)
 112 {
 113     assert(stream < 4);
 114     return (sendmsg)((unsigned)_sendmsg_gs_done | (cut << 4) | (emit << 5) | (stream << 8));
 115 }
 116
 117 class Builder {
 118 public:
 119    struct Result {
 120       Instruction *instr;
 121
 122       Result(Instruction *instr) : instr(instr) {}
 123
 124       operator Instruction *() const {
 125          return instr;
 126       }
 127
 128       operator Temp() const {
 129          return instr->definitions[0].getTemp();
 130       }
 131
 132       operator Operand() const {
 133          return Operand((Temp)*this);
 134       }
 135
 136       Definition& def(unsigned index) const {
 137          return instr->definitions[index];
 138       }
 139
 140       aco_ptr<Instruction> get_ptr() const {
 141         return aco_ptr<Instruction>(instr);
 142       }
 143    };
 144
 145    struct Op {
 146       Operand op;
 147       Op(Temp tmp) : op(tmp) {}
 148       Op(Operand op_) : op(op_) {}
 149       Op(Result res) : op((Temp)res) {}
 150    };
 151
 152    enum WaveSpecificOpcode {
 153       s_cselect = (unsigned) aco_opcode::s_cselect_b64,
 154       s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64,
 155       s_and = (unsigned) aco_opcode::s_and_b64,
 156       s_andn2 = (unsigned) aco_opcode::s_andn2_b64,
 157       s_or = (unsigned) aco_opcode::s_or_b64,
 158       s_orn2 = (unsigned) aco_opcode::s_orn2_b64,
 159       s_not = (unsigned) aco_opcode::s_not_b64,
 160       s_mov = (unsigned) aco_opcode::s_mov_b64,
 161       s_wqm = (unsigned) aco_opcode::s_wqm_b64,
 162       s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64,
 163       s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64,
 164       s_xnor = (unsigned) aco_opcode::s_xnor_b64,
 165       s_xor = (unsigned) aco_opcode::s_xor_b64,
 166       s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64,
 167       s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64,
 168       s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64,
 169    };
 170
 171    Program *program;
 172    bool use_iterator;
 173    bool start; // only when use_iterator == false
 174    RegClass lm;
 175
 176    std::vector<aco_ptr<Instruction>> *instructions;
 177    std::vector<aco_ptr<Instruction>>::iterator it;
 178    bool is_precise = false;
 179
 180    Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm->lane_mask), instructions(NULL) {}
 181    Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {}
 182    Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {}
 183
 184    Builder precise() const {
 185       Builder res = *this;
 186       res.is_precise = true;
 187       return res;
 188    };
 189
 190    void moveEnd(Block *block) {
 191       instructions = &block->instructions;
 192    }
 193
 194    void reset() {
 195       use_iterator = false;
 196       start = false;
 197       instructions = NULL;
 198    }
 199
 200    void reset(Block *block) {
 201       use_iterator = false;
 202       start = false;
 203       instructions = &block->instructions;
 204    }
 205
 206    void reset(std::vector<aco_ptr<Instruction>> *instrs) {
 207       use_iterator = false;
 208       start = false;
 209       instructions = instrs;
 210    }
 211
 212    void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) {
 213       use_iterator = true;
 214       start = false;
 215       instructions = instrs;
 216       it = instr_it;
 217    }
 218
 219    Result insert(aco_ptr<Instruction> instr) {
 220       Instruction *instr_ptr = instr.get();
 221       if (instructions) {
 222          if (use_iterator) {
 223             it = instructions->emplace(it, std::move(instr));
 224             it = std::next(it);
 225          } else if (!start) {
 226             instructions->emplace_back(std::move(instr));
 227          } else {
 228             instructions->emplace(instructions->begin(), std::move(instr));
 229          }
 230       }
 231       return Result(instr_ptr);
 232    }
 233
 234    Result insert(Instruction* instr) {
 235       if (instructions) {
 236          if (use_iterator) {
 237             it = instructions->emplace(it, aco_ptr<Instruction>(instr));
 238             it = std::next(it);
 239          } else if (!start) {
 240             instructions->emplace_back(aco_ptr<Instruction>(instr));
 241          } else {
 242             instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
 243          }
 244       }
 245       return Result(instr);
 246    }
 247
 248    Temp tmp(RegClass rc) {
 249       return (Temp){program->allocateId(), rc};
 250    }
 251
 252    Temp tmp(RegType type, unsigned size) {
 253       return (Temp){program->allocateId(), RegClass(type, size)};
 254    }
 255
 256    Definition def(RegClass rc) {
 257       return Definition((Temp){program->allocateId(), rc});
 258    }
 259
 260    Definition def(RegType type, unsigned size) {
 261       return Definition((Temp){program->allocateId(), RegClass(type, size)});
 262    }
 263
 264    Definition def(RegClass rc, PhysReg reg) {
 265       return Definition(program->allocateId(), reg, rc);
 266    }
 267
 268    inline aco_opcode w64or32(WaveSpecificOpcode opcode) const {
 269       if (program->wave_size == 64)
 270          return (aco_opcode) opcode;
 271
 272       switch (opcode) {
 273       case s_cselect:
 274          return aco_opcode::s_cselect_b32;
 275       case s_cmp_lg:
 276          return aco_opcode::s_cmp_lg_u32;
 277       case s_and:
 278          return aco_opcode::s_and_b32;
 279       case s_andn2:
 280          return aco_opcode::s_andn2_b32;
 281       case s_or:
 282          return aco_opcode::s_or_b32;
 283       case s_orn2:
 284          return aco_opcode::s_orn2_b32;
 285       case s_not:
 286          return aco_opcode::s_not_b32;
 287       case s_mov:
 288          return aco_opcode::s_mov_b32;
 289       case s_wqm:
 290          return aco_opcode::s_wqm_b32;
 291       case s_and_saveexec:
 292          return aco_opcode::s_and_saveexec_b32;
 293       case s_or_saveexec:
 294          return aco_opcode::s_or_saveexec_b32;
 295       case s_xnor:
 296          return aco_opcode::s_xnor_b32;
 297       case s_xor:
 298          return aco_opcode::s_xor_b32;
 299       case s_bcnt1_i32:
 300          return aco_opcode::s_bcnt1_i32_b32;
 301       case s_bitcmp1:
 302          return aco_opcode::s_bitcmp1_b32;
 303       case s_ff1_i32:
 304          return aco_opcode::s_ff1_i32_b32;
 305       default:
 306          unreachable("Unsupported wave specific opcode.");
 307       }
 308    }
 309
 310 % for fixed in ['m0', 'vcc', 'exec', 'scc']:
 311    Operand ${fixed}(Temp tmp) {
 312        % if fixed == 'vcc' or fixed == 'exec':
 313           assert(tmp.regClass() == lm);
 314        % endif
 315        Operand op(tmp);
 316        op.setFixed(aco::${fixed});
 317        return op;
 318    }
 319
 320    Definition ${fixed}(Definition def) {
 321        % if fixed == 'vcc' or fixed == 'exec':
 322           assert(def.regClass() == lm);
 323        % endif
 324        def.setFixed(aco::${fixed});
 325        return def;
 326    }
 327
 328    Definition hint_${fixed}(Definition def) {
 329        % if fixed == 'vcc' or fixed == 'exec':
 330           assert(def.regClass() == lm);
 331        % endif
 332        def.setHint(aco::${fixed});
 333        return def;
 334    }
 335
 336 % endfor
 337    /* hand-written helpers */
 338    Temp as_uniform(Op op)
 339    {
 340       assert(op.op.isTemp());
 341       if (op.op.getTemp().type() == RegType::vgpr)
 342          return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
 343       else
 344          return op.op.getTemp();
 345    }
 346
 347    Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false)
 348    {
 349       assert(tmp.type() == RegType::vgpr);
 350       if (imm == 0) {
 351          return vop1(aco_opcode::v_mov_b32, dst, Operand(0u));
 352       } else if (imm == 1) {
 353          return copy(dst, Operand(tmp));
 354       } else if (util_is_power_of_two_or_zero(imm)) {
 355          return vop2(aco_opcode::v_lshlrev_b32, dst, Operand((uint32_t)ffs(imm) - 1u), tmp);
 356       } else if (bits24) {
 357         return vop2(aco_opcode::v_mul_u32_u24, dst, Operand(imm), tmp);
 358       } else {
 359         Temp imm_tmp = copy(def(v1), Operand(imm));
 360         return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
 361       }
 362    }
 363
 364    Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
 365    {
 366       return v_mul_imm(dst, tmp, imm, true);
 367    }
 368
 369    Result copy(Definition dst, Op op_) {
 370       Operand op = op_.op;
 371       assert(op.bytes() == dst.bytes());
 372       if (dst.regClass() == s1 && op.size() == 1 && op.isLiteral()) {
 373          uint32_t imm = op.constantValue();
 374          if (imm == 0x3e22f983) {
 375             if (program->chip_class >= GFX8)
 376                op.setFixed(PhysReg{248}); /* it can be an inline constant on GFX8+ */
 377          } else if (imm >= 0xffff8000 || imm <= 0x7fff) {
 378             return sopk(aco_opcode::s_movk_i32, dst, imm & 0xFFFFu);
 379          } else if (util_bitreverse(imm) <= 64 || util_bitreverse(imm) >= 0xFFFFFFF0) {
 380             uint32_t rev = util_bitreverse(imm);
 381             return dst.regClass() == v1 ?
 382                    vop1(aco_opcode::v_bfrev_b32, dst, Operand(rev)) :
 383                    sop1(aco_opcode::s_brev_b32, dst, Operand(rev));
 384          } else if (imm != 0) {
 385             unsigned start = (ffs(imm) - 1) & 0x1f;
 386             unsigned size = util_bitcount(imm) & 0x1f;
 387             if ((((1u << size) - 1u) << start) == imm)
 388                 return sop2(aco_opcode::s_bfm_b32, dst, Operand(size), Operand(start));
 389          }
 390       }
 391
 392       if (dst.regClass() == s1) {
 393         return sop1(aco_opcode::s_mov_b32, dst, op);
 394       } else if (dst.regClass() == s2) {
 395         return sop1(aco_opcode::s_mov_b64, dst, op);
 396       } else if (dst.regClass() == v1 || dst.regClass() == v1.as_linear()) {
 397         return vop1(aco_opcode::v_mov_b32, dst, op);
 398       } else if (op.bytes() > 2) {
 399          return pseudo(aco_opcode::p_create_vector, dst, op);
 400       } else if (op.bytes() == 1 && op.isConstant()) {
 401         uint8_t val = op.constantValue();
 402         Operand op32((uint32_t)val | (val & 0x80u ? 0xffffff00u : 0u));
 403         aco_ptr<SDWA_instruction> sdwa;
 404         if (op32.isLiteral()) {
 405             sdwa.reset(create_instruction<SDWA_instruction>(aco_opcode::v_mul_u32_u24, asSDWA(Format::VOP2), 2, 1));
 406             uint32_t a = (uint32_t)int8_mul_table[val * 2];
 407             uint32_t b = (uint32_t)int8_mul_table[val * 2 + 1];
 408             sdwa->operands[0] = Operand(a | (a & 0x80u ? 0xffffff00u : 0x0u));
 409             sdwa->operands[1] = Operand(b | (b & 0x80u ? 0xffffff00u : 0x0u));
 410         } else {
 411             sdwa.reset(create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1));
 412             sdwa->operands[0] = op32;
 413         }
 414         sdwa->definitions[0] = dst;
 415         sdwa->sel[0] = sdwa_udword;
 416         sdwa->sel[1] = sdwa_udword;
 417         sdwa->dst_sel = sdwa_ubyte;
 418         sdwa->dst_preserve = true;
 419         return insert(std::move(sdwa));
 420       } else if (op.bytes() == 2 && op.isConstant() && !op.isLiteral()) {
 421         aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_add_f16, asSDWA(Format::VOP2), 2, 1)};
 422         sdwa->operands[0] = op;
 423         sdwa->operands[1] = Operand(0u);
 424         sdwa->definitions[0] = dst;
 425         sdwa->sel[0] = sdwa_uword;
 426         sdwa->sel[1] = sdwa_udword;
 427         sdwa->dst_sel = dst.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 428         sdwa->dst_preserve = true;
 429         return insert(std::move(sdwa));
 430       } else if (dst.regClass().is_subdword()) {
 431         if (program->chip_class >= GFX8) {
 432             aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)};
 433             sdwa->operands[0] = op;
 434             sdwa->definitions[0] = dst;
 435             sdwa->sel[0] = op.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 436             sdwa->dst_sel = dst.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 437             sdwa->dst_preserve = true;
 438             return insert(std::move(sdwa));
 439         } else {
 440             return vop1(aco_opcode::v_mov_b32, dst, op);
 441         }
 442       } else {
 443         unreachable("Unhandled case in bld.copy()");
 444       }
 445    }
 446
 447    Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) {
 448       if (!b.op.isTemp() || b.op.regClass().type() != RegType::vgpr)
 449          std::swap(a, b);
 450       assert((post_ra || b.op.hasRegClass()) && b.op.regClass().type() == RegType::vgpr);
 451
 452       if (!carry_in.op.isUndefined())
 453          return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(lm)), a, b, carry_in);
 454       else if (program->chip_class >= GFX10 && carry_out)
 455          return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(lm), a, b);
 456       else if (program->chip_class < GFX9 || carry_out)
 457          return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(lm)), a, b);
 458       else
 459          return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
 460    }
 461
 462    Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
 463    {
 464       if (!borrow.op.isUndefined() || program->chip_class < GFX9)
 465          carry_out = true;
 466
 467       bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
 468       if (reverse)
 469          std::swap(a, b);
 470       assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
 471
 472       aco_opcode op;
 473       Temp carry;
 474       if (carry_out) {
 475          carry = tmp(s2);
 476          if (borrow.op.isUndefined())
 477             op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
 478          else
 479             op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
 480       } else {
 481          op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
 482       }
 483       bool vop3 = false;
 484       if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) {
 485         vop3 = true;
 486         op = aco_opcode::v_subrev_co_u32_e64;
 487       } else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) {
 488         vop3 = true;
 489         op = aco_opcode::v_sub_co_u32_e64;
 490       }
 491
 492       int num_ops = borrow.op.isUndefined() ? 2 : 3;
 493       int num_defs = carry_out ? 2 : 1;
 494       aco_ptr<Instruction> sub;
 495       if (vop3)
 496         sub.reset(create_instruction<VOP3A_instruction>(op, Format::VOP3B, num_ops, num_defs));
 497       else
 498         sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs));
 499       sub->operands[0] = a.op;
 500       sub->operands[1] = b.op;
 501       if (!borrow.op.isUndefined())
 502          sub->operands[2] = borrow.op;
 503       sub->definitions[0] = dst;
 504       if (carry_out) {
 505          sub->definitions[1] = Definition(carry);
 506          sub->definitions[1].setHint(aco::vcc);
 507       }
 508       return insert(std::move(sub));
 509    }
 510
 511    Result readlane(Definition dst, Op vsrc, Op lane)
 512    {
 513       if (program->chip_class >= GFX8)
 514          return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane);
 515       else
 516          return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane);
 517    }
 518    Result writelane(Definition dst, Op val, Op lane, Op vsrc) {
 519       if (program->chip_class >= GFX8)
 520          return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc);
 521       else
 522          return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc);
 523    }
 524 <%
 525 import itertools
 526 formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(5))) + [(8, 1), (1, 8)]),
 527            ("sop1", [Format.SOP1], 'SOP1_instruction', [(1, 1), (2, 1), (3, 2)]),
 528            ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])),
 529            ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])),
 530            ("sopp", [Format.SOPP], 'SOPP_instruction', [(0, 0), (0, 1)]),
 531            ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]),
 532            ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]),
 533            ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]),
 534            ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]),
 535            ("mtbuf", [Format.MTBUF], 'MTBUF_instruction', [(0, 4), (1, 3)]),
 536            ("mimg", [Format.MIMG], 'MIMG_instruction', [(0, 3), (1, 3)]),
 537            ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]),
 538            ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([0], [0, 1])),
 539            ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
 540            ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]),
 541            ("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
 542            ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
 543            ("vop2_sdwa", [Format.VOP2, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2, 3])),
 544            ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
 545            ("vop3", [Format.VOP3A], 'VOP3A_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]),
 546            ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]),
 547            ("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]),
 548            ("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])),
 549            ("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])),
 550            ("vop1_e64", [Format.VOP1, Format.VOP3A], 'VOP3A_instruction', itertools.product([1], [1])),
 551            ("vop2_e64", [Format.VOP2, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2, 3])),
 552            ("vopc_e64", [Format.VOPC, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2])),
 553            ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]),
 554            ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])]
 555 %>\\
 556 % for name, formats, struct, shapes in formats:
 557     % for num_definitions, num_operands in shapes:
 558         <%
 559         args = ['aco_opcode opcode']
 560         for i in range(num_definitions):
 561             args.append('Definition def%d' % i)
 562         for i in range(num_operands):
 563             args.append('Op op%d' % i)
 564         for f in formats:
 565             args += f.get_builder_field_decls()
 566         %>\\
 567
 568    Result ${name}(${', '.join(args)})
 569    {
 570       ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
 571         % for i in range(num_definitions):
 572             instr->definitions[${i}] = def${i};
 573             instr->definitions[${i}].setPrecise(is_precise);
 574         % endfor
 575         % for i in range(num_operands):
 576             instr->operands[${i}] = op${i}.op;
 577         % endfor
 578         % for f in formats:
 579             % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
 580       instr->${dest} = ${field_name};
 581             % endfor
 582             ${f.get_builder_initialization(num_operands)}
 583         % endfor
 584       return insert(instr);
 585    }
 586
 587     % if name == 'sop1' or name == 'sop2' or name == 'sopc':
 588         <%
 589         args[0] = 'WaveSpecificOpcode opcode'
 590         params = []
 591         for i in range(num_definitions):
 592             params.append('def%d' % i)
 593         for i in range(num_operands):
 594             params.append('op%d' % i)
 595         %>\\
 596
 597    inline Result ${name}(${', '.join(args)})
 598    {
 599        return ${name}(w64or32(opcode), ${', '.join(params)});
 600    }
 601
 602     % endif
 603     % endfor
 604 % endfor
 605 };
 606
 607 }
 608 #endif /* _ACO_BUILDER_ */"""
 609
 610 from aco_opcodes import opcodes, Format
 611 from mako.template import Template
 612
 613 print(Template(template).render(opcodes=opcodes, Format=Format))