src/amd/compiler/aco_builder_h.py

   1
   2 template = """\
   3 /*
   4  * Copyright (c) 2019 Valve Corporation
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  *
  25  * This file was generated by aco_builder_h.py
  26  */
  27
  28 #ifndef _ACO_BUILDER_
  29 #define _ACO_BUILDER_
  30
  31 #include "aco_ir.h"
  32 #include "util/u_math.h"
  33 #include "util/bitscan.h"
  34
  35 namespace aco {
  36 enum dpp_ctrl {
  37     _dpp_quad_perm = 0x000,
  38     _dpp_row_sl = 0x100,
  39     _dpp_row_sr = 0x110,
  40     _dpp_row_rr = 0x120,
  41     dpp_wf_sl1 = 0x130,
  42     dpp_wf_rl1 = 0x134,
  43     dpp_wf_sr1 = 0x138,
  44     dpp_wf_rr1 = 0x13C,
  45     dpp_row_mirror = 0x140,
  46     dpp_row_half_mirror = 0x141,
  47     dpp_row_bcast15 = 0x142,
  48     dpp_row_bcast31 = 0x143
  49 };
  50
  51 inline dpp_ctrl
  52 dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
  53 {
  54     assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
  55     return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
  56 }
  57
  58 inline dpp_ctrl
  59 dpp_row_sl(unsigned amount)
  60 {
  61     assert(amount > 0 && amount < 16);
  62     return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
  63 }
  64
  65 inline dpp_ctrl
  66 dpp_row_sr(unsigned amount)
  67 {
  68     assert(amount > 0 && amount < 16);
  69     return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
  70 }
  71
  72 inline dpp_ctrl
  73 dpp_row_rr(unsigned amount)
  74 {
  75     assert(amount > 0 && amount < 16);
  76     return (dpp_ctrl)(((unsigned) _dpp_row_rr) | amount);
  77 }
  78
  79 inline unsigned
  80 ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
  81 {
  82     assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
  83     return and_mask | (or_mask << 5) | (xor_mask << 10);
  84 }
  85
  86 aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
  87
  88 extern uint8_t int8_mul_table[512];
  89
  90 enum sendmsg {
  91    sendmsg_none = 0,
  92    _sendmsg_gs = 2,
  93    _sendmsg_gs_done = 3,
  94    sendmsg_save_wave = 4,
  95    sendmsg_stall_wave_gen = 5,
  96    sendmsg_halt_waves = 6,
  97    sendmsg_ordered_ps_done = 7,
  98    sendmsg_early_prim_dealloc = 8,
  99    sendmsg_gs_alloc_req = 9,
 100    sendmsg_id_mask = 0xf,
 101 };
 102
 103 inline sendmsg
 104 sendmsg_gs(bool cut, bool emit, unsigned stream)
 105 {
 106     assert(stream < 4);
 107     return (sendmsg)((unsigned)_sendmsg_gs | (cut << 4) | (emit << 5) | (stream << 8));
 108 }
 109
 110 inline sendmsg
 111 sendmsg_gs_done(bool cut, bool emit, unsigned stream)
 112 {
 113     assert(stream < 4);
 114     return (sendmsg)((unsigned)_sendmsg_gs_done | (cut << 4) | (emit << 5) | (stream << 8));
 115 }
 116
 117 class Builder {
 118 public:
 119    struct Result {
 120       Instruction *instr;
 121
 122       Result(Instruction *instr) : instr(instr) {}
 123
 124       operator Instruction *() const {
 125          return instr;
 126       }
 127
 128       operator Temp() const {
 129          return instr->definitions[0].getTemp();
 130       }
 131
 132       operator Operand() const {
 133          return Operand((Temp)*this);
 134       }
 135
 136       Definition& def(unsigned index) const {
 137          return instr->definitions[index];
 138       }
 139
 140       aco_ptr<Instruction> get_ptr() const {
 141         return aco_ptr<Instruction>(instr);
 142       }
 143    };
 144
 145    struct Op {
 146       Operand op;
 147       Op(Temp tmp) : op(tmp) {}
 148       Op(Operand op_) : op(op_) {}
 149       Op(Result res) : op((Temp)res) {}
 150    };
 151
 152    enum WaveSpecificOpcode {
 153       s_cselect = (unsigned) aco_opcode::s_cselect_b64,
 154       s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64,
 155       s_and = (unsigned) aco_opcode::s_and_b64,
 156       s_andn2 = (unsigned) aco_opcode::s_andn2_b64,
 157       s_or = (unsigned) aco_opcode::s_or_b64,
 158       s_orn2 = (unsigned) aco_opcode::s_orn2_b64,
 159       s_not = (unsigned) aco_opcode::s_not_b64,
 160       s_mov = (unsigned) aco_opcode::s_mov_b64,
 161       s_wqm = (unsigned) aco_opcode::s_wqm_b64,
 162       s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64,
 163       s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64,
 164       s_xnor = (unsigned) aco_opcode::s_xnor_b64,
 165       s_xor = (unsigned) aco_opcode::s_xor_b64,
 166       s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64,
 167       s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64,
 168       s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64,
 169    };
 170
 171    Program *program;
 172    bool use_iterator;
 173    bool start; // only when use_iterator == false
 174    RegClass lm;
 175
 176    std::vector<aco_ptr<Instruction>> *instructions;
 177    std::vector<aco_ptr<Instruction>>::iterator it;
 178    bool is_precise = false;
 179    bool is_nuw = false;
 180
 181    Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(NULL) {}
 182    Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {}
 183    Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {}
 184
 185    Builder precise() const {
 186       Builder res = *this;
 187       res.is_precise = true;
 188       return res;
 189    };
 190
 191    Builder nuw() const {
 192       Builder res = *this;
 193       res.is_nuw = true;
 194       return res;
 195    }
 196
 197    void moveEnd(Block *block) {
 198       instructions = &block->instructions;
 199    }
 200
 201    void reset() {
 202       use_iterator = false;
 203       start = false;
 204       instructions = NULL;
 205    }
 206
 207    void reset(Block *block) {
 208       use_iterator = false;
 209       start = false;
 210       instructions = &block->instructions;
 211    }
 212
 213    void reset(std::vector<aco_ptr<Instruction>> *instrs) {
 214       use_iterator = false;
 215       start = false;
 216       instructions = instrs;
 217    }
 218
 219    void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) {
 220       use_iterator = true;
 221       start = false;
 222       instructions = instrs;
 223       it = instr_it;
 224    }
 225
 226    Result insert(aco_ptr<Instruction> instr) {
 227       Instruction *instr_ptr = instr.get();
 228       if (instructions) {
 229          if (use_iterator) {
 230             it = instructions->emplace(it, std::move(instr));
 231             it = std::next(it);
 232          } else if (!start) {
 233             instructions->emplace_back(std::move(instr));
 234          } else {
 235             instructions->emplace(instructions->begin(), std::move(instr));
 236          }
 237       }
 238       return Result(instr_ptr);
 239    }
 240
 241    Result insert(Instruction* instr) {
 242       if (instructions) {
 243          if (use_iterator) {
 244             it = instructions->emplace(it, aco_ptr<Instruction>(instr));
 245             it = std::next(it);
 246          } else if (!start) {
 247             instructions->emplace_back(aco_ptr<Instruction>(instr));
 248          } else {
 249             instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
 250          }
 251       }
 252       return Result(instr);
 253    }
 254
 255    Temp tmp(RegClass rc) {
 256       return (Temp){program->allocateId(), rc};
 257    }
 258
 259    Temp tmp(RegType type, unsigned size) {
 260       return (Temp){program->allocateId(), RegClass(type, size)};
 261    }
 262
 263    Definition def(RegClass rc) {
 264       return Definition((Temp){program->allocateId(), rc});
 265    }
 266
 267    Definition def(RegType type, unsigned size) {
 268       return Definition((Temp){program->allocateId(), RegClass(type, size)});
 269    }
 270
 271    Definition def(RegClass rc, PhysReg reg) {
 272       return Definition(program->allocateId(), reg, rc);
 273    }
 274
 275    inline aco_opcode w64or32(WaveSpecificOpcode opcode) const {
 276       if (program->wave_size == 64)
 277          return (aco_opcode) opcode;
 278
 279       switch (opcode) {
 280       case s_cselect:
 281          return aco_opcode::s_cselect_b32;
 282       case s_cmp_lg:
 283          return aco_opcode::s_cmp_lg_u32;
 284       case s_and:
 285          return aco_opcode::s_and_b32;
 286       case s_andn2:
 287          return aco_opcode::s_andn2_b32;
 288       case s_or:
 289          return aco_opcode::s_or_b32;
 290       case s_orn2:
 291          return aco_opcode::s_orn2_b32;
 292       case s_not:
 293          return aco_opcode::s_not_b32;
 294       case s_mov:
 295          return aco_opcode::s_mov_b32;
 296       case s_wqm:
 297          return aco_opcode::s_wqm_b32;
 298       case s_and_saveexec:
 299          return aco_opcode::s_and_saveexec_b32;
 300       case s_or_saveexec:
 301          return aco_opcode::s_or_saveexec_b32;
 302       case s_xnor:
 303          return aco_opcode::s_xnor_b32;
 304       case s_xor:
 305          return aco_opcode::s_xor_b32;
 306       case s_bcnt1_i32:
 307          return aco_opcode::s_bcnt1_i32_b32;
 308       case s_bitcmp1:
 309          return aco_opcode::s_bitcmp1_b32;
 310       case s_ff1_i32:
 311          return aco_opcode::s_ff1_i32_b32;
 312       default:
 313          unreachable("Unsupported wave specific opcode.");
 314       }
 315    }
 316
 317 % for fixed in ['m0', 'vcc', 'exec', 'scc']:
 318    Operand ${fixed}(Temp tmp) {
 319        % if fixed == 'vcc' or fixed == 'exec':
 320           //vcc_hi and exec_hi can still be used in wave32
 321           assert(tmp.type() == RegType::sgpr && tmp.bytes() <= 8);
 322        % endif
 323        Operand op(tmp);
 324        op.setFixed(aco::${fixed});
 325        return op;
 326    }
 327
 328    Definition ${fixed}(Definition def) {
 329        % if fixed == 'vcc' or fixed == 'exec':
 330           //vcc_hi and exec_hi can still be used in wave32
 331           assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8);
 332        % endif
 333        def.setFixed(aco::${fixed});
 334        return def;
 335    }
 336
 337    Definition hint_${fixed}(Definition def) {
 338        % if fixed == 'vcc' or fixed == 'exec':
 339           //vcc_hi and exec_hi can still be used in wave32
 340           assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8);
 341        % endif
 342        def.setHint(aco::${fixed});
 343        return def;
 344    }
 345
 346 % endfor
 347    /* hand-written helpers */
 348    Temp as_uniform(Op op)
 349    {
 350       assert(op.op.isTemp());
 351       if (op.op.getTemp().type() == RegType::vgpr)
 352          return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
 353       else
 354          return op.op.getTemp();
 355    }
 356
 357    Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false)
 358    {
 359       assert(tmp.type() == RegType::vgpr);
 360       if (imm == 0) {
 361          return vop1(aco_opcode::v_mov_b32, dst, Operand(0u));
 362       } else if (imm == 1) {
 363          return copy(dst, Operand(tmp));
 364       } else if (util_is_power_of_two_or_zero(imm)) {
 365          return vop2(aco_opcode::v_lshlrev_b32, dst, Operand((uint32_t)ffs(imm) - 1u), tmp);
 366       } else if (bits24) {
 367         return vop2(aco_opcode::v_mul_u32_u24, dst, Operand(imm), tmp);
 368       } else {
 369         Temp imm_tmp = copy(def(v1), Operand(imm));
 370         return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
 371       }
 372    }
 373
 374    Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
 375    {
 376       return v_mul_imm(dst, tmp, imm, true);
 377    }
 378
 379    Result copy(Definition dst, Op op_) {
 380       Operand op = op_.op;
 381       assert(op.bytes() == dst.bytes());
 382       if (dst.regClass() == s1 && op.size() == 1 && op.isLiteral()) {
 383          uint32_t imm = op.constantValue();
 384          if (imm == 0x3e22f983) {
 385             if (program->chip_class >= GFX8)
 386                op.setFixed(PhysReg{248}); /* it can be an inline constant on GFX8+ */
 387          } else if (imm >= 0xffff8000 || imm <= 0x7fff) {
 388             return sopk(aco_opcode::s_movk_i32, dst, imm & 0xFFFFu);
 389          } else if (util_bitreverse(imm) <= 64 || util_bitreverse(imm) >= 0xFFFFFFF0) {
 390             uint32_t rev = util_bitreverse(imm);
 391             return dst.regClass() == v1 ?
 392                    vop1(aco_opcode::v_bfrev_b32, dst, Operand(rev)) :
 393                    sop1(aco_opcode::s_brev_b32, dst, Operand(rev));
 394          } else if (imm != 0) {
 395             unsigned start = (ffs(imm) - 1) & 0x1f;
 396             unsigned size = util_bitcount(imm) & 0x1f;
 397             if ((((1u << size) - 1u) << start) == imm)
 398                 return sop2(aco_opcode::s_bfm_b32, dst, Operand(size), Operand(start));
 399          }
 400       }
 401
 402       if (dst.regClass() == s1) {
 403         return sop1(aco_opcode::s_mov_b32, dst, op);
 404       } else if (dst.regClass() == s2) {
 405         return sop1(aco_opcode::s_mov_b64, dst, op);
 406       } else if (dst.regClass() == v1 || dst.regClass() == v1.as_linear()) {
 407         return vop1(aco_opcode::v_mov_b32, dst, op);
 408       } else if (op.bytes() > 2) {
 409          return pseudo(aco_opcode::p_create_vector, dst, op);
 410       } else if (op.bytes() == 1 && op.isConstant()) {
 411         uint8_t val = op.constantValue();
 412         Operand op32((uint32_t)val | (val & 0x80u ? 0xffffff00u : 0u));
 413         aco_ptr<SDWA_instruction> sdwa;
 414         if (op32.isLiteral()) {
 415             sdwa.reset(create_instruction<SDWA_instruction>(aco_opcode::v_mul_u32_u24, asSDWA(Format::VOP2), 2, 1));
 416             uint32_t a = (uint32_t)int8_mul_table[val * 2];
 417             uint32_t b = (uint32_t)int8_mul_table[val * 2 + 1];
 418             sdwa->operands[0] = Operand(a | (a & 0x80u ? 0xffffff00u : 0x0u));
 419             sdwa->operands[1] = Operand(b | (b & 0x80u ? 0xffffff00u : 0x0u));
 420         } else {
 421             sdwa.reset(create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1));
 422             sdwa->operands[0] = op32;
 423         }
 424         sdwa->definitions[0] = dst;
 425         sdwa->sel[0] = sdwa_udword;
 426         sdwa->sel[1] = sdwa_udword;
 427         sdwa->dst_sel = sdwa_ubyte;
 428         sdwa->dst_preserve = true;
 429         return insert(std::move(sdwa));
 430       } else if (op.bytes() == 2 && op.isConstant() && !op.isLiteral()) {
 431         aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_add_f16, asSDWA(Format::VOP2), 2, 1)};
 432         sdwa->operands[0] = op;
 433         sdwa->operands[1] = Operand(0u);
 434         sdwa->definitions[0] = dst;
 435         sdwa->sel[0] = sdwa_uword;
 436         sdwa->sel[1] = sdwa_udword;
 437         sdwa->dst_sel = dst.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 438         sdwa->dst_preserve = true;
 439         return insert(std::move(sdwa));
 440       } else if (dst.regClass().is_subdword()) {
 441         if (program->chip_class >= GFX8) {
 442             aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)};
 443             sdwa->operands[0] = op;
 444             sdwa->definitions[0] = dst;
 445             sdwa->sel[0] = op.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 446             sdwa->dst_sel = dst.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 447             sdwa->dst_preserve = true;
 448             return insert(std::move(sdwa));
 449         } else {
 450             return vop1(aco_opcode::v_mov_b32, dst, op);
 451         }
 452       } else {
 453         unreachable("Unhandled case in bld.copy()");
 454       }
 455    }
 456
 457    Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) {
 458       if (!b.op.isTemp() || b.op.regClass().type() != RegType::vgpr)
 459          std::swap(a, b);
 460       assert((post_ra || b.op.hasRegClass()) && b.op.regClass().type() == RegType::vgpr);
 461
 462       if (!carry_in.op.isUndefined())
 463          return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(lm)), a, b, carry_in);
 464       else if (program->chip_class >= GFX10 && carry_out)
 465          return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(lm), a, b);
 466       else if (program->chip_class < GFX9 || carry_out)
 467          return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(lm)), a, b);
 468       else
 469          return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
 470    }
 471
 472    Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
 473    {
 474       if (!borrow.op.isUndefined() || program->chip_class < GFX9)
 475          carry_out = true;
 476
 477       bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
 478       if (reverse)
 479          std::swap(a, b);
 480       assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
 481
 482       aco_opcode op;
 483       Temp carry;
 484       if (carry_out) {
 485          carry = tmp(s2);
 486          if (borrow.op.isUndefined())
 487             op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
 488          else
 489             op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
 490       } else {
 491          op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
 492       }
 493       bool vop3 = false;
 494       if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) {
 495         vop3 = true;
 496         op = aco_opcode::v_subrev_co_u32_e64;
 497       } else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) {
 498         vop3 = true;
 499         op = aco_opcode::v_sub_co_u32_e64;
 500       }
 501
 502       int num_ops = borrow.op.isUndefined() ? 2 : 3;
 503       int num_defs = carry_out ? 2 : 1;
 504       aco_ptr<Instruction> sub;
 505       if (vop3)
 506         sub.reset(create_instruction<VOP3A_instruction>(op, Format::VOP3B, num_ops, num_defs));
 507       else
 508         sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs));
 509       sub->operands[0] = a.op;
 510       sub->operands[1] = b.op;
 511       if (!borrow.op.isUndefined())
 512          sub->operands[2] = borrow.op;
 513       sub->definitions[0] = dst;
 514       if (carry_out) {
 515          sub->definitions[1] = Definition(carry);
 516          sub->definitions[1].setHint(aco::vcc);
 517       }
 518       return insert(std::move(sub));
 519    }
 520
 521    Result readlane(Definition dst, Op vsrc, Op lane)
 522    {
 523       if (program->chip_class >= GFX8)
 524          return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane);
 525       else
 526          return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane);
 527    }
 528    Result writelane(Definition dst, Op val, Op lane, Op vsrc) {
 529       if (program->chip_class >= GFX8)
 530          return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc);
 531       else
 532          return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc);
 533    }
 534 <%
 535 import itertools
 536 formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(5))) + [(8, 1), (1, 8)]),
 537            ("sop1", [Format.SOP1], 'SOP1_instruction', [(1, 1), (2, 1), (3, 2)]),
 538            ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])),
 539            ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])),
 540            ("sopp", [Format.SOPP], 'SOPP_instruction', [(0, 0), (0, 1)]),
 541            ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]),
 542            ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]),
 543            ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]),
 544            ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]),
 545            ("mtbuf", [Format.MTBUF], 'MTBUF_instruction', [(0, 4), (1, 3)]),
 546            ("mimg", [Format.MIMG], 'MIMG_instruction', [(0, 3), (1, 3)]),
 547            ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]),
 548            ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([0], [0, 1])),
 549            ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
 550            ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]),
 551            ("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
 552            ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
 553            ("vop2_sdwa", [Format.VOP2, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2, 3])),
 554            ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
 555            ("vop3", [Format.VOP3A], 'VOP3A_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]),
 556            ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]),
 557            ("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]),
 558            ("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])),
 559            ("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])),
 560            ("vop1_e64", [Format.VOP1, Format.VOP3A], 'VOP3A_instruction', itertools.product([1], [1])),
 561            ("vop2_e64", [Format.VOP2, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2, 3])),
 562            ("vopc_e64", [Format.VOPC, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2])),
 563            ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]),
 564            ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])]
 565 formats = [(f if len(f) == 5 else f + ('',)) for f in formats]
 566 %>\\
 567 % for name, formats, struct, shapes, extra_field_setup in formats:
 568     % for num_definitions, num_operands in shapes:
 569         <%
 570         args = ['aco_opcode opcode']
 571         for i in range(num_definitions):
 572             args.append('Definition def%d' % i)
 573         for i in range(num_operands):
 574             args.append('Op op%d' % i)
 575         for f in formats:
 576             args += f.get_builder_field_decls()
 577         %>\\
 578
 579    Result ${name}(${', '.join(args)})
 580    {
 581       ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
 582         % for i in range(num_definitions):
 583             instr->definitions[${i}] = def${i};
 584             instr->definitions[${i}].setPrecise(is_precise);
 585             instr->definitions[${i}].setNUW(is_nuw);
 586         % endfor
 587         % for i in range(num_operands):
 588             instr->operands[${i}] = op${i}.op;
 589         % endfor
 590         % for f in formats:
 591             % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
 592       instr->${dest} = ${field_name};
 593             % endfor
 594             ${f.get_builder_initialization(num_operands)}
 595         % endfor
 596        ${extra_field_setup}
 597       return insert(instr);
 598    }
 599
 600     % if name == 'sop1' or name == 'sop2' or name == 'sopc':
 601         <%
 602         args[0] = 'WaveSpecificOpcode opcode'
 603         params = []
 604         for i in range(num_definitions):
 605             params.append('def%d' % i)
 606         for i in range(num_operands):
 607             params.append('op%d' % i)
 608         %>\\
 609
 610    inline Result ${name}(${', '.join(args)})
 611    {
 612        return ${name}(w64or32(opcode), ${', '.join(params)});
 613    }
 614
 615     % endif
 616     % endfor
 617 % endfor
 618 };
 619
 620 }
 621 #endif /* _ACO_BUILDER_ */"""
 622
 623 from aco_opcodes import opcodes, Format
 624 from mako.template import Template
 625
 626 print(Template(template).render(opcodes=opcodes, Format=Format))