src/amd/compiler/aco_builder_h.py

   1
   2 template = """\
   3 /*
   4  * Copyright (c) 2019 Valve Corporation
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  *
  25  * This file was generated by aco_builder_h.py
  26  */
  27
  28 #ifndef _ACO_BUILDER_
  29 #define _ACO_BUILDER_
  30
  31 #include "aco_ir.h"
  32 #include "util/u_math.h"
  33 #include "util/bitscan.h"
  34
  35 namespace aco {
  36 enum dpp_ctrl {
  37     _dpp_quad_perm = 0x000,
  38     _dpp_row_sl = 0x100,
  39     _dpp_row_sr = 0x110,
  40     _dpp_row_rr = 0x120,
  41     dpp_wf_sl1 = 0x130,
  42     dpp_wf_rl1 = 0x134,
  43     dpp_wf_sr1 = 0x138,
  44     dpp_wf_rr1 = 0x13C,
  45     dpp_row_mirror = 0x140,
  46     dpp_row_half_mirror = 0x141,
  47     dpp_row_bcast15 = 0x142,
  48     dpp_row_bcast31 = 0x143
  49 };
  50
  51 inline dpp_ctrl
  52 dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
  53 {
  54     assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
  55     return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
  56 }
  57
  58 inline dpp_ctrl
  59 dpp_row_sl(unsigned amount)
  60 {
  61     assert(amount > 0 && amount < 16);
  62     return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
  63 }
  64
  65 inline dpp_ctrl
  66 dpp_row_sr(unsigned amount)
  67 {
  68     assert(amount > 0 && amount < 16);
  69     return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
  70 }
  71
  72 inline unsigned
  73 ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
  74 {
  75     assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
  76     return and_mask | (or_mask << 5) | (xor_mask << 10);
  77 }
  78
  79 aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
  80
  81 extern uint8_t int8_mul_table[512];
  82
  83 enum sendmsg {
  84    sendmsg_none = 0,
  85    _sendmsg_gs = 2,
  86    _sendmsg_gs_done = 3,
  87    sendmsg_save_wave = 4,
  88    sendmsg_stall_wave_gen = 5,
  89    sendmsg_halt_waves = 6,
  90    sendmsg_ordered_ps_done = 7,
  91    sendmsg_early_prim_dealloc = 8,
  92    sendmsg_gs_alloc_req = 9,
  93    sendmsg_id_mask = 0xf,
  94 };
  95
  96 inline sendmsg
  97 sendmsg_gs(bool cut, bool emit, unsigned stream)
  98 {
  99     assert(stream < 4);
 100     return (sendmsg)((unsigned)_sendmsg_gs | (cut << 4) | (emit << 5) | (stream << 8));
 101 }
 102
 103 inline sendmsg
 104 sendmsg_gs_done(bool cut, bool emit, unsigned stream)
 105 {
 106     assert(stream < 4);
 107     return (sendmsg)((unsigned)_sendmsg_gs_done | (cut << 4) | (emit << 5) | (stream << 8));
 108 }
 109
 110 class Builder {
 111 public:
 112    struct Result {
 113       Instruction *instr;
 114
 115       Result(Instruction *instr) : instr(instr) {}
 116
 117       operator Instruction *() const {
 118          return instr;
 119       }
 120
 121       operator Temp() const {
 122          return instr->definitions[0].getTemp();
 123       }
 124
 125       operator Operand() const {
 126          return Operand((Temp)*this);
 127       }
 128
 129       Definition& def(unsigned index) const {
 130          return instr->definitions[index];
 131       }
 132
 133       aco_ptr<Instruction> get_ptr() const {
 134         return aco_ptr<Instruction>(instr);
 135       }
 136    };
 137
 138    struct Op {
 139       Operand op;
 140       Op(Temp tmp) : op(tmp) {}
 141       Op(Operand op_) : op(op_) {}
 142       Op(Result res) : op((Temp)res) {}
 143    };
 144
 145    enum WaveSpecificOpcode {
 146       s_cselect = (unsigned) aco_opcode::s_cselect_b64,
 147       s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64,
 148       s_and = (unsigned) aco_opcode::s_and_b64,
 149       s_andn2 = (unsigned) aco_opcode::s_andn2_b64,
 150       s_or = (unsigned) aco_opcode::s_or_b64,
 151       s_orn2 = (unsigned) aco_opcode::s_orn2_b64,
 152       s_not = (unsigned) aco_opcode::s_not_b64,
 153       s_mov = (unsigned) aco_opcode::s_mov_b64,
 154       s_wqm = (unsigned) aco_opcode::s_wqm_b64,
 155       s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64,
 156       s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64,
 157       s_xnor = (unsigned) aco_opcode::s_xnor_b64,
 158       s_xor = (unsigned) aco_opcode::s_xor_b64,
 159       s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64,
 160       s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64,
 161       s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64,
 162    };
 163
 164    Program *program;
 165    bool use_iterator;
 166    bool start; // only when use_iterator == false
 167    RegClass lm;
 168
 169    std::vector<aco_ptr<Instruction>> *instructions;
 170    std::vector<aco_ptr<Instruction>>::iterator it;
 171    bool is_precise = false;
 172
 173    Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm->lane_mask), instructions(NULL) {}
 174    Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {}
 175    Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {}
 176
 177    Builder precise() const {
 178       Builder res = *this;
 179       res.is_precise = true;
 180       return res;
 181    };
 182
 183    void moveEnd(Block *block) {
 184       instructions = &block->instructions;
 185    }
 186
 187    void reset() {
 188       use_iterator = false;
 189       start = false;
 190       instructions = NULL;
 191    }
 192
 193    void reset(Block *block) {
 194       use_iterator = false;
 195       start = false;
 196       instructions = &block->instructions;
 197    }
 198
 199    void reset(std::vector<aco_ptr<Instruction>> *instrs) {
 200       use_iterator = false;
 201       start = false;
 202       instructions = instrs;
 203    }
 204
 205    void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) {
 206       use_iterator = true;
 207       start = false;
 208       instructions = instrs;
 209       it = instr_it;
 210    }
 211
 212    Result insert(aco_ptr<Instruction> instr) {
 213       Instruction *instr_ptr = instr.get();
 214       if (instructions) {
 215          if (use_iterator) {
 216             it = instructions->emplace(it, std::move(instr));
 217             it = std::next(it);
 218          } else if (!start) {
 219             instructions->emplace_back(std::move(instr));
 220          } else {
 221             instructions->emplace(instructions->begin(), std::move(instr));
 222          }
 223       }
 224       return Result(instr_ptr);
 225    }
 226
 227    Result insert(Instruction* instr) {
 228       if (instructions) {
 229          if (use_iterator) {
 230             it = instructions->emplace(it, aco_ptr<Instruction>(instr));
 231             it = std::next(it);
 232          } else if (!start) {
 233             instructions->emplace_back(aco_ptr<Instruction>(instr));
 234          } else {
 235             instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
 236          }
 237       }
 238       return Result(instr);
 239    }
 240
 241    Temp tmp(RegClass rc) {
 242       return (Temp){program->allocateId(), rc};
 243    }
 244
 245    Temp tmp(RegType type, unsigned size) {
 246       return (Temp){program->allocateId(), RegClass(type, size)};
 247    }
 248
 249    Definition def(RegClass rc) {
 250       return Definition((Temp){program->allocateId(), rc});
 251    }
 252
 253    Definition def(RegType type, unsigned size) {
 254       return Definition((Temp){program->allocateId(), RegClass(type, size)});
 255    }
 256
 257    Definition def(RegClass rc, PhysReg reg) {
 258       return Definition(program->allocateId(), reg, rc);
 259    }
 260
 261    inline aco_opcode w64or32(WaveSpecificOpcode opcode) const {
 262       if (program->wave_size == 64)
 263          return (aco_opcode) opcode;
 264
 265       switch (opcode) {
 266       case s_cselect:
 267          return aco_opcode::s_cselect_b32;
 268       case s_cmp_lg:
 269          return aco_opcode::s_cmp_lg_u32;
 270       case s_and:
 271          return aco_opcode::s_and_b32;
 272       case s_andn2:
 273          return aco_opcode::s_andn2_b32;
 274       case s_or:
 275          return aco_opcode::s_or_b32;
 276       case s_orn2:
 277          return aco_opcode::s_orn2_b32;
 278       case s_not:
 279          return aco_opcode::s_not_b32;
 280       case s_mov:
 281          return aco_opcode::s_mov_b32;
 282       case s_wqm:
 283          return aco_opcode::s_wqm_b32;
 284       case s_and_saveexec:
 285          return aco_opcode::s_and_saveexec_b32;
 286       case s_or_saveexec:
 287          return aco_opcode::s_or_saveexec_b32;
 288       case s_xnor:
 289          return aco_opcode::s_xnor_b32;
 290       case s_xor:
 291          return aco_opcode::s_xor_b32;
 292       case s_bcnt1_i32:
 293          return aco_opcode::s_bcnt1_i32_b32;
 294       case s_bitcmp1:
 295          return aco_opcode::s_bitcmp1_b32;
 296       case s_ff1_i32:
 297          return aco_opcode::s_ff1_i32_b32;
 298       default:
 299          unreachable("Unsupported wave specific opcode.");
 300       }
 301    }
 302
 303 % for fixed in ['m0', 'vcc', 'exec', 'scc']:
 304    Operand ${fixed}(Temp tmp) {
 305        % if fixed == 'vcc' or fixed == 'exec':
 306           assert(tmp.regClass() == lm);
 307        % endif
 308        Operand op(tmp);
 309        op.setFixed(aco::${fixed});
 310        return op;
 311    }
 312
 313    Definition ${fixed}(Definition def) {
 314        % if fixed == 'vcc' or fixed == 'exec':
 315           assert(def.regClass() == lm);
 316        % endif
 317        def.setFixed(aco::${fixed});
 318        return def;
 319    }
 320
 321    Definition hint_${fixed}(Definition def) {
 322        % if fixed == 'vcc' or fixed == 'exec':
 323           assert(def.regClass() == lm);
 324        % endif
 325        def.setHint(aco::${fixed});
 326        return def;
 327    }
 328
 329 % endfor
 330    /* hand-written helpers */
 331    Temp as_uniform(Op op)
 332    {
 333       assert(op.op.isTemp());
 334       if (op.op.getTemp().type() == RegType::vgpr)
 335          return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
 336       else
 337          return op.op.getTemp();
 338    }
 339
 340    Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false)
 341    {
 342       assert(tmp.type() == RegType::vgpr);
 343       if (imm == 0) {
 344          return vop1(aco_opcode::v_mov_b32, dst, Operand(0u));
 345       } else if (imm == 1) {
 346          return copy(dst, Operand(tmp));
 347       } else if (util_is_power_of_two_or_zero(imm)) {
 348          return vop2(aco_opcode::v_lshlrev_b32, dst, Operand((uint32_t)ffs(imm) - 1u), tmp);
 349       } else if (bits24) {
 350         return vop2(aco_opcode::v_mul_u32_u24, dst, Operand(imm), tmp);
 351       } else {
 352         Temp imm_tmp = copy(def(v1), Operand(imm));
 353         return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
 354       }
 355    }
 356
 357    Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
 358    {
 359       return v_mul_imm(dst, tmp, imm, true);
 360    }
 361
 362    Result copy(Definition dst, Op op_) {
 363       Operand op = op_.op;
 364       assert(op.bytes() == dst.bytes());
 365       if (dst.regClass() == s1 && op.size() == 1 && op.isLiteral()) {
 366          uint32_t imm = op.constantValue();
 367          if (imm == 0x3e22f983) {
 368             if (program->chip_class >= GFX8)
 369                op.setFixed(PhysReg{248}); /* it can be an inline constant on GFX8+ */
 370          } else if (imm >= 0xffff8000 || imm <= 0x7fff) {
 371             return sopk(aco_opcode::s_movk_i32, dst, imm & 0xFFFFu);
 372          } else if (util_bitreverse(imm) <= 64 || util_bitreverse(imm) >= 0xFFFFFFF0) {
 373             uint32_t rev = util_bitreverse(imm);
 374             return dst.regClass() == v1 ?
 375                    vop1(aco_opcode::v_bfrev_b32, dst, Operand(rev)) :
 376                    sop1(aco_opcode::s_brev_b32, dst, Operand(rev));
 377          } else if (imm != 0) {
 378             unsigned start = (ffs(imm) - 1) & 0x1f;
 379             unsigned size = util_bitcount(imm) & 0x1f;
 380             if ((((1u << size) - 1u) << start) == imm)
 381                 return sop2(aco_opcode::s_bfm_b32, dst, Operand(size), Operand(start));
 382          }
 383       }
 384
 385       if (dst.regClass() == s1) {
 386         return sop1(aco_opcode::s_mov_b32, dst, op);
 387       } else if (dst.regClass() == s2) {
 388         return sop1(aco_opcode::s_mov_b64, dst, op);
 389       } else if (dst.regClass() == v1 || dst.regClass() == v1.as_linear()) {
 390         return vop1(aco_opcode::v_mov_b32, dst, op);
 391       } else if (op.bytes() > 2) {
 392          return pseudo(aco_opcode::p_create_vector, dst, op);
 393       } else if (op.bytes() == 1 && op.isConstant()) {
 394         uint8_t val = op.constantValue();
 395         Operand op32((uint32_t)val | (val & 0x80u ? 0xffffff00u : 0u));
 396         aco_ptr<SDWA_instruction> sdwa;
 397         if (op32.isLiteral()) {
 398             sdwa.reset(create_instruction<SDWA_instruction>(aco_opcode::v_mul_u32_u24, asSDWA(Format::VOP2), 2, 1));
 399             uint32_t a = (uint32_t)int8_mul_table[val * 2];
 400             uint32_t b = (uint32_t)int8_mul_table[val * 2 + 1];
 401             sdwa->operands[0] = Operand(a | (a & 0x80u ? 0xffffff00u : 0x0u));
 402             sdwa->operands[1] = Operand(b | (b & 0x80u ? 0xffffff00u : 0x0u));
 403         } else {
 404             sdwa.reset(create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1));
 405             sdwa->operands[0] = op32;
 406         }
 407         sdwa->definitions[0] = dst;
 408         sdwa->sel[0] = sdwa_udword;
 409         sdwa->sel[1] = sdwa_udword;
 410         sdwa->dst_sel = sdwa_ubyte;
 411         sdwa->dst_preserve = true;
 412         return insert(std::move(sdwa));
 413       } else if (op.bytes() == 2 && op.isConstant() && !op.isLiteral()) {
 414         aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_add_f16, asSDWA(Format::VOP2), 2, 1)};
 415         sdwa->operands[0] = op;
 416         sdwa->operands[1] = Operand(0u);
 417         sdwa->definitions[0] = dst;
 418         sdwa->sel[0] = sdwa_uword;
 419         sdwa->sel[1] = sdwa_udword;
 420         sdwa->dst_sel = dst.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 421         sdwa->dst_preserve = true;
 422         return insert(std::move(sdwa));
 423       } else if (dst.regClass().is_subdword()) {
 424         if (program->chip_class >= GFX8) {
 425             aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)};
 426             sdwa->operands[0] = op;
 427             sdwa->definitions[0] = dst;
 428             sdwa->sel[0] = op.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 429             sdwa->dst_sel = dst.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
 430             sdwa->dst_preserve = true;
 431             return insert(std::move(sdwa));
 432         } else {
 433             return vop1(aco_opcode::v_mov_b32, dst, op);
 434         }
 435       } else {
 436         unreachable("Unhandled case in bld.copy()");
 437       }
 438    }
 439
 440    Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) {
 441       if (!b.op.isTemp() || b.op.regClass().type() != RegType::vgpr)
 442          std::swap(a, b);
 443       assert((post_ra || b.op.hasRegClass()) && b.op.regClass().type() == RegType::vgpr);
 444
 445       if (!carry_in.op.isUndefined())
 446          return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(lm)), a, b, carry_in);
 447       else if (program->chip_class >= GFX10 && carry_out)
 448          return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(lm), a, b);
 449       else if (program->chip_class < GFX9 || carry_out)
 450          return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(lm)), a, b);
 451       else
 452          return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
 453    }
 454
 455    Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
 456    {
 457       if (!borrow.op.isUndefined() || program->chip_class < GFX9)
 458          carry_out = true;
 459
 460       bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
 461       if (reverse)
 462          std::swap(a, b);
 463       assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
 464
 465       aco_opcode op;
 466       Temp carry;
 467       if (carry_out) {
 468          carry = tmp(s2);
 469          if (borrow.op.isUndefined())
 470             op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
 471          else
 472             op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
 473       } else {
 474          op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
 475       }
 476       bool vop3 = false;
 477       if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) {
 478         vop3 = true;
 479         op = aco_opcode::v_subrev_co_u32_e64;
 480       } else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) {
 481         vop3 = true;
 482         op = aco_opcode::v_sub_co_u32_e64;
 483       }
 484
 485       int num_ops = borrow.op.isUndefined() ? 2 : 3;
 486       int num_defs = carry_out ? 2 : 1;
 487       aco_ptr<Instruction> sub;
 488       if (vop3)
 489         sub.reset(create_instruction<VOP3A_instruction>(op, Format::VOP3B, num_ops, num_defs));
 490       else
 491         sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs));
 492       sub->operands[0] = a.op;
 493       sub->operands[1] = b.op;
 494       if (!borrow.op.isUndefined())
 495          sub->operands[2] = borrow.op;
 496       sub->definitions[0] = dst;
 497       if (carry_out) {
 498          sub->definitions[1] = Definition(carry);
 499          sub->definitions[1].setHint(aco::vcc);
 500       }
 501       return insert(std::move(sub));
 502    }
 503
 504    Result readlane(Definition dst, Op vsrc, Op lane)
 505    {
 506       if (program->chip_class >= GFX8)
 507          return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane);
 508       else
 509          return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane);
 510    }
 511    Result writelane(Definition dst, Op val, Op lane, Op vsrc) {
 512       if (program->chip_class >= GFX8)
 513          return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc);
 514       else
 515          return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc);
 516    }
 517 <%
 518 import itertools
 519 formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(5))) + [(8, 1), (1, 8)]),
 520            ("sop1", [Format.SOP1], 'SOP1_instruction', [(1, 1), (2, 1), (3, 2)]),
 521            ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])),
 522            ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])),
 523            ("sopp", [Format.SOPP], 'SOPP_instruction', [(0, 0), (0, 1)]),
 524            ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]),
 525            ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]),
 526            ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]),
 527            ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]),
 528            ("mtbuf", [Format.MTBUF], 'MTBUF_instruction', [(0, 4), (1, 3)]),
 529            ("mimg", [Format.MIMG], 'MIMG_instruction', [(0, 3), (1, 3)]),
 530            ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]),
 531            ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([0], [0, 1])),
 532            ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
 533            ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]),
 534            ("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
 535            ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
 536            ("vop2_sdwa", [Format.VOP2, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2, 3])),
 537            ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
 538            ("vop3", [Format.VOP3A], 'VOP3A_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]),
 539            ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]),
 540            ("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]),
 541            ("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])),
 542            ("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])),
 543            ("vop1_e64", [Format.VOP1, Format.VOP3A], 'VOP3A_instruction', itertools.product([1], [1])),
 544            ("vop2_e64", [Format.VOP2, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2, 3])),
 545            ("vopc_e64", [Format.VOPC, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2])),
 546            ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]),
 547            ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])]
 548 %>\\
 549 % for name, formats, struct, shapes in formats:
 550     % for num_definitions, num_operands in shapes:
 551         <%
 552         args = ['aco_opcode opcode']
 553         for i in range(num_definitions):
 554             args.append('Definition def%d' % i)
 555         for i in range(num_operands):
 556             args.append('Op op%d' % i)
 557         for f in formats:
 558             args += f.get_builder_field_decls()
 559         %>\\
 560
 561    Result ${name}(${', '.join(args)})
 562    {
 563       ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
 564         % for i in range(num_definitions):
 565             instr->definitions[${i}] = def${i};
 566             instr->definitions[${i}].setPrecise(is_precise);
 567         % endfor
 568         % for i in range(num_operands):
 569             instr->operands[${i}] = op${i}.op;
 570         % endfor
 571         % for f in formats:
 572             % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
 573       instr->${dest} = ${field_name};
 574             % endfor
 575             ${f.get_builder_initialization(num_operands)}
 576         % endfor
 577       return insert(instr);
 578    }
 579
 580     % if name == 'sop1' or name == 'sop2' or name == 'sopc':
 581         <%
 582         args[0] = 'WaveSpecificOpcode opcode'
 583         params = []
 584         for i in range(num_definitions):
 585             params.append('def%d' % i)
 586         for i in range(num_operands):
 587             params.append('op%d' % i)
 588         %>\\
 589
 590    inline Result ${name}(${', '.join(args)})
 591    {
 592        return ${name}(w64or32(opcode), ${', '.join(params)});
 593    }
 594
 595     % endif
 596     % endfor
 597 % endfor
 598 };
 599
 600 }
 601 #endif /* _ACO_BUILDER_ */"""
 602
 603 from aco_opcodes import opcodes, Format
 604 from mako.template import Template
 605
 606 print(Template(template).render(opcodes=opcodes, Format=Format))