4 * Copyright (c) 2019 Valve Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * This file was generated by aco_builder_h.py
32 #include "util/u_math.h"
33 #include "util/bitscan.h"
37 _dpp_quad_perm = 0x000,
45 dpp_row_mirror = 0x140,
46 dpp_row_half_mirror = 0x141,
47 dpp_row_bcast15 = 0x142,
48 dpp_row_bcast31 = 0x143
52 dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
54 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
55 return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
59 dpp_row_sl(unsigned amount)
61 assert(amount > 0 && amount < 16);
62 return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
66 dpp_row_sr(unsigned amount)
68 assert(amount > 0 && amount < 16);
69 return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
73 ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
75 assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
76 return and_mask | (or_mask << 5) | (xor_mask << 10);
79 aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
86 Result(Instruction *instr) : instr(instr) {}
88 operator Instruction *() const {
92 operator Temp() const {
93 return instr->definitions[0].getTemp();
96 operator Operand() const {
97 return Operand((Temp)*this);
100 Definition& def(unsigned index) const {
101 return instr->definitions[index];
104 aco_ptr<Instruction> get_ptr() const {
105 return aco_ptr<Instruction>(instr);
111 Op(Temp tmp) : op(tmp) {}
112 Op(Operand op_) : op(op_) {}
113 Op(Result res) : op((Temp)res) {}
116 enum WaveSpecificOpcode {
117 s_cselect = (unsigned) aco_opcode::s_cselect_b64,
118 s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64,
119 s_and = (unsigned) aco_opcode::s_and_b64,
120 s_andn2 = (unsigned) aco_opcode::s_andn2_b64,
121 s_or = (unsigned) aco_opcode::s_or_b64,
122 s_orn2 = (unsigned) aco_opcode::s_orn2_b64,
123 s_not = (unsigned) aco_opcode::s_not_b64,
124 s_mov = (unsigned) aco_opcode::s_mov_b64,
125 s_wqm = (unsigned) aco_opcode::s_wqm_b64,
126 s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64,
127 s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64,
128 s_xnor = (unsigned) aco_opcode::s_xnor_b64,
129 s_xor = (unsigned) aco_opcode::s_xor_b64,
130 s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64,
131 s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64,
132 s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64,
137 bool start; // only when use_iterator == false
140 std::vector<aco_ptr<Instruction>> *instructions;
141 std::vector<aco_ptr<Instruction>>::iterator it;
143 Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm->lane_mask), instructions(NULL) {}
144 Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {}
145 Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {}
147 void moveEnd(Block *block) {
148 instructions = &block->instructions;
152 use_iterator = false;
157 void reset(Block *block) {
158 use_iterator = false;
160 instructions = &block->instructions;
163 void reset(std::vector<aco_ptr<Instruction>> *instrs) {
164 use_iterator = false;
166 instructions = instrs;
169 void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) {
172 instructions = instrs;
176 Result insert(aco_ptr<Instruction> instr) {
177 Instruction *instr_ptr = instr.get();
180 it = instructions->emplace(it, std::move(instr));
183 instructions->emplace_back(std::move(instr));
185 instructions->emplace(instructions->begin(), std::move(instr));
188 return Result(instr_ptr);
191 Result insert(Instruction* instr) {
194 it = instructions->emplace(it, aco_ptr<Instruction>(instr));
197 instructions->emplace_back(aco_ptr<Instruction>(instr));
199 instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
202 return Result(instr);
205 Temp tmp(RegClass rc) {
206 return (Temp){program->allocateId(), rc};
209 Temp tmp(RegType type, unsigned size) {
210 return (Temp){program->allocateId(), RegClass(type, size)};
213 Definition def(RegClass rc) {
214 return Definition((Temp){program->allocateId(), rc});
217 Definition def(RegType type, unsigned size) {
218 return Definition((Temp){program->allocateId(), RegClass(type, size)});
221 Definition def(RegClass rc, PhysReg reg) {
222 return Definition(program->allocateId(), reg, rc);
225 inline aco_opcode w64or32(WaveSpecificOpcode opcode) const {
226 if (program->wave_size == 64)
227 return (aco_opcode) opcode;
231 return aco_opcode::s_cselect_b32;
233 return aco_opcode::s_cmp_lg_u32;
235 return aco_opcode::s_and_b32;
237 return aco_opcode::s_andn2_b32;
239 return aco_opcode::s_or_b32;
241 return aco_opcode::s_orn2_b32;
243 return aco_opcode::s_not_b32;
245 return aco_opcode::s_mov_b32;
247 return aco_opcode::s_wqm_b32;
249 return aco_opcode::s_and_saveexec_b32;
251 return aco_opcode::s_or_saveexec_b32;
253 return aco_opcode::s_xnor_b32;
255 return aco_opcode::s_xor_b32;
257 return aco_opcode::s_bcnt1_i32_b32;
259 return aco_opcode::s_bitcmp1_b32;
261 return aco_opcode::s_ff1_i32_b32;
263 unreachable("Unsupported wave specific opcode.");
267 % for fixed in ['m0', 'vcc', 'exec', 'scc']:
268 Operand ${fixed}(Temp tmp) {
269 % if fixed == 'vcc' or fixed == 'exec':
270 assert(tmp.regClass() == lm);
273 op.setFixed(aco::${fixed});
277 Definition ${fixed}(Definition def) {
278 % if fixed == 'vcc' or fixed == 'exec':
279 assert(def.regClass() == lm);
281 def.setFixed(aco::${fixed});
285 Definition hint_${fixed}(Definition def) {
286 % if fixed == 'vcc' or fixed == 'exec':
287 assert(def.regClass() == lm);
289 def.setHint(aco::${fixed});
294 /* hand-written helpers */
295 Temp as_uniform(Op op)
297 assert(op.op.isTemp());
298 if (op.op.getTemp().type() == RegType::vgpr)
299 return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
301 return op.op.getTemp();
304 Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false)
306 assert(tmp.type() == RegType::vgpr);
308 return vop1(aco_opcode::v_mov_b32, dst, Operand(0u));
309 } else if (imm == 1) {
310 return copy(dst, Operand(tmp));
311 } else if (util_is_power_of_two_or_zero(imm)) {
312 return vop2(aco_opcode::v_lshlrev_b32, dst, Operand((uint32_t)ffs(imm) - 1u), tmp);
314 return vop2(aco_opcode::v_mul_u32_u24, dst, Operand(imm), tmp);
316 Temp imm_tmp = copy(def(v1), Operand(imm));
317 return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
321 Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
323 return v_mul_imm(dst, tmp, imm, true);
326 Result copy(Definition dst, Op op_) {
328 if (dst.regClass() == s1 && op.size() == 1 && op.isLiteral()) {
329 uint32_t imm = op.constantValue();
330 if (imm >= 0xffff8000 || imm <= 0x7fff) {
331 return sopk(aco_opcode::s_movk_i32, dst, imm & 0xFFFFu);
332 } else if (util_bitreverse(imm) <= 64 || util_bitreverse(imm) >= 0xFFFFFFF0) {
333 uint32_t rev = util_bitreverse(imm);
334 return dst.regClass() == v1 ?
335 vop1(aco_opcode::v_bfrev_b32, dst, Operand(rev)) :
336 sop1(aco_opcode::s_brev_b32, dst, Operand(rev));
337 } else if (imm != 0) {
338 unsigned start = (ffs(imm) - 1) & 0x1f;
339 unsigned size = util_bitcount(imm) & 0x1f;
340 if ((((1u << size) - 1u) << start) == imm)
341 return sop2(aco_opcode::s_bfm_b32, dst, Operand(size), Operand(start));
345 if (dst.regClass() == s2) {
346 return sop1(aco_opcode::s_mov_b64, dst, op);
347 } else if (op.size() > 1) {
348 return pseudo(aco_opcode::p_create_vector, dst, op);
349 } else if (dst.regClass() == v1 || dst.regClass() == v1.as_linear()) {
350 return vop1(aco_opcode::v_mov_b32, dst, op);
352 assert(dst.regClass() == s1);
353 return sop1(aco_opcode::s_mov_b32, dst, op);
357 Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) {
358 if (!b.op.isTemp() || b.op.regClass().type() != RegType::vgpr)
360 assert((post_ra || b.op.hasRegClass()) && b.op.regClass().type() == RegType::vgpr);
362 if (!carry_in.op.isUndefined())
363 return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(lm)), a, b, carry_in);
364 else if (program->chip_class >= GFX10 && carry_out)
365 return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(s2), a, b);
366 else if (program->chip_class < GFX9 || carry_out)
367 return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(lm)), a, b);
369 return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
372 Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
374 if (!borrow.op.isUndefined() || program->chip_class < GFX9)
377 bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
380 assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
386 if (borrow.op.isUndefined())
387 op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
389 op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
391 op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
394 if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) {
396 op = aco_opcode::v_subrev_co_u32_e64;
397 } else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) {
399 op = aco_opcode::v_sub_co_u32_e64;
402 int num_ops = borrow.op.isUndefined() ? 2 : 3;
403 int num_defs = carry_out ? 2 : 1;
404 aco_ptr<Instruction> sub;
406 sub.reset(create_instruction<VOP3A_instruction>(op, Format::VOP3B, num_ops, num_defs));
408 sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs));
409 sub->operands[0] = a.op;
410 sub->operands[1] = b.op;
411 if (!borrow.op.isUndefined())
412 sub->operands[2] = borrow.op;
413 sub->definitions[0] = dst;
415 sub->definitions[1] = Definition(carry);
416 sub->definitions[1].setHint(aco::vcc);
418 return insert(std::move(sub));
423 formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(5))) + [(8, 1), (1, 8)]),
424 ("sop1", [Format.SOP1], 'SOP1_instruction', [(1, 1), (2, 1), (3, 2)]),
425 ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])),
426 ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])),
427 ("sopp", [Format.SOPP], 'SOPP_instruction', [(0, 0), (0, 1)]),
428 ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]),
429 ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]),
430 ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]),
431 ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]),
432 ("mimg", [Format.MIMG], 'MIMG_instruction', [(0, 4), (1, 3), (0, 3), (1, 2)]), #TODO(pendingchaos): less shapes?
433 ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]),
434 ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([0], [0, 1])),
435 ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
436 ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2), (3, 4)]),
437 ("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
438 ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
439 ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
440 ("vop3", [Format.VOP3A], 'VOP3A_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]),
441 ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]),
442 ("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]),
443 ("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])),
444 ("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])),
445 ("vop1_e64", [Format.VOP1, Format.VOP3A], 'VOP3A_instruction', itertools.product([1], [1])),
446 ("vop2_e64", [Format.VOP2, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2, 3])),
447 ("vopc_e64", [Format.VOPC, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2])),
448 ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]),
449 ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])]
451 % for name, formats, struct, shapes in formats:
452 % for num_definitions, num_operands in shapes:
454 args = ['aco_opcode opcode']
455 for i in range(num_definitions):
456 args.append('Definition def%d' % i)
457 for i in range(num_operands):
458 args.append('Op op%d' % i)
460 args += f.get_builder_field_decls()
463 Result ${name}(${', '.join(args)})
465 ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
466 % for i in range(num_definitions):
467 instr->definitions[${i}] = def${i};
469 % for i in range(num_operands):
470 instr->operands[${i}] = op${i}.op;
473 % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
474 instr->${dest} = ${field_name};
477 return insert(instr);
480 % if name == 'sop1' or name == 'sop2' or name == 'sopc':
482 args[0] = 'WaveSpecificOpcode opcode'
484 for i in range(num_definitions):
485 params.append('def%d' % i)
486 for i in range(num_operands):
487 params.append('op%d' % i)
490 inline Result ${name}(${', '.join(args)})
492 return ${name}(w64or32(opcode), ${', '.join(params)});
501 #endif /* _ACO_BUILDER_ */"""
503 from aco_opcodes
import opcodes
, Format
504 from mako
.template
import Template
506 print(Template(template
).render(opcodes
=opcodes
, Format
=Format
))