2 * Copyright © 2018 Valve Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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31 #include "vulkan/radv_shader.h"
38 * The general idea of this pass is:
39 * The CFG is traversed in reverse postorder (forward) and loops are processed
40 * several times until no progress is made.
41 * Per BB two wait_ctx is maintained: an in-context and out-context.
42 * The in-context is the joined out-contexts of the predecessors.
43 * The context contains a map: gpr -> wait_entry
44 * consisting of the information about the cnt values to be waited for.
45 * Note: After merge-nodes, it might occur that for the same register
46 * multiple cnt values are to be waited for.
48 * The values are updated according to the encountered instructions:
49 * - additional events increment the counter of waits of the same type
50 * - or erase gprs with counters higher than to be waited for.
53 // TODO: do a more clever insertion of wait_cnt (lgkm_cnt) when there is a load followed by a use of a previous load
55 /* Instructions of the same event will finish in-order except for smem
56 * and maybe flat. Instructions of different events may not finish in-order. */
57 enum wait_event
: uint16_t {
62 event_vmem_store
= 1 << 4, /* GFX10+ */
64 event_exp_pos
= 1 << 6,
65 event_exp_param
= 1 << 7,
66 event_exp_mrt_null
= 1 << 8,
67 event_gds_gpr_lock
= 1 << 9,
68 event_vmem_gpr_lock
= 1 << 10,
69 event_sendmsg
= 1 << 11,
73 enum counter_type
: uint8_t {
75 counter_lgkm
= 1 << 1,
81 static const uint16_t exp_events
= event_exp_pos
| event_exp_param
| event_exp_mrt_null
| event_gds_gpr_lock
| event_vmem_gpr_lock
;
82 static const uint16_t lgkm_events
= event_smem
| event_lds
| event_gds
| event_flat
| event_sendmsg
;
83 static const uint16_t vm_events
= event_vmem
| event_flat
;
84 static const uint16_t vs_events
= event_vmem_store
;
86 uint8_t get_counters_for_event(wait_event ev
)
96 case event_vmem_store
:
99 return counter_vm
| counter_lgkm
;
101 case event_exp_param
:
102 case event_exp_mrt_null
:
103 case event_gds_gpr_lock
:
104 case event_vmem_gpr_lock
:
111 uint16_t get_events_for_counter(counter_type ctr
)
127 static const uint8_t unset_counter
= 0xff;
135 vm(unset_counter
), exp(unset_counter
), lgkm(unset_counter
), vs(unset_counter
) {}
136 wait_imm(uint16_t vm_
, uint16_t exp_
, uint16_t lgkm_
, uint16_t vs_
) :
137 vm(vm_
), exp(exp_
), lgkm(lgkm_
), vs(vs_
) {}
139 wait_imm(enum chip_class chip
, uint16_t packed
) : vs(unset_counter
)
143 vm
|= (packed
>> 10) & 0x30;
145 exp
= (packed
>> 4) & 0x7;
147 lgkm
= (packed
>> 8) & 0xf;
149 lgkm
|= (packed
>> 8) & 0x30;
152 uint16_t pack(enum chip_class chip
) const
155 assert(exp
== unset_counter
|| exp
<= 0x7);
158 assert(lgkm
== unset_counter
|| lgkm
<= 0x3f);
159 assert(vm
== unset_counter
|| vm
<= 0x3f);
160 imm
= ((vm
& 0x30) << 10) | ((lgkm
& 0x3f) << 8) | ((exp
& 0x7) << 4) | (vm
& 0xf);
163 assert(lgkm
== unset_counter
|| lgkm
<= 0xf);
164 assert(vm
== unset_counter
|| vm
<= 0x3f);
165 imm
= ((vm
& 0x30) << 10) | ((lgkm
& 0xf) << 8) | ((exp
& 0x7) << 4) | (vm
& 0xf);
168 assert(lgkm
== unset_counter
|| lgkm
<= 0xf);
169 assert(vm
== unset_counter
|| vm
<= 0xf);
170 imm
= ((lgkm
& 0xf) << 8) | ((exp
& 0x7) << 4) | (vm
& 0xf);
173 if (chip
< GFX9
&& vm
== wait_imm::unset_counter
)
174 imm
|= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the architecture when interpreting the immediate */
175 if (chip
< GFX10
&& lgkm
== wait_imm::unset_counter
)
176 imm
|= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the architecture when interpreting the immediate */
180 bool combine(const wait_imm
& other
)
182 bool changed
= other
.vm
< vm
|| other
.exp
< exp
|| other
.lgkm
< lgkm
|| other
.vs
< vs
;
183 vm
= std::min(vm
, other
.vm
);
184 exp
= std::min(exp
, other
.exp
);
185 lgkm
= std::min(lgkm
, other
.lgkm
);
186 vs
= std::min(vs
, other
.vs
);
192 return vm
== unset_counter
&& exp
== unset_counter
&&
193 lgkm
== unset_counter
&& vs
== unset_counter
;
199 uint16_t events
; /* use wait_event notion */
200 uint8_t counters
; /* use counter_type notion */
203 bool has_vmem_nosampler
:1;
204 bool has_vmem_sampler
:1;
206 wait_entry(wait_event event
, wait_imm imm
, bool logical
, bool wait_on_read
)
207 : imm(imm
), events(event
), counters(get_counters_for_event(event
)),
208 wait_on_read(wait_on_read
), logical(logical
),
209 has_vmem_nosampler(false), has_vmem_sampler(false) {}
211 bool join(const wait_entry
& other
)
213 bool changed
= (other
.events
& ~events
) ||
214 (other
.counters
& ~counters
) ||
215 (other
.wait_on_read
&& !wait_on_read
) ||
216 (other
.has_vmem_nosampler
&& !has_vmem_nosampler
) ||
217 (other
.has_vmem_sampler
&& !has_vmem_sampler
);
218 events
|= other
.events
;
219 counters
|= other
.counters
;
220 changed
|= imm
.combine(other
.imm
);
221 wait_on_read
|= other
.wait_on_read
;
222 has_vmem_nosampler
|= other
.has_vmem_nosampler
;
223 has_vmem_sampler
|= other
.has_vmem_sampler
;
224 assert(logical
== other
.logical
);
228 void remove_counter(counter_type counter
)
230 counters
&= ~counter
;
232 if (counter
== counter_lgkm
) {
233 imm
.lgkm
= wait_imm::unset_counter
;
234 events
&= ~(event_smem
| event_lds
| event_gds
| event_sendmsg
);
237 if (counter
== counter_vm
) {
238 imm
.vm
= wait_imm::unset_counter
;
239 events
&= ~event_vmem
;
240 has_vmem_nosampler
= false;
241 has_vmem_sampler
= false;
244 if (counter
== counter_exp
) {
245 imm
.exp
= wait_imm::unset_counter
;
246 events
&= ~(event_exp_pos
| event_exp_param
| event_exp_mrt_null
| event_gds_gpr_lock
| event_vmem_gpr_lock
);
249 if (counter
== counter_vs
) {
250 imm
.vs
= wait_imm::unset_counter
;
251 events
&= ~event_vmem_store
;
254 if (!(counters
& counter_lgkm
) && !(counters
& counter_vm
))
255 events
&= ~event_flat
;
261 enum chip_class chip_class
;
263 uint16_t max_exp_cnt
;
264 uint16_t max_lgkm_cnt
;
266 uint16_t unordered_events
= event_smem
| event_flat
;
270 uint8_t lgkm_cnt
= 0;
272 bool pending_flat_lgkm
= false;
273 bool pending_flat_vm
= false;
274 bool pending_s_buffer_store
= false; /* GFX10 workaround */
276 wait_imm barrier_imm
[barrier_count
];
277 uint16_t barrier_events
[barrier_count
] = {}; /* use wait_event notion */
279 std::map
<PhysReg
,wait_entry
> gpr_map
;
281 /* used for vmem/smem scores */
282 bool collect_statistics
;
283 Instruction
*gen_instr
;
284 std::map
<Instruction
*, unsigned> unwaited_instrs
[num_counters
];
285 std::map
<PhysReg
,std::set
<Instruction
*>> reg_instrs
[num_counters
];
286 std::vector
<unsigned> wait_distances
[num_events
];
289 wait_ctx(Program
*program_
)
291 chip_class(program_
->chip_class
),
292 max_vm_cnt(program_
->chip_class
>= GFX9
? 62 : 14),
294 max_lgkm_cnt(program_
->chip_class
>= GFX10
? 62 : 14),
295 max_vs_cnt(program_
->chip_class
>= GFX10
? 62 : 0),
296 unordered_events(event_smem
| (program_
->chip_class
< GFX10
? event_flat
: 0)),
297 collect_statistics(program_
->collect_statistics
) {}
299 bool join(const wait_ctx
* other
, bool logical
)
301 bool changed
= other
->exp_cnt
> exp_cnt
||
302 other
->vm_cnt
> vm_cnt
||
303 other
->lgkm_cnt
> lgkm_cnt
||
304 other
->vs_cnt
> vs_cnt
||
305 (other
->pending_flat_lgkm
&& !pending_flat_lgkm
) ||
306 (other
->pending_flat_vm
&& !pending_flat_vm
);
308 exp_cnt
= std::max(exp_cnt
, other
->exp_cnt
);
309 vm_cnt
= std::max(vm_cnt
, other
->vm_cnt
);
310 lgkm_cnt
= std::max(lgkm_cnt
, other
->lgkm_cnt
);
311 vs_cnt
= std::max(vs_cnt
, other
->vs_cnt
);
312 pending_flat_lgkm
|= other
->pending_flat_lgkm
;
313 pending_flat_vm
|= other
->pending_flat_vm
;
314 pending_s_buffer_store
|= other
->pending_s_buffer_store
;
316 for (std::pair
<PhysReg
,wait_entry
> entry
: other
->gpr_map
)
318 std::map
<PhysReg
,wait_entry
>::iterator it
= gpr_map
.find(entry
.first
);
319 if (entry
.second
.logical
!= logical
)
322 if (it
!= gpr_map
.end()) {
323 changed
|= it
->second
.join(entry
.second
);
325 gpr_map
.insert(entry
);
330 for (unsigned i
= 0; i
< barrier_count
; i
++) {
331 changed
|= barrier_imm
[i
].combine(other
->barrier_imm
[i
]);
332 changed
|= other
->barrier_events
[i
] & ~barrier_events
[i
];
333 barrier_events
[i
] |= other
->barrier_events
[i
];
336 /* these are used for statistics, so don't update "changed" */
337 for (unsigned i
= 0; i
< num_counters
; i
++) {
338 for (std::pair
<Instruction
*, unsigned> instr
: other
->unwaited_instrs
[i
]) {
339 auto pos
= unwaited_instrs
[i
].find(instr
.first
);
340 if (pos
== unwaited_instrs
[i
].end())
341 unwaited_instrs
[i
].insert(instr
);
343 pos
->second
= std::min(pos
->second
, instr
.second
);
345 /* don't use a foreach loop to avoid copies */
346 for (auto it
= other
->reg_instrs
[i
].begin(); it
!= other
->reg_instrs
[i
].end(); ++it
)
347 reg_instrs
[i
][it
->first
].insert(it
->second
.begin(), it
->second
.end());
353 void wait_and_remove_from_entry(PhysReg reg
, wait_entry
& entry
, counter_type counter
) {
354 if (collect_statistics
&& (entry
.counters
& counter
)) {
355 unsigned counter_idx
= ffs(counter
) - 1;
356 for (Instruction
*instr
: reg_instrs
[counter_idx
][reg
]) {
357 auto pos
= unwaited_instrs
[counter_idx
].find(instr
);
358 if (pos
== unwaited_instrs
[counter_idx
].end())
361 unsigned distance
= pos
->second
;
362 unsigned events
= entry
.events
& get_events_for_counter(counter
);
364 unsigned event_idx
= u_bit_scan(&events
);
365 wait_distances
[event_idx
].push_back(distance
);
368 unwaited_instrs
[counter_idx
].erase(instr
);
370 reg_instrs
[counter_idx
][reg
].clear();
373 entry
.remove_counter(counter
);
376 void advance_unwaited_instrs()
378 for (unsigned i
= 0; i
< num_counters
; i
++) {
379 for (auto it
= unwaited_instrs
[i
].begin(); it
!= unwaited_instrs
[i
].end(); ++it
)
385 wait_imm
check_instr(Instruction
* instr
, wait_ctx
& ctx
)
389 for (const Operand op
: instr
->operands
) {
390 if (op
.isConstant() || op
.isUndefined())
393 /* check consecutively read gprs */
394 for (unsigned j
= 0; j
< op
.size(); j
++) {
395 PhysReg reg
{op
.physReg() + j
};
396 std::map
<PhysReg
,wait_entry
>::iterator it
= ctx
.gpr_map
.find(reg
);
397 if (it
== ctx
.gpr_map
.end() || !it
->second
.wait_on_read
)
400 wait
.combine(it
->second
.imm
);
404 for (const Definition
& def
: instr
->definitions
) {
405 /* check consecutively written gprs */
406 for (unsigned j
= 0; j
< def
.getTemp().size(); j
++)
408 PhysReg reg
{def
.physReg() + j
};
410 std::map
<PhysReg
,wait_entry
>::iterator it
= ctx
.gpr_map
.find(reg
);
411 if (it
== ctx
.gpr_map
.end())
414 /* Vector Memory reads and writes return in the order they were issued */
415 bool has_sampler
= instr
->format
== Format::MIMG
&& !instr
->operands
[1].isUndefined() && instr
->operands
[1].regClass() == s4
;
416 if (instr
->isVMEM() && ((it
->second
.events
& vm_events
) == event_vmem
) &&
417 it
->second
.has_vmem_nosampler
== !has_sampler
&& it
->second
.has_vmem_sampler
== has_sampler
)
420 /* LDS reads and writes return in the order they were issued. same for GDS */
421 if (instr
->format
== Format::DS
) {
422 bool gds
= static_cast<DS_instruction
*>(instr
)->gds
;
423 if ((it
->second
.events
& lgkm_events
) == (gds
? event_gds
: event_lds
))
427 wait
.combine(it
->second
.imm
);
434 wait_imm
parse_wait_instr(wait_ctx
& ctx
, Instruction
*instr
)
436 if (instr
->opcode
== aco_opcode::s_waitcnt_vscnt
&&
437 instr
->definitions
[0].physReg() == sgpr_null
) {
439 imm
.vs
= std::min
<uint8_t>(imm
.vs
, static_cast<SOPK_instruction
*>(instr
)->imm
);
441 } else if (instr
->opcode
== aco_opcode::s_waitcnt
) {
442 return wait_imm(ctx
.chip_class
, static_cast<SOPP_instruction
*>(instr
)->imm
);
447 wait_imm
kill(Instruction
* instr
, wait_ctx
& ctx
)
450 if (ctx
.exp_cnt
|| ctx
.vm_cnt
|| ctx
.lgkm_cnt
)
451 imm
.combine(check_instr(instr
, ctx
));
453 imm
.combine(parse_wait_instr(ctx
, instr
));
456 /* It's required to wait for scalar stores before "writing back" data.
457 * It shouldn't cost anything anyways since we're about to do s_endpgm.
459 if (ctx
.lgkm_cnt
&& instr
->opcode
== aco_opcode::s_dcache_wb
) {
460 assert(ctx
.chip_class
>= GFX8
);
464 if (ctx
.chip_class
>= GFX10
&& instr
->format
== Format::SMEM
) {
465 /* GFX10: A store followed by a load at the same address causes a problem because
466 * the load doesn't load the correct values unless we wait for the store first.
467 * This is NOT mitigated by an s_nop.
469 * TODO: Refine this when we have proper alias analysis.
471 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
);
472 if (ctx
.pending_s_buffer_store
&&
473 !smem
->definitions
.empty() &&
474 !smem
->can_reorder
&& smem
->barrier
== barrier_buffer
) {
479 if (instr
->format
== Format::PSEUDO_BARRIER
) {
480 switch (instr
->opcode
) {
481 case aco_opcode::p_memory_barrier_common
:
482 imm
.combine(ctx
.barrier_imm
[ffs(barrier_atomic
) - 1]);
483 imm
.combine(ctx
.barrier_imm
[ffs(barrier_buffer
) - 1]);
484 imm
.combine(ctx
.barrier_imm
[ffs(barrier_image
) - 1]);
485 if (ctx
.program
->workgroup_size
> ctx
.program
->wave_size
)
486 imm
.combine(ctx
.barrier_imm
[ffs(barrier_shared
) - 1]);
488 case aco_opcode::p_memory_barrier_atomic
:
489 imm
.combine(ctx
.barrier_imm
[ffs(barrier_atomic
) - 1]);
491 /* see comment in aco_scheduler.cpp's can_move_instr() on why these barriers are merged */
492 case aco_opcode::p_memory_barrier_buffer
:
493 case aco_opcode::p_memory_barrier_image
:
494 imm
.combine(ctx
.barrier_imm
[ffs(barrier_buffer
) - 1]);
495 imm
.combine(ctx
.barrier_imm
[ffs(barrier_image
) - 1]);
497 case aco_opcode::p_memory_barrier_shared
:
498 if (ctx
.program
->workgroup_size
> ctx
.program
->wave_size
)
499 imm
.combine(ctx
.barrier_imm
[ffs(barrier_shared
) - 1]);
501 case aco_opcode::p_memory_barrier_gs_data
:
502 imm
.combine(ctx
.barrier_imm
[ffs(barrier_gs_data
) - 1]);
504 case aco_opcode::p_memory_barrier_gs_sendmsg
:
505 imm
.combine(ctx
.barrier_imm
[ffs(barrier_gs_sendmsg
) - 1]);
514 if (ctx
.pending_flat_vm
&& imm
.vm
!= wait_imm::unset_counter
)
516 if (ctx
.pending_flat_lgkm
&& imm
.lgkm
!= wait_imm::unset_counter
)
520 ctx
.exp_cnt
= std::min(ctx
.exp_cnt
, imm
.exp
);
521 ctx
.vm_cnt
= std::min(ctx
.vm_cnt
, imm
.vm
);
522 ctx
.lgkm_cnt
= std::min(ctx
.lgkm_cnt
, imm
.lgkm
);
523 ctx
.vs_cnt
= std::min(ctx
.vs_cnt
, imm
.vs
);
525 /* update barrier wait imms */
526 for (unsigned i
= 0; i
< barrier_count
; i
++) {
527 wait_imm
& bar
= ctx
.barrier_imm
[i
];
528 uint16_t& bar_ev
= ctx
.barrier_events
[i
];
529 if (bar
.exp
!= wait_imm::unset_counter
&& imm
.exp
<= bar
.exp
) {
530 bar
.exp
= wait_imm::unset_counter
;
531 bar_ev
&= ~exp_events
;
533 if (bar
.vm
!= wait_imm::unset_counter
&& imm
.vm
<= bar
.vm
) {
534 bar
.vm
= wait_imm::unset_counter
;
535 bar_ev
&= ~(vm_events
& ~event_flat
);
537 if (bar
.lgkm
!= wait_imm::unset_counter
&& imm
.lgkm
<= bar
.lgkm
) {
538 bar
.lgkm
= wait_imm::unset_counter
;
539 bar_ev
&= ~(lgkm_events
& ~event_flat
);
541 if (bar
.vs
!= wait_imm::unset_counter
&& imm
.vs
<= bar
.vs
) {
542 bar
.vs
= wait_imm::unset_counter
;
543 bar_ev
&= ~vs_events
;
545 if (bar
.vm
== wait_imm::unset_counter
&& bar
.lgkm
== wait_imm::unset_counter
)
546 bar_ev
&= ~event_flat
;
549 /* remove all gprs with higher counter from map */
550 std::map
<PhysReg
,wait_entry
>::iterator it
= ctx
.gpr_map
.begin();
551 while (it
!= ctx
.gpr_map
.end())
553 if (imm
.exp
!= wait_imm::unset_counter
&& imm
.exp
<= it
->second
.imm
.exp
)
554 ctx
.wait_and_remove_from_entry(it
->first
, it
->second
, counter_exp
);
555 if (imm
.vm
!= wait_imm::unset_counter
&& imm
.vm
<= it
->second
.imm
.vm
)
556 ctx
.wait_and_remove_from_entry(it
->first
, it
->second
, counter_vm
);
557 if (imm
.lgkm
!= wait_imm::unset_counter
&& imm
.lgkm
<= it
->second
.imm
.lgkm
)
558 ctx
.wait_and_remove_from_entry(it
->first
, it
->second
, counter_lgkm
);
559 if (imm
.vs
!= wait_imm::unset_counter
&& imm
.vs
<= it
->second
.imm
.vs
)
560 ctx
.wait_and_remove_from_entry(it
->first
, it
->second
, counter_vs
);
561 if (!it
->second
.counters
)
562 it
= ctx
.gpr_map
.erase(it
);
569 ctx
.pending_flat_vm
= false;
571 ctx
.pending_flat_lgkm
= false;
572 ctx
.pending_s_buffer_store
= false;
578 void update_barrier_counter(uint8_t *ctr
, unsigned max
)
580 if (*ctr
!= wait_imm::unset_counter
&& *ctr
< max
)
584 void update_barrier_imm(wait_ctx
& ctx
, uint8_t counters
, wait_event event
, barrier_interaction barrier
)
586 for (unsigned i
= 0; i
< barrier_count
; i
++) {
587 wait_imm
& bar
= ctx
.barrier_imm
[i
];
588 uint16_t& bar_ev
= ctx
.barrier_events
[i
];
589 if (barrier
& (1 << i
)) {
591 if (counters
& counter_lgkm
)
593 if (counters
& counter_vm
)
595 if (counters
& counter_exp
)
597 if (counters
& counter_vs
)
599 } else if (!(bar_ev
& ctx
.unordered_events
) && !(ctx
.unordered_events
& event
)) {
600 if (counters
& counter_lgkm
&& (bar_ev
& lgkm_events
) == event
)
601 update_barrier_counter(&bar
.lgkm
, ctx
.max_lgkm_cnt
);
602 if (counters
& counter_vm
&& (bar_ev
& vm_events
) == event
)
603 update_barrier_counter(&bar
.vm
, ctx
.max_vm_cnt
);
604 if (counters
& counter_exp
&& (bar_ev
& exp_events
) == event
)
605 update_barrier_counter(&bar
.exp
, ctx
.max_exp_cnt
);
606 if (counters
& counter_vs
&& (bar_ev
& vs_events
) == event
)
607 update_barrier_counter(&bar
.vs
, ctx
.max_vs_cnt
);
612 void update_counters(wait_ctx
& ctx
, wait_event event
, barrier_interaction barrier
=barrier_none
)
614 uint8_t counters
= get_counters_for_event(event
);
616 if (counters
& counter_lgkm
&& ctx
.lgkm_cnt
<= ctx
.max_lgkm_cnt
)
618 if (counters
& counter_vm
&& ctx
.vm_cnt
<= ctx
.max_vm_cnt
)
620 if (counters
& counter_exp
&& ctx
.exp_cnt
<= ctx
.max_exp_cnt
)
622 if (counters
& counter_vs
&& ctx
.vs_cnt
<= ctx
.max_vs_cnt
)
625 update_barrier_imm(ctx
, counters
, event
, barrier
);
627 if (ctx
.unordered_events
& event
)
630 if (ctx
.pending_flat_lgkm
)
631 counters
&= ~counter_lgkm
;
632 if (ctx
.pending_flat_vm
)
633 counters
&= ~counter_vm
;
635 for (std::pair
<const PhysReg
,wait_entry
>& e
: ctx
.gpr_map
) {
636 wait_entry
& entry
= e
.second
;
638 if (entry
.events
& ctx
.unordered_events
)
641 assert(entry
.events
);
643 if ((counters
& counter_exp
) && (entry
.events
& exp_events
) == event
&& entry
.imm
.exp
< ctx
.max_exp_cnt
)
645 if ((counters
& counter_lgkm
) && (entry
.events
& lgkm_events
) == event
&& entry
.imm
.lgkm
< ctx
.max_lgkm_cnt
)
647 if ((counters
& counter_vm
) && (entry
.events
& vm_events
) == event
&& entry
.imm
.vm
< ctx
.max_vm_cnt
)
649 if ((counters
& counter_vs
) && (entry
.events
& vs_events
) == event
&& entry
.imm
.vs
< ctx
.max_vs_cnt
)
654 void update_counters_for_flat_load(wait_ctx
& ctx
, barrier_interaction barrier
=barrier_none
)
656 assert(ctx
.chip_class
< GFX10
);
658 if (ctx
.lgkm_cnt
<= ctx
.max_lgkm_cnt
)
660 if (ctx
.vm_cnt
<= ctx
.max_vm_cnt
)
663 update_barrier_imm(ctx
, counter_vm
| counter_lgkm
, event_flat
, barrier
);
665 for (std::pair
<PhysReg
,wait_entry
> e
: ctx
.gpr_map
)
667 if (e
.second
.counters
& counter_vm
)
669 if (e
.second
.counters
& counter_lgkm
)
670 e
.second
.imm
.lgkm
= 0;
672 ctx
.pending_flat_lgkm
= true;
673 ctx
.pending_flat_vm
= true;
676 void insert_wait_entry(wait_ctx
& ctx
, PhysReg reg
, RegClass rc
, wait_event event
, bool wait_on_read
,
677 bool has_sampler
=false)
679 uint16_t counters
= get_counters_for_event(event
);
681 if (counters
& counter_lgkm
)
683 if (counters
& counter_vm
)
685 if (counters
& counter_exp
)
687 if (counters
& counter_vs
)
690 wait_entry
new_entry(event
, imm
, !rc
.is_linear(), wait_on_read
);
691 new_entry
.has_vmem_nosampler
= (event
& event_vmem
) && !has_sampler
;
692 new_entry
.has_vmem_sampler
= (event
& event_vmem
) && has_sampler
;
694 for (unsigned i
= 0; i
< rc
.size(); i
++) {
695 auto it
= ctx
.gpr_map
.emplace(PhysReg
{reg
.reg()+i
}, new_entry
);
697 it
.first
->second
.join(new_entry
);
700 if (ctx
.collect_statistics
) {
701 unsigned counters_todo
= counters
;
702 while (counters_todo
) {
703 unsigned i
= u_bit_scan(&counters_todo
);
704 ctx
.unwaited_instrs
[i
].insert(std::make_pair(ctx
.gen_instr
, 0u));
705 for (unsigned j
= 0; j
< rc
.size(); j
++)
706 ctx
.reg_instrs
[i
][PhysReg
{reg
.reg()+j
}].insert(ctx
.gen_instr
);
711 void insert_wait_entry(wait_ctx
& ctx
, Operand op
, wait_event event
, bool has_sampler
=false)
713 if (!op
.isConstant() && !op
.isUndefined())
714 insert_wait_entry(ctx
, op
.physReg(), op
.regClass(), event
, false, has_sampler
);
717 void insert_wait_entry(wait_ctx
& ctx
, Definition def
, wait_event event
, bool has_sampler
=false)
719 insert_wait_entry(ctx
, def
.physReg(), def
.regClass(), event
, true, has_sampler
);
722 void gen(Instruction
* instr
, wait_ctx
& ctx
)
724 switch (instr
->format
) {
726 Export_instruction
* exp_instr
= static_cast<Export_instruction
*>(instr
);
729 if (exp_instr
->dest
<= 9)
730 ev
= event_exp_mrt_null
;
731 else if (exp_instr
->dest
<= 15)
734 ev
= event_exp_param
;
735 update_counters(ctx
, ev
);
737 /* insert new entries for exported vgprs */
738 for (unsigned i
= 0; i
< 4; i
++)
740 if (exp_instr
->enabled_mask
& (1 << i
)) {
741 unsigned idx
= exp_instr
->compressed
? i
>> 1 : i
;
742 assert(idx
< exp_instr
->operands
.size());
743 insert_wait_entry(ctx
, exp_instr
->operands
[idx
], ev
);
747 insert_wait_entry(ctx
, exec
, s2
, ev
, false);
751 if (ctx
.chip_class
< GFX10
&& !instr
->definitions
.empty())
752 update_counters_for_flat_load(ctx
, barrier_buffer
);
754 update_counters(ctx
, event_flat
, barrier_buffer
);
756 if (!instr
->definitions
.empty())
757 insert_wait_entry(ctx
, instr
->definitions
[0], event_flat
);
761 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
);
762 update_counters(ctx
, event_smem
, static_cast<SMEM_instruction
*>(instr
)->barrier
);
764 if (!instr
->definitions
.empty())
765 insert_wait_entry(ctx
, instr
->definitions
[0], event_smem
);
766 else if (ctx
.chip_class
>= GFX10
&&
767 !smem
->can_reorder
&&
768 smem
->barrier
== barrier_buffer
)
769 ctx
.pending_s_buffer_store
= true;
774 bool gds
= static_cast<DS_instruction
*>(instr
)->gds
;
775 update_counters(ctx
, gds
? event_gds
: event_lds
, gds
? barrier_none
: barrier_shared
);
777 update_counters(ctx
, event_gds_gpr_lock
);
779 if (!instr
->definitions
.empty())
780 insert_wait_entry(ctx
, instr
->definitions
[0], gds
? event_gds
: event_lds
);
783 for (const Operand
& op
: instr
->operands
)
784 insert_wait_entry(ctx
, op
, event_gds_gpr_lock
);
785 insert_wait_entry(ctx
, exec
, s2
, event_gds_gpr_lock
, false);
792 case Format::GLOBAL
: {
793 wait_event ev
= !instr
->definitions
.empty() || ctx
.chip_class
< GFX10
? event_vmem
: event_vmem_store
;
794 update_counters(ctx
, ev
, get_barrier_interaction(instr
));
796 bool has_sampler
= instr
->format
== Format::MIMG
&& !instr
->operands
[1].isUndefined() && instr
->operands
[1].regClass() == s4
;
798 if (!instr
->definitions
.empty())
799 insert_wait_entry(ctx
, instr
->definitions
[0], ev
, has_sampler
);
801 if (ctx
.chip_class
== GFX6
&&
802 instr
->format
!= Format::MIMG
&&
803 instr
->operands
.size() == 4) {
805 update_counters(ctx
, event_vmem_gpr_lock
);
806 insert_wait_entry(ctx
, instr
->operands
[3], event_vmem_gpr_lock
);
807 } else if (ctx
.chip_class
== GFX6
&&
808 instr
->format
== Format::MIMG
&&
809 instr
->operands
[1].regClass().type() == RegType::vgpr
) {
811 update_counters(ctx
, event_vmem_gpr_lock
);
812 insert_wait_entry(ctx
, instr
->operands
[1], event_vmem_gpr_lock
);
818 if (instr
->opcode
== aco_opcode::s_sendmsg
||
819 instr
->opcode
== aco_opcode::s_sendmsghalt
)
820 update_counters(ctx
, event_sendmsg
, get_barrier_interaction(instr
));
827 void emit_waitcnt(wait_ctx
& ctx
, std::vector
<aco_ptr
<Instruction
>>& instructions
, wait_imm imm
)
829 if (imm
.vs
!= wait_imm::unset_counter
) {
830 assert(ctx
.chip_class
>= GFX10
);
831 SOPK_instruction
* waitcnt_vs
= create_instruction
<SOPK_instruction
>(aco_opcode::s_waitcnt_vscnt
, Format::SOPK
, 0, 1);
832 waitcnt_vs
->definitions
[0] = Definition(sgpr_null
, s1
);
833 waitcnt_vs
->imm
= imm
.vs
;
834 instructions
.emplace_back(waitcnt_vs
);
835 imm
.vs
= wait_imm::unset_counter
;
838 SOPP_instruction
* waitcnt
= create_instruction
<SOPP_instruction
>(aco_opcode::s_waitcnt
, Format::SOPP
, 0, 0);
839 waitcnt
->imm
= imm
.pack(ctx
.chip_class
);
841 instructions
.emplace_back(waitcnt
);
845 void handle_block(Program
*program
, Block
& block
, wait_ctx
& ctx
)
847 std::vector
<aco_ptr
<Instruction
>> new_instructions
;
851 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
852 bool is_wait
= !parse_wait_instr(ctx
, instr
.get()).empty();
854 queued_imm
.combine(kill(instr
.get(), ctx
));
856 ctx
.gen_instr
= instr
.get();
857 gen(instr
.get(), ctx
);
859 if (instr
->format
!= Format::PSEUDO_BARRIER
&& !is_wait
) {
860 if (!queued_imm
.empty()) {
861 emit_waitcnt(ctx
, new_instructions
, queued_imm
);
862 queued_imm
= wait_imm();
864 new_instructions
.emplace_back(std::move(instr
));
866 if (ctx
.collect_statistics
)
867 ctx
.advance_unwaited_instrs();
871 if (!queued_imm
.empty())
872 emit_waitcnt(ctx
, new_instructions
, queued_imm
);
874 block
.instructions
.swap(new_instructions
);
877 } /* end namespace */
879 static uint32_t calculate_score(std::vector
<wait_ctx
> &ctx_vec
, uint32_t event_mask
)
882 unsigned num_waits
= 0;
884 unsigned event_index
= u_bit_scan(&event_mask
);
885 for (const wait_ctx
&ctx
: ctx_vec
) {
886 for (unsigned dist
: ctx
.wait_distances
[event_index
]) {
888 /* for many events, excessive distances provide little benefit, so
889 * decrease the score in that case. */
890 double threshold
= INFINITY
;
891 double inv_strength
= 0.000001;
892 switch (1 << event_index
) {
898 case event_vmem_store
:
901 inv_strength
= 150.0;
909 if (score
> threshold
) {
911 score
= threshold
+ score
/ (1.0 + score
/ inv_strength
);
914 /* we don't want increases in high scores to hide decreases in low scores,
915 * so raise to the power of 0.1 before averaging. */
916 result
+= pow(score
, 0.1);
921 return round(pow(result
/ num_waits
, 10.0) * 10.0);
924 void insert_wait_states(Program
* program
)
927 std::vector
<bool> done(program
->blocks
.size());
928 std::vector
<wait_ctx
> in_ctx(program
->blocks
.size(), wait_ctx(program
));
929 std::vector
<wait_ctx
> out_ctx(program
->blocks
.size(), wait_ctx(program
));
931 std::stack
<unsigned> loop_header_indices
;
932 unsigned loop_progress
= 0;
934 for (unsigned i
= 0; i
< program
->blocks
.size();) {
935 Block
& current
= program
->blocks
[i
++];
936 wait_ctx ctx
= in_ctx
[current
.index
];
938 if (current
.kind
& block_kind_loop_header
) {
939 loop_header_indices
.push(current
.index
);
940 } else if (current
.kind
& block_kind_loop_exit
) {
942 if (loop_progress
== loop_header_indices
.size()) {
943 i
= loop_header_indices
.top();
946 loop_header_indices
.pop();
947 loop_progress
= std::min
<unsigned>(loop_progress
, loop_header_indices
.size());
952 bool changed
= false;
953 for (unsigned b
: current
.linear_preds
)
954 changed
|= ctx
.join(&out_ctx
[b
], false);
955 for (unsigned b
: current
.logical_preds
)
956 changed
|= ctx
.join(&out_ctx
[b
], true);
958 if (done
[current
.index
] && !changed
) {
959 in_ctx
[current
.index
] = std::move(ctx
);
962 in_ctx
[current
.index
] = ctx
;
965 if (current
.instructions
.empty()) {
966 out_ctx
[current
.index
] = std::move(ctx
);
970 loop_progress
= std::max
<unsigned>(loop_progress
, current
.loop_nest_depth
);
971 done
[current
.index
] = true;
973 handle_block(program
, current
, ctx
);
975 out_ctx
[current
.index
] = std::move(ctx
);
978 if (program
->collect_statistics
) {
979 program
->statistics
[statistic_vmem_score
] =
980 calculate_score(out_ctx
, event_vmem
| event_flat
| event_vmem_store
);
981 program
->statistics
[statistic_smem_score
] =
982 calculate_score(out_ctx
, event_smem
);