src/amd/compiler/aco_insert_waitcnt.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <algorithm>
  26 #include <map>
  27 #include <stack>
  28 #include <math.h>
  29
  30 #include "aco_ir.h"
  31 #include "vulkan/radv_shader.h"
  32
  33 namespace aco {
  34
  35 namespace {
  36
  37 /**
  38  * The general idea of this pass is:
  39  * The CFG is traversed in reverse postorder (forward) and loops are processed
  40  * several times until no progress is made.
  41  * Per BB two wait_ctx is maintained: an in-context and out-context.
  42  * The in-context is the joined out-contexts of the predecessors.
  43  * The context contains a map: gpr -> wait_entry
  44  * consisting of the information about the cnt values to be waited for.
  45  * Note: After merge-nodes, it might occur that for the same register
  46  *       multiple cnt values are to be waited for.
  47  *
  48  * The values are updated according to the encountered instructions:
  49  * - additional events increment the counter of waits of the same type
  50  * - or erase gprs with counters higher than to be waited for.
  51  */
  52
  53 // TODO: do a more clever insertion of wait_cnt (lgkm_cnt) when there is a load followed by a use of a previous load
  54
  55 /* Instructions of the same event will finish in-order except for smem
  56  * and maybe flat. Instructions of different events may not finish in-order. */
  57 enum wait_event : uint16_t {
  58    event_smem = 1 << 0,
  59    event_lds = 1 << 1,
  60    event_gds = 1 << 2,
  61    event_vmem = 1 << 3,
  62    event_vmem_store = 1 << 4, /* GFX10+ */
  63    event_flat = 1 << 5,
  64    event_exp_pos = 1 << 6,
  65    event_exp_param = 1 << 7,
  66    event_exp_mrt_null = 1 << 8,
  67    event_gds_gpr_lock = 1 << 9,
  68    event_vmem_gpr_lock = 1 << 10,
  69    event_sendmsg = 1 << 11,
  70    num_events = 12,
  71 };
  72
  73 enum counter_type : uint8_t {
  74    counter_exp = 1 << 0,
  75    counter_lgkm = 1 << 1,
  76    counter_vm = 1 << 2,
  77    counter_vs = 1 << 3,
  78    num_counters = 4,
  79 };
  80
  81 static const uint16_t exp_events = event_exp_pos | event_exp_param | event_exp_mrt_null | event_gds_gpr_lock | event_vmem_gpr_lock;
  82 static const uint16_t lgkm_events = event_smem | event_lds | event_gds | event_flat | event_sendmsg;
  83 static const uint16_t vm_events = event_vmem | event_flat;
  84 static const uint16_t vs_events = event_vmem_store;
  85
  86 uint8_t get_counters_for_event(wait_event ev)
  87 {
  88    switch (ev) {
  89    case event_smem:
  90    case event_lds:
  91    case event_gds:
  92    case event_sendmsg:
  93       return counter_lgkm;
  94    case event_vmem:
  95       return counter_vm;
  96    case event_vmem_store:
  97       return counter_vs;
  98    case event_flat:
  99       return counter_vm | counter_lgkm;
 100    case event_exp_pos:
 101    case event_exp_param:
 102    case event_exp_mrt_null:
 103    case event_gds_gpr_lock:
 104    case event_vmem_gpr_lock:
 105       return counter_exp;
 106    default:
 107       return 0;
 108    }
 109 }
 110
 111 uint16_t get_events_for_counter(counter_type ctr)
 112 {
 113    switch (ctr) {
 114    case counter_exp:
 115       return exp_events;
 116    case counter_lgkm:
 117       return lgkm_events;
 118    case counter_vm:
 119       return vm_events;
 120    case counter_vs:
 121       return vs_events;
 122    }
 123    return 0;
 124 }
 125
 126 struct wait_imm {
 127    static const uint8_t unset_counter = 0xff;
 128
 129    uint8_t vm;
 130    uint8_t exp;
 131    uint8_t lgkm;
 132    uint8_t vs;
 133
 134    wait_imm() :
 135       vm(unset_counter), exp(unset_counter), lgkm(unset_counter), vs(unset_counter) {}
 136    wait_imm(uint16_t vm_, uint16_t exp_, uint16_t lgkm_, uint16_t vs_) :
 137       vm(vm_), exp(exp_), lgkm(lgkm_), vs(vs_) {}
 138
 139    wait_imm(enum chip_class chip, uint16_t packed) : vs(unset_counter)
 140    {
 141       vm = packed & 0xf;
 142       if (chip >= GFX9)
 143          vm |= (packed >> 10) & 0x30;
 144
 145       exp = (packed >> 4) & 0x7;
 146
 147       lgkm = (packed >> 8) & 0xf;
 148       if (chip >= GFX10)
 149          lgkm |= (packed >> 8) & 0x30;
 150    }
 151
 152    uint16_t pack(enum chip_class chip) const
 153    {
 154       uint16_t imm = 0;
 155       assert(exp == unset_counter || exp <= 0x7);
 156       switch (chip) {
 157       case GFX10:
 158          assert(lgkm == unset_counter || lgkm <= 0x3f);
 159          assert(vm == unset_counter || vm <= 0x3f);
 160          imm = ((vm & 0x30) << 10) | ((lgkm & 0x3f) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 161          break;
 162       case GFX9:
 163          assert(lgkm == unset_counter || lgkm <= 0xf);
 164          assert(vm == unset_counter || vm <= 0x3f);
 165          imm = ((vm & 0x30) << 10) | ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 166          break;
 167       default:
 168          assert(lgkm == unset_counter || lgkm <= 0xf);
 169          assert(vm == unset_counter || vm <= 0xf);
 170          imm = ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 171          break;
 172       }
 173       if (chip < GFX9 && vm == wait_imm::unset_counter)
 174          imm |= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the architecture when interpreting the immediate */
 175       if (chip < GFX10 && lgkm == wait_imm::unset_counter)
 176          imm |= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the architecture when interpreting the immediate */
 177       return imm;
 178    }
 179
 180    bool combine(const wait_imm& other)
 181    {
 182       bool changed = other.vm < vm || other.exp < exp || other.lgkm < lgkm || other.vs < vs;
 183       vm = std::min(vm, other.vm);
 184       exp = std::min(exp, other.exp);
 185       lgkm = std::min(lgkm, other.lgkm);
 186       vs = std::min(vs, other.vs);
 187       return changed;
 188    }
 189
 190    bool empty() const
 191    {
 192       return vm == unset_counter && exp == unset_counter &&
 193              lgkm == unset_counter && vs == unset_counter;
 194    }
 195 };
 196
 197 struct wait_entry {
 198    wait_imm imm;
 199    uint16_t events; /* use wait_event notion */
 200    uint8_t counters; /* use counter_type notion */
 201    bool wait_on_read:1;
 202    bool logical:1;
 203    bool has_vmem_nosampler:1;
 204    bool has_vmem_sampler:1;
 205
 206    wait_entry(wait_event event, wait_imm imm, bool logical, bool wait_on_read)
 207            : imm(imm), events(event), counters(get_counters_for_event(event)),
 208              wait_on_read(wait_on_read), logical(logical),
 209              has_vmem_nosampler(false), has_vmem_sampler(false) {}
 210
 211    bool join(const wait_entry& other)
 212    {
 213       bool changed = (other.events & ~events) ||
 214                      (other.counters & ~counters) ||
 215                      (other.wait_on_read && !wait_on_read) ||
 216                      (other.has_vmem_nosampler && !has_vmem_nosampler) ||
 217                      (other.has_vmem_sampler && !has_vmem_sampler);
 218       events |= other.events;
 219       counters |= other.counters;
 220       changed |= imm.combine(other.imm);
 221       wait_on_read |= other.wait_on_read;
 222       has_vmem_nosampler |= other.has_vmem_nosampler;
 223       has_vmem_sampler |= other.has_vmem_sampler;
 224       assert(logical == other.logical);
 225       return changed;
 226    }
 227
 228    void remove_counter(counter_type counter)
 229    {
 230       counters &= ~counter;
 231
 232       if (counter == counter_lgkm) {
 233          imm.lgkm = wait_imm::unset_counter;
 234          events &= ~(event_smem | event_lds | event_gds | event_sendmsg);
 235       }
 236
 237       if (counter == counter_vm) {
 238          imm.vm = wait_imm::unset_counter;
 239          events &= ~event_vmem;
 240          has_vmem_nosampler = false;
 241          has_vmem_sampler = false;
 242       }
 243
 244       if (counter == counter_exp) {
 245          imm.exp = wait_imm::unset_counter;
 246          events &= ~(event_exp_pos | event_exp_param | event_exp_mrt_null | event_gds_gpr_lock | event_vmem_gpr_lock);
 247       }
 248
 249       if (counter == counter_vs) {
 250          imm.vs = wait_imm::unset_counter;
 251          events &= ~event_vmem_store;
 252       }
 253
 254       if (!(counters & counter_lgkm) && !(counters & counter_vm))
 255          events &= ~event_flat;
 256    }
 257 };
 258
 259 struct wait_ctx {
 260    Program *program;
 261    enum chip_class chip_class;
 262    uint16_t max_vm_cnt;
 263    uint16_t max_exp_cnt;
 264    uint16_t max_lgkm_cnt;
 265    uint16_t max_vs_cnt;
 266    uint16_t unordered_events = event_smem | event_flat;
 267
 268    uint8_t vm_cnt = 0;
 269    uint8_t exp_cnt = 0;
 270    uint8_t lgkm_cnt = 0;
 271    uint8_t vs_cnt = 0;
 272    bool pending_flat_lgkm = false;
 273    bool pending_flat_vm = false;
 274    bool pending_s_buffer_store = false; /* GFX10 workaround */
 275
 276    wait_imm barrier_imm[storage_count];
 277    uint16_t barrier_events[storage_count] = {}; /* use wait_event notion */
 278
 279    std::map<PhysReg,wait_entry> gpr_map;
 280
 281    /* used for vmem/smem scores */
 282    bool collect_statistics;
 283    Instruction *gen_instr;
 284    std::map<Instruction *, unsigned> unwaited_instrs[num_counters];
 285    std::map<PhysReg,std::set<Instruction *>> reg_instrs[num_counters];
 286    std::vector<unsigned> wait_distances[num_events];
 287
 288    wait_ctx() {}
 289    wait_ctx(Program *program_)
 290            : program(program_),
 291              chip_class(program_->chip_class),
 292              max_vm_cnt(program_->chip_class >= GFX9 ? 62 : 14),
 293              max_exp_cnt(6),
 294              max_lgkm_cnt(program_->chip_class >= GFX10 ? 62 : 14),
 295              max_vs_cnt(program_->chip_class >= GFX10 ? 62 : 0),
 296              unordered_events(event_smem | (program_->chip_class < GFX10 ? event_flat : 0)),
 297              collect_statistics(program_->collect_statistics) {}
 298
 299    bool join(const wait_ctx* other, bool logical)
 300    {
 301       bool changed = other->exp_cnt > exp_cnt ||
 302                      other->vm_cnt > vm_cnt ||
 303                      other->lgkm_cnt > lgkm_cnt ||
 304                      other->vs_cnt > vs_cnt ||
 305                      (other->pending_flat_lgkm && !pending_flat_lgkm) ||
 306                      (other->pending_flat_vm && !pending_flat_vm);
 307
 308       exp_cnt = std::max(exp_cnt, other->exp_cnt);
 309       vm_cnt = std::max(vm_cnt, other->vm_cnt);
 310       lgkm_cnt = std::max(lgkm_cnt, other->lgkm_cnt);
 311       vs_cnt = std::max(vs_cnt, other->vs_cnt);
 312       pending_flat_lgkm |= other->pending_flat_lgkm;
 313       pending_flat_vm |= other->pending_flat_vm;
 314       pending_s_buffer_store |= other->pending_s_buffer_store;
 315
 316       for (std::pair<PhysReg,wait_entry> entry : other->gpr_map)
 317       {
 318          std::map<PhysReg,wait_entry>::iterator it = gpr_map.find(entry.first);
 319          if (entry.second.logical != logical)
 320             continue;
 321
 322          if (it != gpr_map.end()) {
 323             changed |= it->second.join(entry.second);
 324          } else {
 325             gpr_map.insert(entry);
 326             changed = true;
 327          }
 328       }
 329
 330       for (unsigned i = 0; i < storage_count; i++) {
 331          changed |= barrier_imm[i].combine(other->barrier_imm[i]);
 332          changed |= other->barrier_events[i] & ~barrier_events[i];
 333          barrier_events[i] |= other->barrier_events[i];
 334       }
 335
 336       /* these are used for statistics, so don't update "changed" */
 337       for (unsigned i = 0; i < num_counters; i++) {
 338          for (std::pair<Instruction *, unsigned> instr : other->unwaited_instrs[i]) {
 339             auto pos = unwaited_instrs[i].find(instr.first);
 340             if (pos == unwaited_instrs[i].end())
 341                unwaited_instrs[i].insert(instr);
 342             else
 343                pos->second = std::min(pos->second, instr.second);
 344          }
 345          /* don't use a foreach loop to avoid copies */
 346          for (auto it = other->reg_instrs[i].begin(); it != other->reg_instrs[i].end(); ++it)
 347             reg_instrs[i][it->first].insert(it->second.begin(), it->second.end());
 348       }
 349
 350       return changed;
 351    }
 352
 353    void wait_and_remove_from_entry(PhysReg reg, wait_entry& entry, counter_type counter) {
 354       if (collect_statistics && (entry.counters & counter)) {
 355          unsigned counter_idx = ffs(counter) - 1;
 356          for (Instruction *instr : reg_instrs[counter_idx][reg]) {
 357             auto pos = unwaited_instrs[counter_idx].find(instr);
 358             if (pos == unwaited_instrs[counter_idx].end())
 359                continue;
 360
 361             unsigned distance = pos->second;
 362             unsigned events = entry.events & get_events_for_counter(counter);
 363             while (events) {
 364                unsigned event_idx = u_bit_scan(&events);
 365                wait_distances[event_idx].push_back(distance);
 366             }
 367
 368             unwaited_instrs[counter_idx].erase(instr);
 369          }
 370          reg_instrs[counter_idx][reg].clear();
 371       }
 372
 373       entry.remove_counter(counter);
 374    }
 375
 376    void advance_unwaited_instrs()
 377    {
 378       for (unsigned i = 0; i < num_counters; i++) {
 379          for (auto it = unwaited_instrs[i].begin(); it != unwaited_instrs[i].end(); ++it)
 380             it->second++;
 381       }
 382    }
 383 };
 384
 385 wait_imm check_instr(Instruction* instr, wait_ctx& ctx)
 386 {
 387    wait_imm wait;
 388
 389    for (const Operand op : instr->operands) {
 390       if (op.isConstant() || op.isUndefined())
 391          continue;
 392
 393       /* check consecutively read gprs */
 394       for (unsigned j = 0; j < op.size(); j++) {
 395          PhysReg reg{op.physReg() + j};
 396          std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.find(reg);
 397          if (it == ctx.gpr_map.end() || !it->second.wait_on_read)
 398             continue;
 399
 400          wait.combine(it->second.imm);
 401       }
 402    }
 403
 404    for (const Definition& def : instr->definitions) {
 405       /* check consecutively written gprs */
 406       for (unsigned j = 0; j < def.getTemp().size(); j++)
 407       {
 408          PhysReg reg{def.physReg() + j};
 409
 410          std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.find(reg);
 411          if (it == ctx.gpr_map.end())
 412             continue;
 413
 414          /* Vector Memory reads and writes return in the order they were issued */
 415          bool has_sampler = instr->format == Format::MIMG && !instr->operands[1].isUndefined() && instr->operands[1].regClass() == s4;
 416          if (instr->isVMEM() && ((it->second.events & vm_events) == event_vmem) &&
 417              it->second.has_vmem_nosampler == !has_sampler && it->second.has_vmem_sampler == has_sampler)
 418             continue;
 419
 420          /* LDS reads and writes return in the order they were issued. same for GDS */
 421          if (instr->format == Format::DS) {
 422             bool gds = static_cast<DS_instruction*>(instr)->gds;
 423             if ((it->second.events & lgkm_events) == (gds ? event_gds : event_lds))
 424                continue;
 425          }
 426
 427          wait.combine(it->second.imm);
 428       }
 429    }
 430
 431    return wait;
 432 }
 433
 434 wait_imm parse_wait_instr(wait_ctx& ctx, Instruction *instr)
 435 {
 436    if (instr->opcode == aco_opcode::s_waitcnt_vscnt &&
 437        instr->definitions[0].physReg() == sgpr_null) {
 438       wait_imm imm;
 439       imm.vs = std::min<uint8_t>(imm.vs, static_cast<SOPK_instruction*>(instr)->imm);
 440       return imm;
 441    } else if (instr->opcode == aco_opcode::s_waitcnt) {
 442       return wait_imm(ctx.chip_class, static_cast<SOPP_instruction*>(instr)->imm);
 443    }
 444    return wait_imm();
 445 }
 446
 447 wait_imm perform_barrier(wait_ctx& ctx, memory_sync_info sync, unsigned semantics)
 448 {
 449    wait_imm imm;
 450    sync_scope subgroup_scope = ctx.program->workgroup_size <= ctx.program->wave_size ? scope_workgroup : scope_subgroup;
 451    if (sync.semantics & semantics) {
 452       unsigned storage = sync.storage;
 453       while (storage) {
 454          unsigned idx = u_bit_scan(&storage);
 455
 456          /* LDS is private to the workgroup */
 457          sync_scope bar_scope_lds = MIN2(sync.scope, scope_workgroup);
 458
 459          uint16_t events = ctx.barrier_events[idx];
 460          if (bar_scope_lds <= subgroup_scope)
 461             events &= ~event_lds;
 462
 463          if (events)
 464             imm.combine(ctx.barrier_imm[idx]);
 465       }
 466    }
 467
 468    return imm;
 469 }
 470
 471 wait_imm kill(Instruction* instr, wait_ctx& ctx, memory_sync_info sync_info)
 472 {
 473    wait_imm imm;
 474    if (ctx.exp_cnt || ctx.vm_cnt || ctx.lgkm_cnt)
 475       imm.combine(check_instr(instr, ctx));
 476
 477    imm.combine(parse_wait_instr(ctx, instr));
 478
 479
 480    /* It's required to wait for scalar stores before "writing back" data.
 481     * It shouldn't cost anything anyways since we're about to do s_endpgm.
 482     */
 483    if (ctx.lgkm_cnt && instr->opcode == aco_opcode::s_dcache_wb) {
 484       assert(ctx.chip_class >= GFX8);
 485       imm.lgkm = 0;
 486    }
 487
 488    if (ctx.chip_class >= GFX10 && instr->format == Format::SMEM) {
 489       /* GFX10: A store followed by a load at the same address causes a problem because
 490        * the load doesn't load the correct values unless we wait for the store first.
 491        * This is NOT mitigated by an s_nop.
 492        *
 493        * TODO: Refine this when we have proper alias analysis.
 494        */
 495       SMEM_instruction *smem = static_cast<SMEM_instruction *>(instr);
 496       if (ctx.pending_s_buffer_store &&
 497           !smem->definitions.empty() &&
 498           !smem->sync.can_reorder()) {
 499          imm.lgkm = 0;
 500       }
 501    }
 502
 503    if (instr->opcode == aco_opcode::p_barrier)
 504       imm.combine(perform_barrier(ctx, static_cast<Pseudo_barrier_instruction *>(instr)->sync, semantic_acqrel));
 505    else
 506       imm.combine(perform_barrier(ctx, sync_info, semantic_release));
 507
 508    if (!imm.empty()) {
 509       if (ctx.pending_flat_vm && imm.vm != wait_imm::unset_counter)
 510          imm.vm = 0;
 511       if (ctx.pending_flat_lgkm && imm.lgkm != wait_imm::unset_counter)
 512          imm.lgkm = 0;
 513
 514       /* reset counters */
 515       ctx.exp_cnt = std::min(ctx.exp_cnt, imm.exp);
 516       ctx.vm_cnt = std::min(ctx.vm_cnt, imm.vm);
 517       ctx.lgkm_cnt = std::min(ctx.lgkm_cnt, imm.lgkm);
 518       ctx.vs_cnt = std::min(ctx.vs_cnt, imm.vs);
 519
 520       /* update barrier wait imms */
 521       for (unsigned i = 0; i < storage_count; i++) {
 522          wait_imm& bar = ctx.barrier_imm[i];
 523          uint16_t& bar_ev = ctx.barrier_events[i];
 524          if (bar.exp != wait_imm::unset_counter && imm.exp <= bar.exp) {
 525             bar.exp = wait_imm::unset_counter;
 526             bar_ev &= ~exp_events;
 527          }
 528          if (bar.vm != wait_imm::unset_counter && imm.vm <= bar.vm) {
 529             bar.vm = wait_imm::unset_counter;
 530             bar_ev &= ~(vm_events & ~event_flat);
 531          }
 532          if (bar.lgkm != wait_imm::unset_counter && imm.lgkm <= bar.lgkm) {
 533             bar.lgkm = wait_imm::unset_counter;
 534             bar_ev &= ~(lgkm_events & ~event_flat);
 535          }
 536          if (bar.vs != wait_imm::unset_counter && imm.vs <= bar.vs) {
 537             bar.vs = wait_imm::unset_counter;
 538             bar_ev &= ~vs_events;
 539          }
 540          if (bar.vm == wait_imm::unset_counter && bar.lgkm == wait_imm::unset_counter)
 541             bar_ev &= ~event_flat;
 542       }
 543
 544       /* remove all gprs with higher counter from map */
 545       std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.begin();
 546       while (it != ctx.gpr_map.end())
 547       {
 548          if (imm.exp != wait_imm::unset_counter && imm.exp <= it->second.imm.exp)
 549             ctx.wait_and_remove_from_entry(it->first, it->second, counter_exp);
 550          if (imm.vm != wait_imm::unset_counter && imm.vm <= it->second.imm.vm)
 551             ctx.wait_and_remove_from_entry(it->first, it->second, counter_vm);
 552          if (imm.lgkm != wait_imm::unset_counter && imm.lgkm <= it->second.imm.lgkm)
 553             ctx.wait_and_remove_from_entry(it->first, it->second, counter_lgkm);
 554          if (imm.vs != wait_imm::unset_counter && imm.vs <= it->second.imm.vs)
 555             ctx.wait_and_remove_from_entry(it->first, it->second, counter_vs);
 556          if (!it->second.counters)
 557             it = ctx.gpr_map.erase(it);
 558          else
 559             it++;
 560       }
 561    }
 562
 563    if (imm.vm == 0)
 564       ctx.pending_flat_vm = false;
 565    if (imm.lgkm == 0) {
 566       ctx.pending_flat_lgkm = false;
 567       ctx.pending_s_buffer_store = false;
 568    }
 569
 570    return imm;
 571 }
 572
 573 void update_barrier_counter(uint8_t *ctr, unsigned max)
 574 {
 575    if (*ctr != wait_imm::unset_counter && *ctr < max)
 576       (*ctr)++;
 577 }
 578
 579 void update_barrier_imm(wait_ctx& ctx, uint8_t counters, wait_event event, memory_sync_info sync)
 580 {
 581    for (unsigned i = 0; i < storage_count; i++) {
 582       wait_imm& bar = ctx.barrier_imm[i];
 583       uint16_t& bar_ev = ctx.barrier_events[i];
 584       if (sync.storage & (1 << i) && !(sync.semantics & semantic_private)) {
 585          bar_ev |= event;
 586          if (counters & counter_lgkm)
 587             bar.lgkm = 0;
 588          if (counters & counter_vm)
 589             bar.vm = 0;
 590          if (counters & counter_exp)
 591             bar.exp = 0;
 592          if (counters & counter_vs)
 593             bar.vs = 0;
 594       } else if (!(bar_ev & ctx.unordered_events) && !(ctx.unordered_events & event)) {
 595          if (counters & counter_lgkm && (bar_ev & lgkm_events) == event)
 596             update_barrier_counter(&bar.lgkm, ctx.max_lgkm_cnt);
 597          if (counters & counter_vm && (bar_ev & vm_events) == event)
 598             update_barrier_counter(&bar.vm, ctx.max_vm_cnt);
 599          if (counters & counter_exp && (bar_ev & exp_events) == event)
 600             update_barrier_counter(&bar.exp, ctx.max_exp_cnt);
 601          if (counters & counter_vs && (bar_ev & vs_events) == event)
 602             update_barrier_counter(&bar.vs, ctx.max_vs_cnt);
 603       }
 604    }
 605 }
 606
 607 void update_counters(wait_ctx& ctx, wait_event event, memory_sync_info sync=memory_sync_info())
 608 {
 609    uint8_t counters = get_counters_for_event(event);
 610
 611    if (counters & counter_lgkm && ctx.lgkm_cnt <= ctx.max_lgkm_cnt)
 612       ctx.lgkm_cnt++;
 613    if (counters & counter_vm && ctx.vm_cnt <= ctx.max_vm_cnt)
 614       ctx.vm_cnt++;
 615    if (counters & counter_exp && ctx.exp_cnt <= ctx.max_exp_cnt)
 616       ctx.exp_cnt++;
 617    if (counters & counter_vs && ctx.vs_cnt <= ctx.max_vs_cnt)
 618       ctx.vs_cnt++;
 619
 620    update_barrier_imm(ctx, counters, event, sync);
 621
 622    if (ctx.unordered_events & event)
 623       return;
 624
 625    if (ctx.pending_flat_lgkm)
 626       counters &= ~counter_lgkm;
 627    if (ctx.pending_flat_vm)
 628       counters &= ~counter_vm;
 629
 630    for (std::pair<const PhysReg,wait_entry>& e : ctx.gpr_map) {
 631       wait_entry& entry = e.second;
 632
 633       if (entry.events & ctx.unordered_events)
 634          continue;
 635
 636       assert(entry.events);
 637
 638       if ((counters & counter_exp) && (entry.events & exp_events) == event && entry.imm.exp < ctx.max_exp_cnt)
 639          entry.imm.exp++;
 640       if ((counters & counter_lgkm) && (entry.events & lgkm_events) == event && entry.imm.lgkm < ctx.max_lgkm_cnt)
 641          entry.imm.lgkm++;
 642       if ((counters & counter_vm) && (entry.events & vm_events) == event && entry.imm.vm < ctx.max_vm_cnt)
 643          entry.imm.vm++;
 644       if ((counters & counter_vs) && (entry.events & vs_events) == event && entry.imm.vs < ctx.max_vs_cnt)
 645          entry.imm.vs++;
 646    }
 647 }
 648
 649 void update_counters_for_flat_load(wait_ctx& ctx, memory_sync_info sync=memory_sync_info())
 650 {
 651    assert(ctx.chip_class < GFX10);
 652
 653    if (ctx.lgkm_cnt <= ctx.max_lgkm_cnt)
 654       ctx.lgkm_cnt++;
 655    if (ctx.vm_cnt <= ctx.max_vm_cnt)
 656       ctx.vm_cnt++;
 657
 658    update_barrier_imm(ctx, counter_vm | counter_lgkm, event_flat, sync);
 659
 660    for (std::pair<PhysReg,wait_entry> e : ctx.gpr_map)
 661    {
 662       if (e.second.counters & counter_vm)
 663          e.second.imm.vm = 0;
 664       if (e.second.counters & counter_lgkm)
 665          e.second.imm.lgkm = 0;
 666    }
 667    ctx.pending_flat_lgkm = true;
 668    ctx.pending_flat_vm = true;
 669 }
 670
 671 void insert_wait_entry(wait_ctx& ctx, PhysReg reg, RegClass rc, wait_event event, bool wait_on_read,
 672                        bool has_sampler=false)
 673 {
 674    uint16_t counters = get_counters_for_event(event);
 675    wait_imm imm;
 676    if (counters & counter_lgkm)
 677       imm.lgkm = 0;
 678    if (counters & counter_vm)
 679       imm.vm = 0;
 680    if (counters & counter_exp)
 681       imm.exp = 0;
 682    if (counters & counter_vs)
 683       imm.vs = 0;
 684
 685    wait_entry new_entry(event, imm, !rc.is_linear(), wait_on_read);
 686    new_entry.has_vmem_nosampler = (event & event_vmem) && !has_sampler;
 687    new_entry.has_vmem_sampler = (event & event_vmem) && has_sampler;
 688
 689    for (unsigned i = 0; i < rc.size(); i++) {
 690       auto it = ctx.gpr_map.emplace(PhysReg{reg.reg()+i}, new_entry);
 691       if (!it.second)
 692          it.first->second.join(new_entry);
 693    }
 694
 695    if (ctx.collect_statistics) {
 696       unsigned counters_todo = counters;
 697       while (counters_todo) {
 698          unsigned i = u_bit_scan(&counters_todo);
 699          ctx.unwaited_instrs[i].insert(std::make_pair(ctx.gen_instr, 0u));
 700          for (unsigned j = 0; j < rc.size(); j++)
 701             ctx.reg_instrs[i][PhysReg{reg.reg()+j}].insert(ctx.gen_instr);
 702       }
 703    }
 704 }
 705
 706 void insert_wait_entry(wait_ctx& ctx, Operand op, wait_event event, bool has_sampler=false)
 707 {
 708    if (!op.isConstant() && !op.isUndefined())
 709       insert_wait_entry(ctx, op.physReg(), op.regClass(), event, false, has_sampler);
 710 }
 711
 712 void insert_wait_entry(wait_ctx& ctx, Definition def, wait_event event, bool has_sampler=false)
 713 {
 714    insert_wait_entry(ctx, def.physReg(), def.regClass(), event, true, has_sampler);
 715 }
 716
 717 void gen(Instruction* instr, wait_ctx& ctx)
 718 {
 719    switch (instr->format) {
 720    case Format::EXP: {
 721       Export_instruction* exp_instr = static_cast<Export_instruction*>(instr);
 722
 723       wait_event ev;
 724       if (exp_instr->dest <= 9)
 725          ev = event_exp_mrt_null;
 726       else if (exp_instr->dest <= 15)
 727          ev = event_exp_pos;
 728       else
 729          ev = event_exp_param;
 730       update_counters(ctx, ev);
 731
 732       /* insert new entries for exported vgprs */
 733       for (unsigned i = 0; i < 4; i++)
 734       {
 735          if (exp_instr->enabled_mask & (1 << i)) {
 736             unsigned idx = exp_instr->compressed ? i >> 1 : i;
 737             assert(idx < exp_instr->operands.size());
 738             insert_wait_entry(ctx, exp_instr->operands[idx], ev);
 739
 740          }
 741       }
 742       insert_wait_entry(ctx, exec, s2, ev, false);
 743       break;
 744    }
 745    case Format::FLAT: {
 746       FLAT_instruction *flat = static_cast<FLAT_instruction*>(instr);
 747       if (ctx.chip_class < GFX10 && !instr->definitions.empty())
 748          update_counters_for_flat_load(ctx, flat->sync);
 749       else
 750          update_counters(ctx, event_flat, flat->sync);
 751
 752       if (!instr->definitions.empty())
 753          insert_wait_entry(ctx, instr->definitions[0], event_flat);
 754       break;
 755    }
 756    case Format::SMEM: {
 757       SMEM_instruction *smem = static_cast<SMEM_instruction*>(instr);
 758       update_counters(ctx, event_smem, smem->sync);
 759
 760       if (!instr->definitions.empty())
 761          insert_wait_entry(ctx, instr->definitions[0], event_smem);
 762       else if (ctx.chip_class >= GFX10 &&
 763                !smem->sync.can_reorder())
 764          ctx.pending_s_buffer_store = true;
 765
 766       break;
 767    }
 768    case Format::DS: {
 769       DS_instruction *ds = static_cast<DS_instruction*>(instr);
 770       update_counters(ctx, ds->gds ? event_gds : event_lds, ds->sync);
 771       if (ds->gds)
 772          update_counters(ctx, event_gds_gpr_lock);
 773
 774       if (!instr->definitions.empty())
 775          insert_wait_entry(ctx, instr->definitions[0], ds->gds ? event_gds : event_lds);
 776
 777       if (ds->gds) {
 778          for (const Operand& op : instr->operands)
 779             insert_wait_entry(ctx, op, event_gds_gpr_lock);
 780          insert_wait_entry(ctx, exec, s2, event_gds_gpr_lock, false);
 781       }
 782       break;
 783    }
 784    case Format::MUBUF:
 785    case Format::MTBUF:
 786    case Format::MIMG:
 787    case Format::GLOBAL: {
 788       wait_event ev = !instr->definitions.empty() || ctx.chip_class < GFX10 ? event_vmem : event_vmem_store;
 789       update_counters(ctx, ev, get_sync_info(instr));
 790
 791       bool has_sampler = instr->format == Format::MIMG && !instr->operands[1].isUndefined() && instr->operands[1].regClass() == s4;
 792
 793       if (!instr->definitions.empty())
 794          insert_wait_entry(ctx, instr->definitions[0], ev, has_sampler);
 795
 796       if (ctx.chip_class == GFX6 &&
 797           instr->format != Format::MIMG &&
 798           instr->operands.size() == 4) {
 799          ctx.exp_cnt++;
 800          update_counters(ctx, event_vmem_gpr_lock);
 801          insert_wait_entry(ctx, instr->operands[3], event_vmem_gpr_lock);
 802       } else if (ctx.chip_class == GFX6 &&
 803                  instr->format == Format::MIMG &&
 804                  instr->operands[1].regClass().type() == RegType::vgpr) {
 805          ctx.exp_cnt++;
 806          update_counters(ctx, event_vmem_gpr_lock);
 807          insert_wait_entry(ctx, instr->operands[1], event_vmem_gpr_lock);
 808       }
 809
 810       break;
 811    }
 812    case Format::SOPP: {
 813       if (instr->opcode == aco_opcode::s_sendmsg ||
 814           instr->opcode == aco_opcode::s_sendmsghalt)
 815          update_counters(ctx, event_sendmsg);
 816    }
 817    default:
 818       break;
 819    }
 820 }
 821
 822 void emit_waitcnt(wait_ctx& ctx, std::vector<aco_ptr<Instruction>>& instructions, wait_imm imm)
 823 {
 824    if (imm.vs != wait_imm::unset_counter) {
 825       assert(ctx.chip_class >= GFX10);
 826       SOPK_instruction* waitcnt_vs = create_instruction<SOPK_instruction>(aco_opcode::s_waitcnt_vscnt, Format::SOPK, 0, 1);
 827       waitcnt_vs->definitions[0] = Definition(sgpr_null, s1);
 828       waitcnt_vs->imm = imm.vs;
 829       instructions.emplace_back(waitcnt_vs);
 830       imm.vs = wait_imm::unset_counter;
 831    }
 832    if (!imm.empty()) {
 833       SOPP_instruction* waitcnt = create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt, Format::SOPP, 0, 0);
 834       waitcnt->imm = imm.pack(ctx.chip_class);
 835       waitcnt->block = -1;
 836       instructions.emplace_back(waitcnt);
 837    }
 838 }
 839
 840 void handle_block(Program *program, Block& block, wait_ctx& ctx)
 841 {
 842    std::vector<aco_ptr<Instruction>> new_instructions;
 843
 844    wait_imm queued_imm;
 845
 846    for (aco_ptr<Instruction>& instr : block.instructions) {
 847       bool is_wait = !parse_wait_instr(ctx, instr.get()).empty();
 848
 849       memory_sync_info sync_info = get_sync_info(instr.get());
 850       queued_imm.combine(kill(instr.get(), ctx, sync_info));
 851
 852       ctx.gen_instr = instr.get();
 853       gen(instr.get(), ctx);
 854
 855       if (instr->format != Format::PSEUDO_BARRIER && !is_wait) {
 856          if (!queued_imm.empty()) {
 857             emit_waitcnt(ctx, new_instructions, queued_imm);
 858             queued_imm = wait_imm();
 859          }
 860          new_instructions.emplace_back(std::move(instr));
 861
 862          queued_imm.combine(perform_barrier(ctx, sync_info, semantic_acquire));
 863
 864          if (ctx.collect_statistics)
 865             ctx.advance_unwaited_instrs();
 866       }
 867    }
 868
 869    if (!queued_imm.empty())
 870       emit_waitcnt(ctx, new_instructions, queued_imm);
 871
 872    block.instructions.swap(new_instructions);
 873 }
 874
 875 } /* end namespace */
 876
 877 static uint32_t calculate_score(std::vector<wait_ctx> &ctx_vec, uint32_t event_mask)
 878 {
 879    double result = 0.0;
 880    unsigned num_waits = 0;
 881    while (event_mask) {
 882       unsigned event_index = u_bit_scan(&event_mask);
 883       for (const wait_ctx &ctx : ctx_vec) {
 884          for (unsigned dist : ctx.wait_distances[event_index]) {
 885             double score = dist;
 886             /* for many events, excessive distances provide little benefit, so
 887              * decrease the score in that case. */
 888             double threshold = INFINITY;
 889             double inv_strength = 0.000001;
 890             switch (1 << event_index) {
 891             case event_smem:
 892                threshold = 70.0;
 893                inv_strength = 75.0;
 894                break;
 895             case event_vmem:
 896             case event_vmem_store:
 897             case event_flat:
 898                threshold = 230.0;
 899                inv_strength = 150.0;
 900                break;
 901             case event_lds:
 902                threshold = 16.0;
 903                break;
 904             default:
 905                break;
 906             }
 907             if (score > threshold) {
 908                score -= threshold;
 909                score = threshold + score / (1.0 + score / inv_strength);
 910             }
 911
 912             /* we don't want increases in high scores to hide decreases in low scores,
 913              * so raise to the power of 0.1 before averaging. */
 914             result += pow(score, 0.1);
 915             num_waits++;
 916          }
 917       }
 918    }
 919    return round(pow(result / num_waits, 10.0) * 10.0);
 920 }
 921
 922 void insert_wait_states(Program* program)
 923 {
 924    /* per BB ctx */
 925    std::vector<bool> done(program->blocks.size());
 926    std::vector<wait_ctx> in_ctx(program->blocks.size(), wait_ctx(program));
 927    std::vector<wait_ctx> out_ctx(program->blocks.size(), wait_ctx(program));
 928
 929    std::stack<unsigned> loop_header_indices;
 930    unsigned loop_progress = 0;
 931
 932    for (unsigned i = 0; i < program->blocks.size();) {
 933       Block& current = program->blocks[i++];
 934       wait_ctx ctx = in_ctx[current.index];
 935
 936       if (current.kind & block_kind_loop_header) {
 937          loop_header_indices.push(current.index);
 938       } else if (current.kind & block_kind_loop_exit) {
 939          bool repeat = false;
 940          if (loop_progress == loop_header_indices.size()) {
 941             i = loop_header_indices.top();
 942             repeat = true;
 943          }
 944          loop_header_indices.pop();
 945          loop_progress = std::min<unsigned>(loop_progress, loop_header_indices.size());
 946          if (repeat)
 947             continue;
 948       }
 949
 950       bool changed = false;
 951       for (unsigned b : current.linear_preds)
 952          changed |= ctx.join(&out_ctx[b], false);
 953       for (unsigned b : current.logical_preds)
 954          changed |= ctx.join(&out_ctx[b], true);
 955
 956       if (done[current.index] && !changed) {
 957          in_ctx[current.index] = std::move(ctx);
 958          continue;
 959       } else {
 960          in_ctx[current.index] = ctx;
 961       }
 962
 963       if (current.instructions.empty()) {
 964          out_ctx[current.index] = std::move(ctx);
 965          continue;
 966       }
 967
 968       loop_progress = std::max<unsigned>(loop_progress, current.loop_nest_depth);
 969       done[current.index] = true;
 970
 971       handle_block(program, current, ctx);
 972
 973       out_ctx[current.index] = std::move(ctx);
 974    }
 975
 976    if (program->collect_statistics) {
 977       program->statistics[statistic_vmem_score] =
 978          calculate_score(out_ctx, event_vmem | event_flat | event_vmem_store);
 979       program->statistics[statistic_smem_score] =
 980          calculate_score(out_ctx, event_smem);
 981    }
 982 }
 983
 984 }
 985